ARM: tegra: Add barriers after cache operations
authorAmit Kamath <akamath@nvidia.com>
Tue, 29 Jan 2013 10:09:58 +0000 (15:09 +0530)
committerRiham Haidar <rhaidar@nvidia.com>
Wed, 30 Jan 2013 20:03:23 +0000 (12:03 -0800)
commit997c54686349728cdf54cfeae96b5f4078ccb436
tree6ccacfd69076b911f472288f1bb875b20be5a037
parentd6f3ddb423827893ea586c5668a56ead5deb87d2
ARM: tegra: Add barriers after cache operations

memory and instruction barriers are needed after the tlb is
invalidated and BTAC is flushed as per ARM TRM. Without this
there is a invalid page translation in some cases.

Bug 1189280

Change-Id: I85e297ffd9245c5066f656bbb70ea257b8b3b317
Signed-off-by: Amit Kamath <akamath@nvidia.com>
Reviewed-on: http://git-master/r/195070
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
arch/arm/mach-tegra/sleep.S