[ARM] tegra: fix packet alignment and padding
authorGary King <gking@nvidia.com>
Wed, 28 Jul 2010 22:03:57 +0000 (15:03 -0700)
committerDan Willemsen <dwillemsen@nvidia.com>
Thu, 1 Dec 2011 05:34:57 +0000 (21:34 -0800)
commit98ac498cd9c8719f56808d9b1af50a6036615964
treef9e0f264068da83b49d5f42c8a22a03366adb952
parent9a84745ee9c4f2952101bfaa15bb2adb3e099e96
[ARM] tegra: fix packet alignment and padding

tegra's DMA controller expects to start transfers at word boundaries,
and the standard packet alignment (2) was resulting in data corruption

also, provide a full cacheline of padding between skbuffs, to eliminate
coherency issues between the processor and USB networking devices.

Change-Id: Ibb508b512f43c8934d35eb182c8738370b7be585
Signed-off-by: Gary King <gking@nvidia.com>
arch/arm/mach-tegra/include/mach/memory.h