arm: tegra: xmm: simultaneous L3 to L0 wakeup
authorVinayak Pane <vpane@nvidia.com>
Fri, 27 Apr 2012 22:01:05 +0000 (15:01 -0700)
committerSimone Willett <swillett@nvidia.com>
Mon, 21 May 2012 18:41:37 +0000 (11:41 -0700)
commit9874f9572f416e190befce95e0c53df4e0a62645
tree089601671745f5a5155f0b901e92d46f4dc04532
parent611caa58525e80f46eaf6990b68a7aa82f4f3dfa
arm: tegra: xmm: simultaneous L3 to L0 wakeup

In AP initiated L3->L0 wakeup xmm power state is set BBXMM_PS_L3TOL0
but if CP is also trying to wakeup then ipc_ap_wake_irq with falling
edge treats it incorrectly as CP wakeup pending - new race condition.

Adding a check to fix this scenario for both L3 and L3TOL0 states.

Bug 966077

Change-Id: I3af3538b48745588f17e4c13a3e23e4033f21821
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/102698
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Steve Lin <stlin@nvidia.com>
arch/arm/mach-tegra/baseband-xmm-power.c