x86, cpu: Package Level Thermal Control, Power Limit Notification definitions
authorFenghua Yu <fenghua.yu@intel.com>
Fri, 30 Jul 2010 00:13:42 +0000 (17:13 -0700)
committerH. Peter Anvin <hpa@linux.intel.com>
Fri, 30 Jul 2010 23:15:32 +0000 (16:15 -0700)
commit9792db6174d9927700ed288e6d74b9391bf785d1
tree2a77654e13de14ec945abb38b5e19f2699bea0be
parenta5b91606bdc9d0a0d036d2d829a22921c705573e
x86, cpu: Package Level Thermal Control, Power Limit Notification definitions

Add package level thermal and power limit feature support.

The two MSRs and features are new starting with Intel's Sandy Bridge processor.

Please check Intel 64 and IA-32 Architectures SDMV Vol 3A 14.5.6 Power Limit
Notification and 14.6 Package Level Thermal Management.

This patch also fixes a bug which defines reverse THERM_INT_LOW_ENABLE bit and
THERM_INT_HIGH_ENABLE bit.

[ hpa: fixed up against current tip:x86/cpu ]

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
LKML-Reference: <1280448826-12004-2-git-send-email-fenghua.yu@intel.com>
Reviewed-by: Len Brown <len.brown@intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
arch/x86/include/asm/cpufeature.h
arch/x86/include/asm/msr-index.h
arch/x86/kernel/cpu/scattered.c