ARM: tegra: More accurate name for LP2 functions
authorBo Yan <byan@nvidia.com>
Mon, 1 Oct 2012 18:59:50 +0000 (11:59 -0700)
committerSimone Willett <swillett@nvidia.com>
Tue, 23 Oct 2012 01:40:28 +0000 (18:40 -0700)
commit976c82355f79b2d38efeeb56e9c712e477601d2d
tree0d7aa7a1a080d1ced24ae3cbc4dae57df33d8660
parent1b2161f3157b7fd740752ab49616322914f1d3a6
ARM: tegra: More accurate name for LP2 functions

Starting from tegra3, the LP2 is no longer an appropriate name
for a particular CPU power state. LP2 on CPU0 means rail-gating,
LP2 on slave CPUs means power-gating. Starting from tegra11x,
even CPU0 can do power gating.

This changes function names to reflect the fact that the rail-gating
is a cluster-wide power state, and power gating is a per-CPU core
power state.

Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/140704
(cherry picked from commit 885c9b26a07b2b8f5b05be3cf3e9dcda60a92157)

Change-Id: Icd1bd75494c17d18aecaea2a5177ca0a12df0ca1
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146480
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit
arch/arm/mach-tegra/cpuidle-t3.c