ARM: dts: tegratab: pclk change
authorMin-wuk Lee <mlee@nvidia.com>
Tue, 2 Jul 2013 07:49:24 +0000 (16:49 +0900)
committerGabby Lee <galee@nvidia.com>
Sun, 13 Oct 2013 23:31:23 +0000 (16:31 -0700)
commit94245960b68f75e85b782e4baf93d344542b8edf
tree2ce154e0db2940dfe33ce52431728d5faac2ab73
parent8fd4d6be639e6a37d663739e082a6d0adda7b55f
ARM: dts: tegratab: pclk change

Before LP0 entry, pclk in tegra_dc_mode struct is referred to.
After LP0 exit, pclk is calculated with dc timing.
Because pclk is set differently, required emc bandwidth is
calculated differently as well beween two cases.

<Without this change>
Before LP0 entry
disp1.emc         $ on     1            102000000  (17751000+)

After LP0 exit
disp1.emc         $ on     1            102000000  (17667000+)

<With this change>
Before LP0 entry
disp1.emc         $ on     1            102000000  (17667000+)

After LP0 exit
disp1.emc         $ on     1            102000000  (17667000+)

Bug 1301312

Change-Id: Ibab5ed84d5c91f935884fb119ca1bac2d6ce68fa
Signed-off-by: Min-wuk Lee <mlee@nvidia.com>
Reviewed-on: http://git-master/r/244211
(cherry picked from commit 12d77a24d7b8bcc904d86a83578230c0edc323b1)
Reviewed-on: http://git-master/r/289745
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Gabby Lee <galee@nvidia.com>
Tested-by: Gabby Lee <galee@nvidia.com>
arch/arm/boot/dts/tegra114-tegratab-ers.dts
arch/arm/boot/dts/tegra114-tegratab.dts