ARM: tegra11: clock: Update DFLL switch error handling
authorAlex Frid <afrid@nvidia.com>
Thu, 11 Oct 2012 02:35:44 +0000 (19:35 -0700)
committerSimone Willett <swillett@nvidia.com>
Mon, 22 Oct 2012 20:59:55 +0000 (13:59 -0700)
commit911ab103724f15fe4e1dd2167a26b3a9442c3d37
tree746aea13280e17dd81f493002225845456adcfbd
parent905bfb114b30d7279178d9e1a51dd870ab6a2da7
ARM: tegra11: clock: Update DFLL switch error handling

The changes below provide WAR for possible I2C deadlock if CL-DVFS
output is disabled while the I2C request is pending.

- Switch to Open Loop mode at the beginning of unlocking API (this
guarantees at most 2 outstanding transaction), drain pending (if any)
transactions, and then disable output.

- Separated cl_dvfs output_enable() and output_disable() operations.
Swap the order of waiting for output interface quiet and disabling
the output: first wait for quiet interface, and then disable output.
Re-enable interface if pending request is set again and continue
waiting until quiet state is confirmed or timeout is expired. Passed
timeout error to the caller of unlocking API.

- When switching CPU clock source from DFLL to PLL, restore DFLL
clock source and DFLL rail control in case of switch error,
including unlock timeout error.

- When switching from CPU G mode to CPU LP mode, re-lock DFLL in
case of switch error, including unlock timeout error.

- When switching CPU clock source from PLL to DFLL, move control
of VDD_CPU rail to DFLL even if it failed to lock (lock failure
should never happen here, and WARN() will be replaced with BUG()).

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/144305
(cherry picked from commit 6c2782755b082b005fc7ce8e82e9f051e64bfbf1)

Change-Id: I4b4229f2737eed9bdffca2efbd08fc9a5ac058e3
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146282
Reviewed-by: Automatic_Commit_Validation_User
arch/arm/mach-tegra/tegra11_clocks.c
arch/arm/mach-tegra/tegra_cl_dvfs.c