ARM: tegra: clock: Support restricted PLLM usage
authorAlex Frid <afrid@nvidia.com>
Sat, 12 Nov 2011 02:19:16 +0000 (18:19 -0800)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 24 Mar 2012 04:04:53 +0000 (21:04 -0700)
commit8a9edf48ed52eab8141571c276b8ed4e3a6963f7
treeaa87835c95b6d9604f652118c408023989dd4e76
parent2a1395764cc1a49798f8f60b3bfd129a37d34b03
ARM: tegra: clock: Support restricted PLLM usage

Added configuration option TEGRA_PLLM_RESTRICTED - when enabled,
PLLM - memory PLL - usage may be restricted to modules with dividers
capable of dividing maximum PLLM frequency at minimum voltage. When
disabled, PLLM is available as a clock source with no restrictions
(current configuration), which may effectively increase lower limit
for core voltage if high grade SDRAM is used.

Implemented PLLM restrictions in Tegra3 clock framework and DVFS, but
keep them disabled by default.

Bug 884419

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 5313ebcae92839146870d5865bc0f4cd08b35c61)
(cherry picked from commit 634647a9d2a8c1e03c8d98d0b2199950c947acc3)

Change-Id: I012452d92830ad6b63ec407350568b8c316b3caa
Reviewed-on: http://git-master/r/66512
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>

Rebase-Id: R769a8c4d8bffd675ecc703bc9d2d655ba24615ea
arch/arm/mach-tegra/board-enterprise.c