mmc: tegra: Fix SDR50 mode clock rate setting
authorPavan Kunapuli <pkunapuli@nvidia.com>
Wed, 9 May 2012 12:44:51 +0000 (17:44 +0530)
committerSimone Willett <swillett@nvidia.com>
Fri, 11 May 2012 21:11:49 +0000 (14:11 -0700)
commit881cc68b78cb8b188222ecb29205f5b601a8b2e5
tree494ed60d461fe79f1a009d4cba185af115ed683b
parent6ef470d530c3ce43151b61de1b32d73d2a60b3a6
mmc: tegra: Fix SDR50 mode clock rate setting

In SDR50 mode, set the controller clock to double
the requested clock to ensure that the core voltage
is maintained at a min of 1.2V.

Bug 965298

Change-Id: I557a07de97efd6b44f812a11da657e03d3ddefd0
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/101522
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
drivers/mmc/host/sdhci-tegra.c