regmap: irq: Add mask invert flag for enable register
authorXiaofan Tian <tianxf@marvell.com>
Thu, 30 Aug 2012 09:03:35 +0000 (17:03 +0800)
committerSimone Willett <swillett@nvidia.com>
Wed, 7 Nov 2012 02:29:03 +0000 (18:29 -0800)
commit82cb86ac5befc989a87710af4b283c48e0f162b4
tree801593a89fa262295d1c4f56aeb5e0b82f71660e
parentbdb711f75a366b909867f2cef596fd0fb0f6d7e9
regmap: irq: Add mask invert flag for enable register

Currently, regmap will write 1 to mask_base to mask
an interrupt and write 0 to unmask it.

But some chips do not have an interrupt mask register,
and only have interrupt enable register.
Then we should write 0 to disable interrupt and 1 to enable.

So add an mask_invert flag to handle this.
If it is not set, behavior is same as previous.
If set it to 1, the mask value will be inverted
before written to mask_base

Change-Id: I1c6875de71e0b9b9a89a23c1669638df4dfe541e
Signed-off-by: Xiaofan Tian <tianxf@marvell.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/161554
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit
drivers/base/regmap/regmap-irq.c
include/linux/regmap.h