ARM: tegra: cardhu: Specify PLLD2 as backup clock source
authorAlex Frid <afrid@nvidia.com>
Sun, 15 Jan 2012 06:54:23 +0000 (22:54 -0800)
committerRohan Somvanshi <rsomvanshi@nvidia.com>
Tue, 24 Jan 2012 18:57:58 +0000 (10:57 -0800)
commit7d33bebaf50ad911bfa85668040a4ca42150ca09
treecf97bff611c2f330f731d83f25ce70a7c1fe919a
parent3a74a9a1c0f6337f5c970de4d890f8f6841dc12f
ARM: tegra: cardhu: Specify PLLD2 as backup clock source

Since not all possible PLLP output rates (216MHz, 408MHz or 204MHz)
can provide accurate enough pixel clock rate for cardhu panel, use
PLLD2 as backup clock source.

Bug 928260

Change-Id: I767e621606e849cb7d1976fbed198b9427660544
Reviewed-on: http://git-master/r/76034
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76816
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
arch/arm/mach-tegra/board-cardhu-panel.c