ARM: tegra: power: setup TTB0 for cacheable memory
authorJin Qian <jqian@nvidia.com>
Tue, 16 Aug 2011 02:32:23 +0000 (19:32 -0700)
committerDan Willemsen <dwillemsen@nvidia.com>
Thu, 1 Dec 2011 05:47:21 +0000 (21:47 -0800)
commit7b8232e71a72125f06bc3b1dbfdef36928e24ae6
treef8f2f5f4664e0a8653298e3480916b646a66d0a2
parentb20d7996604b924cd3fa2aa416b968c6e64d0d46
ARM: tegra: power: setup TTB0 for cacheable memory

Bug 862494

Change-Id: Ib7875ded150b3e9dc288a9ed90f6ded0a37014a3
Reviewed-on: http://git-master/r/47246
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R11be58a9cf3a46fadf985e209e26dc00a8d87c58
arch/arm/mach-tegra/pm.c