video: tegra: add 504MHz pll_d rate for HDMI
authorJoseph Lehrer <jlehrer@nvidia.com>
Wed, 22 Jun 2011 20:58:28 +0000 (13:58 -0700)
committerDan Willemsen <dwillemsen@nvidia.com>
Thu, 1 Dec 2011 05:48:00 +0000 (21:48 -0800)
commit6bf73fb46cc8badcec1540da8ab5de9f06af97c3
tree9bdc81ac5f165e1e70f6b4098449c7e36a109a10
parentd5506a49ce8b3e144375097d19494139488d15b5
video: tegra: add 504MHz pll_d rate for HDMI

To support the 25.2MHz pixel clock frequency required for CEA-861-B format 1: 640x480p at 59.94Hz

bug 837571

(cherry picked from commit d03e629f3f428d0666a559e8a5c5f94419107ad3)

Original-Change-Id: I4f12b9333f31a2df6b1029acf5faffb7802f170c
Reviewed-on: http://git-master/r/40380
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Re7907dc7bb4b61cd1af284a722a2b208d34e4687
drivers/video/tegra/dc/dc.c