arm: tegra: p1852: set FPDLink latch clock edge
authorDongfang Shi <dshi@nvidia.com>
Thu, 9 Aug 2012 19:22:27 +0000 (12:22 -0700)
committerSimone Willett <swillett@nvidia.com>
Wed, 29 Aug 2012 01:12:10 +0000 (18:12 -0700)
commit6bc9afa39a1d2a0b2c909fb019ca49d848d96d63
tree04f4f532f6e55e1e1c65b67349963774a2d71420
parente3d92859c4351847a98e48746fb19d12fac16c6d
arm: tegra: p1852: set FPDLink latch clock edge

Make parallel data strobed on rising clock edge
For SKU2 MODS get correct CRC.

Bug 995623

Change-Id: I70f4b87e781821cf4ff8370c17b79f5bea7dc55c
Signed-off-by: Dongfang Shi <dshi@nvidia.com>
Reviewed-on: http://git-master/r/121824
(cherry-pick from 5200d0f10b936e00dbc2a946eed8c2e48b039943)
Reviewed-on: http://git-master/r/122537
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bob Johnston <bjohnston@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
arch/arm/mach-tegra/board-p1852-panel.c