sdhci-tegra:Enabling LVL2_CLK_OVR for sdmmc1
authorPavan Kunapuli <pkunapuli@nvidia.com>
Sat, 29 Jan 2011 03:17:33 +0000 (19:17 -0800)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 24 Mar 2012 02:56:46 +0000 (19:56 -0700)
commit69829fc8eb47d0d8956336c479242aaf6cdb99b9
treee40cde36ea81250fc3d45f91c73d853c983d4b28
parente1e01430eaa0557b11feed251dd924053907a50e
sdhci-tegra:Enabling LVL2_CLK_OVR for sdmmc1

Enabling LVL2 CLK OVR bit for sdmmc1.
Disabling cd and wp gpios for sdmmc1.
Enabling vddio_sdmmc1 using regulator and
setting the voltage to 3.3V.
Using clk_m for sdmmc1.

Original-Change-Id: Id38e2357c5cafe103b7607ef5adb4e7e9bc228d4
Reviewed-on: http://git-master/r/17212
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I89e4ab5b4cc501cf02eb800bc3acb49b0dba2519

Rebase-Id: R834679a3c750e41663510af164e8b36f5b1013ab
arch/arm/mach-tegra/board-cardhu-sdhci.c
arch/arm/mach-tegra/board-cardhu.c