i2c: tegra: Avoid duplicate write into Tx fifo
authorChaitanya Bandi <bandik@nvidia.com>
Mon, 12 Mar 2012 10:48:07 +0000 (15:48 +0530)
committerVarun Wadekar <vwadekar@nvidia.com>
Wed, 18 Apr 2012 04:09:23 +0000 (09:09 +0530)
commit67ee893a536aba15457b8198d75190a2b544b49d
tree7bec69c27bd870d9a85a7e033f8a454c3d1af018
parent2d69cd47eb3c3157062da1cb719924cc77de25ef
i2c: tegra: Avoid duplicate write into Tx fifo

Dvc I2C_DONE_INTR_EN interrupt bit is always enable into dvc
control register3. During normal transaction on dvc i2c bus
sometimes one transaction written two times in TX fifo buffer
because of triggered dvc interrupt. This is causing to corrupt
the next transaction header and send wrong address over dvc
i2c bus. To solve this issue dvc i2c interrupt has to disable
during filling of Tx fifo and enable after that.

Updated the following things in code:
(1) Add the code to mask/unmask I2C_DONE_INTR_EN into dvc control reg3
writing into Tx Fifo register.
(2) Put delay before resetting the controller

Hand-picked this change from: http://git-master/r/#change,39997
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>

Change-Id: I16b5821e1d0d0cf8419ce9d239e794de9d5b47be
Reviewed-on: http://git-master/r/89456
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
drivers/i2c/busses/i2c-tegra.c