mmc: tegra: Fix SDR50 clock rate configuration
authorPavan Kunapuli <pkunapuli@nvidia.com>
Wed, 27 Jun 2012 11:28:10 +0000 (16:28 +0530)
committerRohan Somvanshi <rsomvanshi@nvidia.com>
Thu, 19 Jul 2012 07:52:55 +0000 (00:52 -0700)
commit61c10696751004b4a6ceda1eb6acd247800a0eff
tree94b17026e81c65d0b214ebc12d2ec0cddb40f9e9
parent4c93dd529897db120a5b8151e04598ebc864f0d2
mmc: tegra: Fix SDR50 clock rate configuration

The host clock configuration in SDR50 mode is
incorrectly grouped with DDR50 mode due to which
DDR50 mode clock limits are wrongly applied even
in SDR50 mode.

Bug 965298

Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/111566
(cherry picked from commit 2ad290d477e8198bace22d2623856555f07b9bf9)

Change-Id: I5d3a446e39a349209e5842d385c1b728bfb7012e
Reviewed-on: http://git-master/r/116428
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
drivers/mmc/host/sdhci-tegra.c