drm/i915: fixup interlaced bits clearing in PIPECONF on PCH_SPLIT (v2)
authorKeith Packard <keithp@keithp.com>
Wed, 8 Feb 2012 21:53:38 +0000 (13:53 -0800)
committerKeith Packard <keithp@keithp.com>
Wed, 8 Feb 2012 21:54:18 +0000 (13:54 -0800)
commit617cf884810b44384fe8e9431e9babeb80a2ff37
tree53efc5b8d73dc556cb027304f596313c06d30749
parente57b6886f555ab57f40a01713304e2053efe51ec
drm/i915: fixup interlaced bits clearing in PIPECONF on PCH_SPLIT (v2)

An identical patch has been merged for i9xx_crtc_mode_set:

Commit 59df7b1771c150163e522f33c638096ab0efbf42
Author: Christian Schmidt <schmidt@digadd.de>
Date:   Mon Dec 19 20:03:33 2011 +0100

    drm/intel: Fix initialization if startup happens in interlaced mode [v2]

But that one neglected to fix up the ironlake+ path.

This should fix the issue reported by Alfonso Fiore where booting with
only a HDMI cable connected to his TV failed to display anything. The
issue is that the bios set up things for 1080i and used the pannel
fitter to scale up the lower progressive resolutions. We failed to
clear the interlace bit in the PIPEACONF register, resulting in havoc.

v2: Be more paranoid and just unconditionally clear the field before
setting new values.

Cc: Peter Ross <pross@xvid.org>
Cc: Alfonso Fiore <alfonso.fiore@gmail.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Signed-off-by: Keith Packard <keithp@keithp.com>
drivers/gpu/drm/i915/intel_display.c