Arm: Tegra3: clocks: Disabled SSCCENTER bit for plle
authorMohit Kataria <mkataria@nvidia.com>
Tue, 24 Apr 2012 07:33:54 +0000 (12:33 +0530)
committerSimone Willett <swillett@nvidia.com>
Fri, 25 May 2012 21:34:22 +0000 (14:34 -0700)
commit5f965f2c63d3e9c6b335d1f6337c83c1f5437739
tree845ba1fc2c30f2200198aad2c9c06a0960f9da8f
parenta5b582a0ad0cd078b059c68036406f9b7f1645ce
Arm: Tegra3: clocks: Disabled SSCCENTER bit for plle

Disabled SSCCENTRE bit for plle as per golden register
(value provided by syseng)

Bug 942384 978870

Change-Id: I3c2f8e8e220015b58f0c8bcbaac4e9998a5b6dcd
Reviewed-on: http://git-master/r/98381
Signed-off-by: Mohit Kataria <mkataria@nvidia.com>
Reviewed-on: http://git-master/r/102408
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
arch/arm/mach-tegra/tegra3_clocks.c