arm: tegra: macallan: set vdd_rtc to 950mV during lp0
authorKerwin Wan <kerwinw@nvidia.com>
Thu, 28 Mar 2013 10:17:16 +0000 (18:17 +0800)
committerRiham Haidar <rhaidar@nvidia.com>
Sat, 30 Mar 2013 03:39:08 +0000 (20:39 -0700)
commit599cee8c196fa219ddf408303212a77c7686447c
treea696eb6780f121e0a916ea0f2c08c896a7525d47
parentb13b0d6c8a6c04d96d5040568e6d1dd3665ef69e
arm: tegra: macallan: set vdd_rtc to 950mV during lp0

When vdd_rtc is set to 900mv, cpu will meet hard hang after
wake up from lp0. Hardware team should do WAT to get the proper margin
for vdd_rtc. Set vdd_rtc to 950mV to avoid this issue now.

Bug 1262674

Change-Id: Ic3ddfeb586a78e6731178bb6bd672dda0ae49566
Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/213967
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
arch/arm/mach-tegra/board-macallan-power.c