arm: tegra: cardhu: move VI to PLL_P
authorJihoon Bang <jbang@nvidia.com>
Fri, 29 Jun 2012 20:54:34 +0000 (13:54 -0700)
committerVarun Wadekar <vwadekar@nvidia.com>
Mon, 16 Jul 2012 12:31:58 +0000 (17:31 +0530)
commit5917c3c5c8eb676d1fe61fe42d22d617ce9fcf36
tree1940eabbe8e96265949511176fe4e4d688cd051b
parente1a742f4bb40d259cb5afe2bd86817075b494ff4
arm: tegra: cardhu: move VI to PLL_P

As a part of effort to bring in 437MHz clock frequency in EMC,
We need to move VI from PLL_M to PLL_P.

Bug 1005576

Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/112704
(cherry picked from commit c175857e80355857b55e8eb2012c12e94e532835)

Change-Id: Icd314c01625f5c4765b0215735ceafb7d3f25d1e
Reviewed-on: http://git-master/r/114241
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
arch/arm/mach-tegra/board-cardhu.c