mfd: tps80031: fix irq status clear sequence
authorDavid Schalig <dschalig@nvidia.com>
Wed, 14 Dec 2011 07:01:30 +0000 (16:01 +0900)
committerDan Willemsen <dwillemsen@nvidia.com>
Fri, 23 Mar 2012 07:52:27 +0000 (00:52 -0700)
commit3c7597f9a0be540f87d8188bd8a154a3ea9d6039
tree103c5e857178b7cb6a7c9a000f9dedd370e7c99a
parent865e09c99548b012c81f56941a5df93cc1911b3e
mfd: tps80031: fix irq status clear sequence

According to tps80031 datasheet, all 3 interrupt status registers should
be read, before writing to clear them. The old code used interleaved status
read/clear, which may drop interrupts.

Bug 914740

Change-Id: I4c9c0b7c623ea0fe01d90e9a531ff2e9d34f125c
Signed-off-by: David Schalig <dschalig@nvidia.com>
Reviewed-on: http://git-master/r/69941
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R3fdd7130e696888073ac1b065c44043263557566
drivers/mfd/tps80031.c