ARM: tegra11: dvfs: Update CPU dvfs tables and bins
authorAlex Frid <afrid@nvidia.com>
Wed, 12 Dec 2012 05:19:04 +0000 (21:19 -0800)
committerRohan Somvanshi <rsomvanshi@nvidia.com>
Tue, 18 Dec 2012 13:35:38 +0000 (05:35 -0800)
commit3bb08c690497976b8de5933db6ccce8d4541b08c
tree94d79d6d665cd2af731198c4257e19e0ca46c3c3
parentf115428fa770a05ee001917d430f238e600a8c9b
ARM: tegra11: dvfs: Update CPU dvfs tables and bins

Based on characterization results:
- Integrated new cvb dvfs coefficients
- Expanded DFLL operating voltage range to 0.9V ... 1.35V with
  1.0V as dynamic tuning threshold
- Added speedo_id 2 to differentiate fast parts
- Duplicated CPU EDP table for new speedo_id

Bug 1170986
Bug 1178825
Bug 1161126

Change-Id: I49ccdb7c3d734dcdd3bb9f2542683d418d21ab5f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/170368
(cherry picked from commit dbde7ee5f627874af256abe647fcf310e705d60c)
Reviewed-on: http://git-master/r/171629
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
arch/arm/mach-tegra/edp.c
arch/arm/mach-tegra/tegra11_dvfs.c
arch/arm/mach-tegra/tegra11_speedo.c