arm: tegra: p1852: Configure CPU_SOFTRST_CTRL
authorBhavesh Parekh <bparekh@nvidia.com>
Thu, 4 Oct 2012 09:57:52 +0000 (14:57 +0530)
committerRohan Somvanshi <rsomvanshi@nvidia.com>
Mon, 12 Nov 2012 11:09:29 +0000 (03:09 -0800)
commit3a68efbe7009e1c8ded95582b18287eba20d0fe8
tree6f6139f8ffce224979fd52dc28e571a68d217dc2
parentf54da068f7f4ddee838f6597ef5605a3939fc210
arm: tegra: p1852: Configure CPU_SOFTRST_CTRL

CPU_SOFTRST_CTRL register is used during cluster-switching. It tells the
delays for un-clamping and reset in term of sclk cycle

On P1852, we are running SCLK at 334MHz so we can't use the
reset value of this register.
Currently configuring the value with high number till we get proper
value from qual team

Bug 1051967
Bug 1010500

Reviewed-on: http://git-master/r/141524
(cherry picked from commit ac86e1d722cb4efd152bc3c335be7ce91205c88c)
Change-Id: I768b68c694543f7a3f2a6c4435e9829aeaeaa51c
Signed-off-by: Nitin Agrawal <nitina@nvidia.com>
Reviewed-on: http://git-master/r/146496
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
arch/arm/mach-tegra/board-p1852-power.c