ARM: tegra: power: Defer switch to 32kHz on LP1 entry
authorAlex Frid <afrid@nvidia.com>
Tue, 15 Jan 2013 05:20:56 +0000 (21:20 -0800)
committerSimone Willett <swillett@nvidia.com>
Fri, 18 Jan 2013 01:07:00 +0000 (17:07 -0800)
commit31615e1677a5e76ca90622cf2756aa09c0e17286
tree3636f303ee30d87ab8bc8b1be7db4d3404ce86f5
parent2b8d8704295e1aba2328559fa978750505535e49
ARM: tegra: power: Defer switch to 32kHz on LP1 entry

Deferred switching system clock to 32kHz source after all PLLs are
disabled. There is no need to slow down entry procedure by PLLs
manipulation in 32kHz domain.

Change-Id: I2cfad09f80baa9deda8626ae78cbfcc3326dc7d3
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/191111
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
arch/arm/mach-tegra/sleep-t3.S