ARM: kernel: update cpu_suspend code to use cache LoUIS operations
authorLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Fri, 7 Sep 2012 05:36:57 +0000 (10:36 +0530)
committerMrutyunjay Sawant <msawant@nvidia.com>
Tue, 30 Oct 2012 12:51:57 +0000 (05:51 -0700)
commit2fb1c645cf7f5568fa5ac83703fd630444307d29
treee5a05e3616c6d1107738252a070cde07919b43a9
parent5fd6a29b0c64c579b9605e5c80dacf5418b8ceaf
ARM: kernel: update cpu_suspend code to use cache LoUIS operations

In processors like A15/A7 L2 cache is unified and integrated within the
processor cache hierarchy, so that it is not considered an outer cache
anymore. For processors like A15/A7 flush_cache_all() ends up cleaning
all cache levels up to Level of Coherency (LoC) that includes
the L2 unified cache.

When a single CPU is suspended (CPU idle) a complete L2 clean is not
required, so generic cpu_suspend code must clean the data cache using the
newly introduced cache LoUIS function.

The context and stack pointer (context pointer) are cleaned to main memory
using cache area functions that operate on MVA and guarantee that the data
is written back to main memory (perform cache cleaning up to the Point of
Coherency - PoC) so that the processor can fetch the context when the MMU
is off in the cpu_resume code path.

outer_cache management remains unchanged.

Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Change-Id: I305b9d3bbb2def6f32d3d08769babd6a99798194
Reviewed-on: http://git-master/r/147783
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
arch/arm/kernel/suspend.c