ARM: tegra: power: Update PLL configuration in LP1 state
authorAlex Frid <afrid@nvidia.com>
Fri, 21 Dec 2012 04:34:33 +0000 (20:34 -0800)
committerSimone Willett <swillett@nvidia.com>
Fri, 18 Jan 2013 01:06:56 +0000 (17:06 -0800)
commit2b8d8704295e1aba2328559fa978750505535e49
tree99f946350046c8d2637db7b0d842e98be437ca1a
parenta20acde4e113eb936f60187a9cb707d99a834593
ARM: tegra: power: Update PLL configuration in LP1 state

- Put Tegra11 PLLs (PLLM, PLLC, PLLX) in IDDQ mode during LP1 state
- Made sure Tegra30 style PLL lock detect control is not applied to
Tegra11 PLLs (it was overwriting some unrelated Tegra11 bits)
- Added Tegra30 PLL lock detect reset pulse (Bug 1198457)

Change-Id: Ib14a86ffdc24144620f1dc18cf8a0c4c23b6b3e2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/191097
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
arch/arm/mach-tegra/sleep-t3.S