ARM: tegra20: pm: flush L1 data before exit coherency
authorPrashant Gaikwad <pgaikwad@nvidia.com>
Tue, 27 Mar 2012 12:10:35 +0000 (17:10 +0530)
committerSimone Willett <swillett@nvidia.com>
Fri, 6 Apr 2012 01:13:15 +0000 (18:13 -0700)
commit209209a303742d6312f66896b4351dd97e48e24c
treef9f9b53fdc95200eebc9c9dc4f0a7259f8019a5d
parent743c03fbeb5908faf4aef6bee7702a2ad4caac22
ARM: tegra20: pm: flush L1 data before exit coherency

Bug 934368

Change-Id: I960d8ae5c6390e719b8ee6c9cbc067cf8d28122d
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/92543
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
arch/arm/mach-tegra/sleep-t2.S