ARM: tegra: clock: Add Tegra3 0.95V core voltage step
authorAlex Frid <afrid@nvidia.com>
Tue, 10 Jan 2012 03:46:25 +0000 (19:46 -0800)
committerVarun Colbert <vcolbert@nvidia.com>
Fri, 20 Jan 2012 21:56:42 +0000 (13:56 -0800)
commit1faa1d5bd9db88b4e3656622ea81b48ca5b58367
treeb76fa2fee4a7f777a84ea136018112443b51f09e
parent937ed7672266b64988a86fdf30556f6fe75034da
ARM: tegra: clock: Add Tegra3 0.95V core voltage step

- Expanded Tegra3 DVFS tables with 0.95V core voltage step
- Updated cbus minimum rate calculation, since cbus can not
  run at 0.95V
- Updated PLLM dvfs initialization, since PLLM can no longer
  be voltage independent, even when its usage is restricted.

Bug 817679
Bug 841336

Change-Id: I4973dc19d351ce237f2b249ebf75a79abf3afef4
Reviewed-on: http://git-master/r/74141
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76463
Reviewed-by: Automatic_Commit_Validation_User
arch/arm/mach-tegra/tegra3_clocks.c
arch/arm/mach-tegra/tegra3_dvfs.c