mtd: sh_flctl SHBUSSEL and SEL_16BIT support
[linux-2.6.git] / include / linux / mtd / onenand_regs.h
index c46161f..cd6f3b4 100644 (file)
 /*
  * Device ID Register F001h (R)
  */
+#define DEVICE_IS_FLEXONENAND          (1 << 9)
+#define FLEXONENAND_PI_MASK            (0x3ff)
+#define FLEXONENAND_PI_UNLOCK_SHIFT    (14)
+#define ONENAND_DEVICE_DENSITY_MASK    (0xf)
 #define ONENAND_DEVICE_DENSITY_SHIFT   (4)
 #define ONENAND_DEVICE_IS_DDP          (1 << 3)
 #define ONENAND_DEVICE_IS_DEMUX                (1 << 2)
 #define ONENAND_VERSION_PROCESS_SHIFT  (8)
 
 /*
+ * Technology Register F006h (R)
+ */
+#define ONENAND_TECHNOLOGY_IS_MLC      (1 << 0)
+
+/*
  * Start Address 1 F100h (R/W) & Start Address 2 F101h (R/W)
  */
 #define ONENAND_DDP_SHIFT              (15)
 /*
  * Start Address 8 F107h (R/W)
  */
-#define ONENAND_FPA_MASK               (0x3f)
+/* Note: It's actually 0x3f in case of SLC */
+#define ONENAND_FPA_MASK               (0x7f)
 #define ONENAND_FPA_SHIFT              (2)
 #define ONENAND_FSA_MASK               (0x03)
 
 #define ONENAND_BSA_BOOTRAM            (0 << 2)
 #define ONENAND_BSA_DATARAM0           (2 << 2)
 #define ONENAND_BSA_DATARAM1           (3 << 2)
-#define ONENAND_BSC_MASK               (0x03)
+/* Note: It's actually 0x03 in case of SLC */
+#define ONENAND_BSC_MASK               (0x07)
 
 /*
  * Command Register F220h (R/W)
 #define ONENAND_CMD_LOCK_TIGHT         (0x2C)
 #define ONENAND_CMD_UNLOCK_ALL         (0x27)
 #define ONENAND_CMD_ERASE              (0x94)
+#define ONENAND_CMD_MULTIBLOCK_ERASE   (0x95)
+#define ONENAND_CMD_ERASE_VERIFY       (0x71)
 #define ONENAND_CMD_RESET              (0xF0)
 #define ONENAND_CMD_OTP_ACCESS         (0x65)
 #define ONENAND_CMD_READID             (0x90)
+#define FLEXONENAND_CMD_PI_UPDATE      (0x05)
+#define FLEXONENAND_CMD_PI_ACCESS      (0x66)
+#define FLEXONENAND_CMD_RECOVER_LSB    (0x05)
 
 /* NOTE: Those are not *REAL* commands */
 #define ONENAND_CMD_BUFFERRAM          (0x1978)
+#define FLEXONENAND_CMD_READ_PI                (0x1985)
 
 /*
  * System Configuration 1 Register F221h (R, R/W)
 #define ONENAND_SYS_CFG1_INT           (1 << 6)
 #define ONENAND_SYS_CFG1_IOBE          (1 << 5)
 #define ONENAND_SYS_CFG1_RDY_CONF      (1 << 4)
+#define ONENAND_SYS_CFG1_HF            (1 << 2)
+#define ONENAND_SYS_CFG1_SYNC_WRITE    (1 << 1)
 
 /*
  * Controller Status Register F240h (R)
 #define ONENAND_ECC_1BIT_ALL           (0x5555)
 #define ONENAND_ECC_2BIT               (1 << 1)
 #define ONENAND_ECC_2BIT_ALL           (0xAAAA)
+#define FLEXONENAND_UNCORRECTABLE_ERROR        (0x1010)
+#define ONENAND_ECC_3BIT               (1 << 2)
+#define ONENAND_ECC_4BIT               (1 << 3)
+#define ONENAND_ECC_4BIT_UNCORRECTABLE (0x1010)
 
 /*
  * One-Time Programmable (OTP)
  */
+#define FLEXONENAND_OTP_LOCK_OFFSET            (2048)
 #define ONENAND_OTP_LOCK_OFFSET                (14)
 
 #endif /* __ONENAND_REG_H */