video: tegra: host: Remove version from dev name
[linux-2.6.git] / drivers / video / tegra / host / t20 / t20.c
index 02382cb..93e73e5 100644 (file)
 #include <linux/slab.h>
 #include <linux/nvhost_ioctl.h>
 #include <mach/powergate.h>
-#include "dev.h"
+#include <mach/iomap.h>
 #include "t20.h"
 #include "host1x/host1x_syncpt.h"
 #include "host1x/host1x_hardware.h"
 #include "gr3d/gr3d.h"
 #include "gr3d/gr3d_t20.h"
 #include "mpe/mpe.h"
+#include "host1x/host1x.h"
 #include "nvhost_hwctx.h"
 #include "nvhost_channel.h"
 #include "host1x/host1x_channel.h"
 #include "host1x/host1x_cdma.h"
+#include "chip_support.h"
+#include "nvmap.h"
+#include "nvhost_memmgr.h"
 
 #define NVMODMUTEX_2D_FULL     (1)
 #define NVMODMUTEX_2D_SIMPLE   (2)
 #define NVMODMUTEX_VI          (8)
 #define NVMODMUTEX_DSI         (9)
 
-#define NVHOST_NUMCHANNELS     (NV_HOST1X_CHANNELS - 1)
+static int t20_num_alloc_channels = 0;
 
-struct nvhost_device t20_devices[] = {
-{
-       /* channel 0 */
+static struct resource tegra_host1x01_resources[] = {
+       {
+               .start = TEGRA_HOST1X_BASE,
+               .end = TEGRA_HOST1X_BASE + TEGRA_HOST1X_SIZE - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       {
+               .start = INT_SYNCPT_THRESH_BASE,
+               .end = INT_SYNCPT_THRESH_BASE + INT_SYNCPT_THRESH_NR - 1,
+               .flags = IORESOURCE_IRQ,
+       },
+       {
+               .start = INT_HOST1X_MPCORE_GENERAL,
+               .end = INT_HOST1X_MPCORE_GENERAL,
+               .flags = IORESOURCE_IRQ,
+       },
+};
+
+static const char *s_syncpt_names[32] = {
+       "gfx_host",
+       "", "", "", "", "", "", "",
+       "disp0_a", "disp1_a", "avp_0",
+       "csi_vi_0", "csi_vi_1",
+       "vi_isp_0", "vi_isp_1", "vi_isp_2", "vi_isp_3", "vi_isp_4",
+       "2d_0", "2d_1",
+       "disp0_b", "disp1_b",
+       "3d",
+       "mpe",
+       "disp0_c", "disp1_c",
+       "vblank0", "vblank1",
+       "mpe_ebm_eof", "mpe_wr_safe",
+       "2d_tinyblt",
+       "dsi"
+};
+
+static struct host1x_device_info host1x01_info = {
+       .nb_channels    = 8,
+       .nb_pts         = 32,
+       .nb_mlocks      = 16,
+       .nb_bases       = 8,
+       .syncpt_names   = s_syncpt_names,
+       .client_managed = NVSYNCPTS_CLIENT_MANAGED,
+};
+
+static struct nvhost_device tegra_host1x01_device = {
+       .dev            = {.platform_data = &host1x01_info},
+       .name           = "host1x",
+       .id             = -1,
+       .resource       = tegra_host1x01_resources,
+       .num_resources  = ARRAY_SIZE(tegra_host1x01_resources),
+       .clocks         = {{"host1x", UINT_MAX}, {} },
+       NVHOST_MODULE_NO_POWERGATE_IDS,
+};
+
+static struct nvhost_device tegra_display01_device = {
        .name           = "display",
        .id             = -1,
        .index          = 0,
-       .syncpts        = BIT(NVSYNCPT_DISP0_A) | BIT(NVSYNCPT_DISP1_A) |
+       .syncpts        = BIT(NVSYNCPT_DISP0_A) | BIT(NVSYNCPT_DISP1_A) |
                          BIT(NVSYNCPT_DISP0_B) | BIT(NVSYNCPT_DISP1_B) |
                          BIT(NVSYNCPT_DISP0_C) | BIT(NVSYNCPT_DISP1_C) |
                          BIT(NVSYNCPT_VBLANK0) | BIT(NVSYNCPT_VBLANK1),
@@ -59,25 +115,24 @@ struct nvhost_device t20_devices[] = {
        NVHOST_MODULE_NO_POWERGATE_IDS,
        NVHOST_DEFAULT_CLOCKGATE_DELAY,
        .moduleid       = NVHOST_MODULE_NONE,
-},
-{
-       /* channel 1 */
+};
+
+static struct nvhost_device tegra_gr3d01_device = {
        .name           = "gr3d",
+       .version        = 1,
        .id             = -1,
        .index          = 1,
        .syncpts        = BIT(NVSYNCPT_3D),
        .waitbases      = BIT(NVWAITBASE_3D),
        .modulemutexes  = BIT(NVMODMUTEX_3D),
        .class          = NV_GRAPHICS_3D_CLASS_ID,
-       .prepare_poweroff = nvhost_gr3d_prepare_power_off,
-       .alloc_hwctx_handler = nvhost_gr3d_t20_ctxhandler_init,
-       .clocks         = {{"gr3d", UINT_MAX}, {"emc", UINT_MAX}, {} },
+       .clocks         = {{"gr3d", UINT_MAX}, {"emc", UINT_MAX}, {} },
        .powergate_ids  = {TEGRA_POWERGATE_3D, -1},
        NVHOST_DEFAULT_CLOCKGATE_DELAY,
        .moduleid       = NVHOST_MODULE_NONE,
-},
-{
-       /* channel 2 */
+};
+
+static struct nvhost_device tegra_gr2d01_device = {
        .name           = "gr2d",
        .id             = -1,
        .index          = 2,
@@ -85,26 +140,48 @@ struct nvhost_device t20_devices[] = {
        .waitbases      = BIT(NVWAITBASE_2D_0) | BIT(NVWAITBASE_2D_1),
        .modulemutexes  = BIT(NVMODMUTEX_2D_FULL) | BIT(NVMODMUTEX_2D_SIMPLE) |
                          BIT(NVMODMUTEX_2D_SB_A) | BIT(NVMODMUTEX_2D_SB_B),
-       .clocks         = { {"gr2d", UINT_MAX},
+       .clocks         = { {"gr2d", UINT_MAX},
                            {"epp", UINT_MAX},
                            {"emc", UINT_MAX} },
        NVHOST_MODULE_NO_POWERGATE_IDS,
        .clockgate_delay = 0,
        .moduleid       = NVHOST_MODULE_NONE,
-},
-{
-       /* channel 3 */
+};
+
+static struct resource isp_resources_t20[] = {
+       {
+               .name = "regs",
+               .start = TEGRA_ISP_BASE,
+               .end = TEGRA_ISP_BASE + TEGRA_ISP_SIZE - 1,
+               .flags = IORESOURCE_MEM,
+       }
+};
+
+static struct nvhost_device tegra_isp01_device = {
        .name           = "isp",
        .id             = -1,
+       .resource = isp_resources_t20,
+       .num_resources = ARRAY_SIZE(isp_resources_t20),
        .index          = 3,
        .syncpts        = 0,
        NVHOST_MODULE_NO_POWERGATE_IDS,
        NVHOST_DEFAULT_CLOCKGATE_DELAY,
        .moduleid       = NVHOST_MODULE_ISP,
-},
-{
-       /* channel 4 */
+};
+
+static struct resource vi_resources[] = {
+       {
+               .name = "regs",
+               .start = TEGRA_VI_BASE,
+               .end = TEGRA_VI_BASE + TEGRA_VI_SIZE - 1,
+               .flags = IORESOURCE_MEM,
+       },
+};
+
+static struct nvhost_device tegra_vi01_device = {
        .name           = "vi",
+       .resource = vi_resources,
+       .num_resources = ARRAY_SIZE(vi_resources),
        .id             = -1,
        .index          = 4,
        .syncpts        = BIT(NVSYNCPT_CSI_VI_0) | BIT(NVSYNCPT_CSI_VI_1) |
@@ -116,11 +193,23 @@ struct nvhost_device t20_devices[] = {
        NVHOST_MODULE_NO_POWERGATE_IDS,
        NVHOST_DEFAULT_CLOCKGATE_DELAY,
        .moduleid       = NVHOST_MODULE_VI,
-},
-{
-       /* channel 5 */
+};
+
+static struct resource tegra_mpe01_resources[] = {
+       {
+               .name = "regs",
+               .start = TEGRA_MPE_BASE,
+               .end = TEGRA_MPE_BASE + TEGRA_MPE_SIZE - 1,
+               .flags = IORESOURCE_MEM,
+       },
+};
+
+static struct nvhost_device tegra_mpe01_device = {
        .name           = "mpe",
+       .version        = 1,
        .id             = -1,
+       .resource       = tegra_mpe01_resources,
+       .num_resources  = ARRAY_SIZE(tegra_mpe01_resources),
        .index          = 5,
        .syncpts        = BIT(NVSYNCPT_MPE) | BIT(NVSYNCPT_MPE_EBM_EOF) |
                          BIT(NVSYNCPT_MPE_WR_SAFE),
@@ -128,16 +217,14 @@ struct nvhost_device t20_devices[] = {
        .class          = NV_VIDEO_ENCODE_MPEG_CLASS_ID,
        .waitbasesync   = true,
        .keepalive      = true,
-       .prepare_poweroff = nvhost_mpe_prepare_power_off,
-       .alloc_hwctx_handler = nvhost_mpe_ctxhandler_init,
        .clocks         = { {"mpe", UINT_MAX},
                            {"emc", UINT_MAX} },
        .powergate_ids  = {TEGRA_POWERGATE_MPE, -1},
        NVHOST_DEFAULT_CLOCKGATE_DELAY,
        .moduleid       = NVHOST_MODULE_MPE,
-},
-{
-       /* channel 6 */
+};
+
+static struct nvhost_device tegra_dsi01_device = {
        .name           = "dsi",
        .id             = -1,
        .index          = 6,
@@ -146,12 +233,26 @@ struct nvhost_device t20_devices[] = {
        NVHOST_MODULE_NO_POWERGATE_IDS,
        NVHOST_DEFAULT_CLOCKGATE_DELAY,
        .moduleid       = NVHOST_MODULE_NONE,
-} };
+};
 
+static struct nvhost_device *t20_devices[] = {
+       &tegra_host1x01_device,
+       &tegra_display01_device,
+       &tegra_gr3d01_device,
+       &tegra_gr2d01_device,
+       &tegra_isp01_device,
+       &tegra_vi01_device,
+       &tegra_mpe01_device,
+       &tegra_dsi01_device,
+};
+
+int tegra2_register_host1x_devices(void)
+{
+       return nvhost_add_devices(t20_devices, ARRAY_SIZE(t20_devices));
+}
 
 static inline void __iomem *t20_channel_aperture(void __iomem *p, int ndx)
 {
-       p += NV_HOST1X_CHANNEL0_BASE;
        p += ndx * NV_HOST1X_CHANNEL_MAP_SIZE_BYTES;
        return p;
 }
@@ -163,9 +264,10 @@ static inline int t20_nvhost_hwctx_handler_init(struct nvhost_channel *ch)
        unsigned long waitbases = ch->dev->waitbases;
        u32 syncpt = find_first_bit(&syncpts, BITS_PER_LONG);
        u32 waitbase = find_first_bit(&waitbases, BITS_PER_LONG);
+       struct nvhost_driver *drv = to_nvhost_driver(ch->dev->dev.driver);
 
-       if (ch->dev->alloc_hwctx_handler) {
-               ch->ctxhandler = ch->dev->alloc_hwctx_handler(syncpt,
+       if (drv->alloc_hwctx_handler) {
+               ch->ctxhandler = drv->alloc_hwctx_handler(syncpt,
                                waitbase, ch);
                if (!ch->ctxhandler)
                        err = -ENOMEM;
@@ -189,8 +291,6 @@ static int t20_channel_init(struct nvhost_channel *ch,
 int nvhost_init_t20_channel_support(struct nvhost_master *host,
        struct nvhost_chip_support *op)
 {
-       host->nb_channels =  NVHOST_NUMCHANNELS;
-
        op->channel.init = t20_channel_init;
        op->channel.submit = host1x_channel_submit;
        op->channel.read3dreg = host1x_channel_read_3d_reg;
@@ -198,17 +298,17 @@ int nvhost_init_t20_channel_support(struct nvhost_master *host,
        return 0;
 }
 
-struct nvhost_device *t20_get_nvhost_device(struct nvhost_master *host,
-       char *name)
+static void t20_free_nvhost_channel(struct nvhost_channel *ch)
 {
-       int i;
-
-       for (i = 0; i < ARRAY_SIZE(t20_devices); i++) {
-               if (strcmp(t20_devices[i].name, name) == 0)
-                       return &t20_devices[i];
-       }
+       nvhost_free_channel_internal(ch, &t20_num_alloc_channels);
+}
 
-       return NULL;
+static struct nvhost_channel *t20_alloc_nvhost_channel(
+               struct nvhost_device *dev)
+{
+       return nvhost_alloc_channel_internal(dev->index,
+               nvhost_get_host(dev)->info.nb_channels,
+               &t20_num_alloc_channels);
 }
 
 int nvhost_init_t20_support(struct nvhost_master *host,
@@ -232,6 +332,10 @@ int nvhost_init_t20_support(struct nvhost_master *host,
        err = nvhost_init_t20_intr_support(op);
        if (err)
                return err;
-       op->nvhost_dev.get_nvhost_device = t20_get_nvhost_device;
+       err = nvhost_memmgr_init(op);
+
+       op->nvhost_dev.alloc_nvhost_channel = t20_alloc_nvhost_channel;
+       op->nvhost_dev.free_nvhost_channel = t20_free_nvhost_channel;
+
        return 0;
 }