Merge 'akpm' patch series
[linux-2.6.git] / drivers / video / cirrusfb.c
index dda240e..6df7c54 100644 (file)
  *
  */
 
-#define CIRRUSFB_VERSION "2.0-pre2"
-
-#include <linux/config.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/string.h>
 #include <linux/mm.h>
-#include <linux/tty.h>
-#include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/fb.h>
 #include <linux/init.h>
-#include <linux/selection.h>
 #include <asm/pgtable.h>
 
 #ifdef CONFIG_ZORRO
 #endif
 #ifdef CONFIG_PPC_PREP
 #include <asm/machdep.h>
-#define isPReP (machine_is(prep))
+#define isPReP machine_is(prep)
 #else
 #define isPReP 0
 #endif
 
-#include "video/vga.h"
-#include "video/cirrus.h"
-
+#include <video/vga.h>
+#include <video/cirrus.h>
 
 /*****************************************************************
  *
  *
  */
 
-/* enable debug output? */
-/* #define CIRRUSFB_DEBUG 1 */
-
 /* disable runtime assertions? */
 /* #define CIRRUSFB_NDEBUG */
 
-/* debug output */
-#ifdef CIRRUSFB_DEBUG
-#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
-#else
-#define DPRINTK(fmt, args...)
-#endif
-
 /* debugging assertions */
 #ifndef CIRRUSFB_NDEBUG
 #define assert(expr) \
-        if(!(expr)) { \
-        printk( "Assertion failed! %s,%s,%s,line=%d\n",\
-        #expr,__FILE__,__FUNCTION__,__LINE__); \
-        }
+       if (!(expr)) { \
+               printk("Assertion failed! %s,%s,%s,line=%d\n", \
+               #expr, __FILE__, __func__, __LINE__); \
+       }
 #else
 #define assert(expr)
 #endif
 
-#ifdef TRUE
-#undef TRUE
-#endif
-#ifdef FALSE
-#undef FALSE
-#endif
-#define TRUE  1
-#define FALSE 0
-
-#define MB_ (1024*1024)
-#define KB_ (1024)
-
-#define MAX_NUM_BOARDS 7
-
+#define MB_ (1024 * 1024)
 
 /*****************************************************************
  *
  */
 
 /* board types */
-typedef enum {
+enum cirrus_board {
        BT_NONE = 0,
-       BT_SD64,
-       BT_PICCOLO,
-       BT_PICASSO,
-       BT_SPECTRUM,
+       BT_SD64,        /* GD5434 */
+       BT_PICCOLO,     /* GD5426 */
+       BT_PICASSO,     /* GD5426 or GD5428 */
+       BT_SPECTRUM,    /* GD5426 or GD5428 */
        BT_PICASSO4,    /* GD5446 */
        BT_ALPINE,      /* GD543x/4x */
        BT_GD5480,
-       BT_LAGUNA,      /* GD546x */
-} cirrusfb_board_t;
-
+       BT_LAGUNA,      /* GD5462/64 */
+       BT_LAGUNAB,     /* GD5465 */
+};
 
 /*
  * per-board-type information, used for enumerating and abstracting
  * chip-specific information
- * NOTE: MUST be in the same order as cirrusfb_board_t in order to
+ * NOTE: MUST be in the same order as enum cirrus_board in order to
  * use direct indexing on this array
  * NOTE: '__initdata' cannot be used as some of this info
  * is required at runtime.  Maybe separate into an init-only and
@@ -148,9 +118,10 @@ static const struct cirrusfb_board_info_rec {
        char *name;             /* ASCII name of chipset */
        long maxclock[5];               /* maximum video clock */
        /* for  1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
-       unsigned init_sr07 : 1; /* init SR07 during init_vgachip() */
-       unsigned init_sr1f : 1; /* write SR1F during init_vgachip() */
-       unsigned scrn_start_bit19 : 1; /* construct bit 19 of screen start address */
+       bool init_sr07 : 1; /* init SR07 during init_vgachip() */
+       bool init_sr1f : 1; /* write SR1F during init_vgachip() */
+       /* construct bit 19 of screen start address */
+       bool scrn_start_bit19 : 1;
 
        /* initial SR07 value, then for each mode */
        unsigned char sr07;
@@ -166,15 +137,17 @@ static const struct cirrusfb_board_info_rec {
                .maxclock               = {
                        /* guess */
                        /* the SD64/P4 have a higher max. videoclock */
-                       140000, 140000, 140000, 140000, 140000,
+                       135100, 135100, 85500, 85500, 0
                },
-               .init_sr07              = TRUE,
-               .init_sr1f              = TRUE,
-               .scrn_start_bit19       = TRUE,
+               .init_sr07              = true,
+               .init_sr1f              = true,
+               .scrn_start_bit19       = true,
                .sr07                   = 0xF0,
                .sr07_1bpp              = 0xF0,
+               .sr07_1bpp_mux          = 0xF6,
                .sr07_8bpp              = 0xF1,
-               .sr1f                   = 0x20
+               .sr07_8bpp_mux          = 0xF7,
+               .sr1f                   = 0x1E
        },
        [BT_PICCOLO] = {
                .name                   = "CL Piccolo",
@@ -182,9 +155,9 @@ static const struct cirrusfb_board_info_rec {
                        /* guess */
                        90000, 90000, 90000, 90000, 90000
                },
-               .init_sr07              = TRUE,
-               .init_sr1f              = TRUE,
-               .scrn_start_bit19       = FALSE,
+               .init_sr07              = true,
+               .init_sr1f              = true,
+               .scrn_start_bit19       = false,
                .sr07                   = 0x80,
                .sr07_1bpp              = 0x80,
                .sr07_8bpp              = 0x81,
@@ -196,9 +169,9 @@ static const struct cirrusfb_board_info_rec {
                        /* guess */
                        90000, 90000, 90000, 90000, 90000
                },
-               .init_sr07              = TRUE,
-               .init_sr1f              = TRUE,
-               .scrn_start_bit19       = FALSE,
+               .init_sr07              = true,
+               .init_sr1f              = true,
+               .scrn_start_bit19       = false,
                .sr07                   = 0x20,
                .sr07_1bpp              = 0x20,
                .sr07_8bpp              = 0x21,
@@ -210,9 +183,9 @@ static const struct cirrusfb_board_info_rec {
                        /* guess */
                        90000, 90000, 90000, 90000, 90000
                },
-               .init_sr07              = TRUE,
-               .init_sr1f              = TRUE,
-               .scrn_start_bit19       = FALSE,
+               .init_sr07              = true,
+               .init_sr1f              = true,
+               .scrn_start_bit19       = false,
                .sr07                   = 0x80,
                .sr07_1bpp              = 0x80,
                .sr07_8bpp              = 0x81,
@@ -223,12 +196,14 @@ static const struct cirrusfb_board_info_rec {
                .maxclock               = {
                        135100, 135100, 85500, 85500, 0
                },
-               .init_sr07              = TRUE,
-               .init_sr1f              = FALSE,
-               .scrn_start_bit19       = TRUE,
-               .sr07                   = 0x20,
-               .sr07_1bpp              = 0x20,
-               .sr07_8bpp              = 0x21,
+               .init_sr07              = true,
+               .init_sr1f              = false,
+               .scrn_start_bit19       = true,
+               .sr07                   = 0xA0,
+               .sr07_1bpp              = 0xA0,
+               .sr07_1bpp_mux          = 0xA6,
+               .sr07_8bpp              = 0xA1,
+               .sr07_8bpp_mux          = 0xA7,
                .sr1f                   = 0
        },
        [BT_ALPINE] = {
@@ -237,12 +212,12 @@ static const struct cirrusfb_board_info_rec {
                        /* for the GD5430.  GD5446 can do more... */
                        85500, 85500, 50000, 28500, 0
                },
-               .init_sr07              = TRUE,
-               .init_sr1f              = TRUE,
-               .scrn_start_bit19       = TRUE,
+               .init_sr07              = true,
+               .init_sr1f              = true,
+               .scrn_start_bit19       = true,
                .sr07                   = 0xA0,
-               .sr07_1bpp              = 0xA1,
-               .sr07_1bpp_mux          = 0xA7,
+               .sr07_1bpp              = 0xA0,
+               .sr07_1bpp_mux          = 0xA6,
                .sr07_8bpp              = 0xA1,
                .sr07_8bpp_mux          = 0xA7,
                .sr1f                   = 0x1C
@@ -252,9 +227,9 @@ static const struct cirrusfb_board_info_rec {
                .maxclock               = {
                        135100, 200000, 200000, 135100, 135100
                },
-               .init_sr07              = TRUE,
-               .init_sr1f              = TRUE,
-               .scrn_start_bit19       = TRUE,
+               .init_sr07              = true,
+               .init_sr1f              = true,
+               .scrn_start_bit19       = true,
                .sr07                   = 0x10,
                .sr07_1bpp              = 0x11,
                .sr07_8bpp              = 0x11,
@@ -263,39 +238,47 @@ static const struct cirrusfb_board_info_rec {
        [BT_LAGUNA] = {
                .name                   = "CL Laguna",
                .maxclock               = {
-                       /* guess */
-                       135100, 135100, 135100, 135100, 135100,
+                       /* taken from X11 code */
+                       170000, 170000, 170000, 170000, 135100,
+               },
+               .init_sr07              = false,
+               .init_sr1f              = false,
+               .scrn_start_bit19       = true,
+       },
+       [BT_LAGUNAB] = {
+               .name                   = "CL Laguna AGP",
+               .maxclock               = {
+                       /* taken from X11 code */
+                       170000, 250000, 170000, 170000, 135100,
                },
-               .init_sr07              = FALSE,
-               .init_sr1f              = FALSE,
-               .scrn_start_bit19       = TRUE,
+               .init_sr07              = false,
+               .init_sr1f              = false,
+               .scrn_start_bit19       = true,
        }
 };
 
-
 #ifdef CONFIG_PCI
 #define CHIP(id, btype) \
        { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
 
 static struct pci_device_id cirrusfb_pci_table[] = {
-       CHIP( PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE ),
-       CHIP( PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE ),
-       CHIP( PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE ),
-       CHIP( PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE ), /* GD-5440 is same id */
-       CHIP( PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE ),
-       CHIP( PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE ),
-       CHIP( PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480 ), /* MacPicasso likely */
-       CHIP( PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4 ), /* Picasso 4 is 5446 */
-       CHIP( PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA ), /* CL Laguna */
-       CHIP( PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA ), /* CL Laguna 3D */
-       CHIP( PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNA ), /* CL Laguna 3DA*/
+       CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
+       CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_SD64),
+       CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_SD64),
+       CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
+       CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
+       CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
+       CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
+       CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
+       CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
+       CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
+       CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNAB), /* CL Laguna 3DA*/
        { 0, }
 };
 MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
 #undef CHIP
 #endif /* CONFIG_PCI */
 
-
 #ifdef CONFIG_ZORRO
 static const struct zorro_device_id cirrusfb_zorro_table[] = {
        {
@@ -305,7 +288,7 @@ static const struct zorro_device_id cirrusfb_zorro_table[] = {
                .id             = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
                .driver_data    = BT_PICCOLO,
        }, {
-               .id             = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
+               .id     = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
                .driver_data    = BT_PICASSO,
        }, {
                .id             = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
@@ -316,6 +299,7 @@ static const struct zorro_device_id cirrusfb_zorro_table[] = {
        },
        { 0 }
 };
+MODULE_DEVICE_TABLE(zorro, cirrusfb_zorro_table);
 
 static const struct {
        zorro_id id2;
@@ -344,275 +328,100 @@ static const struct {
 };
 #endif /* CONFIG_ZORRO */
 
-
-struct cirrusfb_regs {
-       __u32 line_length;      /* in BYTES! */
-       __u32 visual;
-       __u32 type;
-
-       long freq;
-       long nom;
-       long den;
-       long div;
-       long multiplexing;
-       long mclk;
-       long divMCLK;
-
-       long HorizRes;          /* The x resolution in pixel */
-       long HorizTotal;
-       long HorizDispEnd;
-       long HorizBlankStart;
-       long HorizBlankEnd;
-       long HorizSyncStart;
-       long HorizSyncEnd;
-
-       long VertRes;           /* the physical y resolution in scanlines */
-       long VertTotal;
-       long VertDispEnd;
-       long VertSyncStart;
-       long VertSyncEnd;
-       long VertBlankStart;
-       long VertBlankEnd;
-};
-
-
-
 #ifdef CIRRUSFB_DEBUG
-typedef enum {
-        CRT,
-        SEQ
-} cirrusfb_dbg_reg_class_t;
-#endif                          /* CIRRUSFB_DEBUG */
-
-
-
+enum cirrusfb_dbg_reg_class {
+       CRT,
+       SEQ
+};
+#endif         /* CIRRUSFB_DEBUG */
 
 /* info about board */
 struct cirrusfb_info {
-       struct fb_info *info;
-
-       u8 __iomem *fbmem;
        u8 __iomem *regbase;
-       u8 __iomem *mem;
-       unsigned long size;
-       cirrusfb_board_t btype;
+       u8 __iomem *laguna_mmio;
+       enum cirrus_board btype;
        unsigned char SFR;      /* Shadow of special function register */
 
-       unsigned long fbmem_phys;
-       unsigned long fbregs_phys;
-
-       struct cirrusfb_regs currentmode;
+       int multiplexing;
+       int doubleVCLK;
        int blank_mode;
+       u32 pseudo_palette[16];
 
-       u32     pseudo_palette[16];
-       struct { u8 red, green, blue, pad; } palette[256];
-
-#ifdef CONFIG_ZORRO
-       struct zorro_dev *zdev;
-#endif
-#ifdef CONFIG_PCI
-       struct pci_dev *pdev;
-#endif
-       void (*unmap)(struct cirrusfb_info *cinfo);
+       void (*unmap)(struct fb_info *info);
 };
 
-
-static unsigned cirrusfb_def_mode = 1;
-static int noaccel = 0;
-
-/*
- *    Predefined Video Modes
- */
-
-static const struct {
-       const char *name;
-       struct fb_var_screeninfo var;
-} cirrusfb_predefined[] = {
-       {
-               /* autodetect mode */
-               .name   = "Autodetect",
-       }, {
-               /* 640x480, 31.25 kHz, 60 Hz, 25 MHz PixClock */
-               .name   = "640x480",
-               .var    = {
-                       .xres           = 640,
-                       .yres           = 480,
-                       .xres_virtual   = 640,
-                       .yres_virtual   = 480,
-                       .bits_per_pixel = 8,
-                       .red            = { .length = 8 },
-                       .green          = { .length = 8 },
-                       .blue           = { .length = 8 },
-                       .width          = -1,
-                       .height         = -1,
-                       .pixclock       = 40000,
-                       .left_margin    = 48,
-                       .right_margin   = 16,
-                       .upper_margin   = 32,
-                       .lower_margin   = 8,
-                       .hsync_len      = 96,
-                       .vsync_len      = 4,
-                       .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-                       .vmode          = FB_VMODE_NONINTERLACED
-                }
-       }, {
-               /* 800x600, 48 kHz, 76 Hz, 50 MHz PixClock */
-               .name   = "800x600",
-               .var    = {
-                       .xres           = 800,
-                       .yres           = 600,
-                       .xres_virtual   = 800,
-                       .yres_virtual   = 600,
-                       .bits_per_pixel = 8,
-                       .red            = { .length = 8 },
-                       .green          = { .length = 8 },
-                       .blue           = { .length = 8 },
-                       .width          = -1,
-                       .height         = -1,
-                       .pixclock       = 20000,
-                       .left_margin    = 128,
-                       .right_margin   = 16,
-                       .upper_margin   = 24,
-                       .lower_margin   = 2,
-                       .hsync_len      = 96,
-                       .vsync_len      = 6,
-                       .vmode          = FB_VMODE_NONINTERLACED
-                }
-       }, {
-               /*
-                * Modeline from XF86Config:
-                * Mode "1024x768" 80  1024 1136 1340 1432  768 770 774 805
-                */
-               /* 1024x768, 55.8 kHz, 70 Hz, 80 MHz PixClock */
-               .name   = "1024x768",
-               .var    = {
-                       .xres           = 1024,
-                       .yres           = 768,
-                       .xres_virtual   = 1024,
-                       .yres_virtual   = 768,
-                       .bits_per_pixel = 8,
-                       .red            = { .length = 8 },
-                       .green          = { .length = 8 },
-                       .blue           = { .length = 8 },
-                       .width          = -1,
-                       .height         = -1,
-                       .pixclock       = 12500,
-                       .left_margin    = 144,
-                       .right_margin   = 32,
-                       .upper_margin   = 30,
-                       .lower_margin   = 2,
-                       .hsync_len      = 192,
-                       .vsync_len      = 6,
-                       .vmode          = FB_VMODE_NONINTERLACED
-               }
-       }
-};
-
-#define NUM_TOTAL_MODES    ARRAY_SIZE(cirrusfb_predefined)
+static int noaccel __devinitdata;
+static char *mode_option __devinitdata = "640x480@60";
 
 /****************************************************************************/
 /**** BEGIN PROTOTYPES ******************************************************/
 
-
 /*--- Interface used by the world ------------------------------------------*/
-static int cirrusfb_init (void);
-#ifndef MODULE
-static int cirrusfb_setup (char *options);
-#endif
+static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
+                               struct fb_info *info);
 
-static int cirrusfb_open (struct fb_info *info, int user);
-static int cirrusfb_release (struct fb_info *info, int user);
-static int cirrusfb_setcolreg (unsigned regno, unsigned red, unsigned green,
-                              unsigned blue, unsigned transp,
-                              struct fb_info *info);
-static int cirrusfb_check_var (struct fb_var_screeninfo *var,
-                              struct fb_info *info);
-static int cirrusfb_set_par (struct fb_info *info);
-static int cirrusfb_pan_display (struct fb_var_screeninfo *var,
-                                struct fb_info *info);
-static int cirrusfb_blank (int blank_mode, struct fb_info *info);
-static void cirrusfb_fillrect (struct fb_info *info, const struct fb_fillrect *region);
-static void cirrusfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
-static void cirrusfb_imageblit(struct fb_info *info, const struct fb_image *image);
-
-/* function table of the above functions */
-static struct fb_ops cirrusfb_ops = {
-       .owner          = THIS_MODULE,
-       .fb_open        = cirrusfb_open,
-       .fb_release     = cirrusfb_release,
-       .fb_setcolreg   = cirrusfb_setcolreg,
-       .fb_check_var   = cirrusfb_check_var,
-       .fb_set_par     = cirrusfb_set_par,
-       .fb_pan_display = cirrusfb_pan_display,
-       .fb_blank       = cirrusfb_blank,
-       .fb_fillrect    = cirrusfb_fillrect,
-       .fb_copyarea    = cirrusfb_copyarea,
-       .fb_imageblit   = cirrusfb_imageblit,
-};
-
-/*--- Hardware Specific Routines -------------------------------------------*/
-static int cirrusfb_decode_var (const struct fb_var_screeninfo *var,
-                               struct cirrusfb_regs *regs,
-                               const struct fb_info *info);
 /*--- Internal routines ----------------------------------------------------*/
-static void init_vgachip (struct cirrusfb_info *cinfo);
-static void switch_monitor (struct cirrusfb_info *cinfo, int on);
-static void WGen (const struct cirrusfb_info *cinfo,
-                 int regnum, unsigned char val);
-static unsigned char RGen (const struct cirrusfb_info *cinfo, int regnum);
-static void AttrOn (const struct cirrusfb_info *cinfo);
-static void WHDR (const struct cirrusfb_info *cinfo, unsigned char val);
-static void WSFR (struct cirrusfb_info *cinfo, unsigned char val);
-static void WSFR2 (struct cirrusfb_info *cinfo, unsigned char val);
-static void WClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
-                  unsigned char green,
-                  unsigned char blue);
+static void init_vgachip(struct fb_info *info);
+static void switch_monitor(struct cirrusfb_info *cinfo, int on);
+static void WGen(const struct cirrusfb_info *cinfo,
+                int regnum, unsigned char val);
+static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
+static void AttrOn(const struct cirrusfb_info *cinfo);
+static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
+static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
+static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
+static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
+                 unsigned char red, unsigned char green, unsigned char blue);
 #if 0
-static void RClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
-                  unsigned char *green,
-                  unsigned char *blue);
+static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
+                 unsigned char *red, unsigned char *green,
+                 unsigned char *blue);
 #endif
-static void cirrusfb_WaitBLT (u8 __iomem *regbase);
-static void cirrusfb_BitBLT (u8 __iomem *regbase, int bits_per_pixel,
-                            u_short curx, u_short cury,
-                            u_short destx, u_short desty,
-                            u_short width, u_short height,
-                            u_short line_length);
-static void cirrusfb_RectFill (u8 __iomem *regbase, int bits_per_pixel,
-                              u_short x, u_short y,
-                              u_short width, u_short height,
-                              u_char color, u_short line_length);
-
-static void bestclock (long freq, long *best,
-                      long *nom, long *den,
-                      long *div, long maxfreq);
+static void cirrusfb_WaitBLT(u8 __iomem *regbase);
+static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
+                           u_short curx, u_short cury,
+                           u_short destx, u_short desty,
+                           u_short width, u_short height,
+                           u_short line_length);
+static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
+                             u_short x, u_short y,
+                             u_short width, u_short height,
+                             u32 fg_color, u32 bg_color,
+                             u_short line_length, u_char blitmode);
+
+static void bestclock(long freq, int *nom, int *den, int *div);
 
 #ifdef CIRRUSFB_DEBUG
-static void cirrusfb_dump (void);
-static void cirrusfb_dbg_reg_dump (caddr_t regbase);
-static void cirrusfb_dbg_print_regs (caddr_t regbase, cirrusfb_dbg_reg_class_t reg_class,...);
-static void cirrusfb_dbg_print_byte (const char *name, unsigned char val);
+static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
+static void cirrusfb_dbg_print_regs(struct fb_info *info,
+                                   caddr_t regbase,
+                                   enum cirrusfb_dbg_reg_class reg_class, ...);
 #endif /* CIRRUSFB_DEBUG */
 
 /*** END   PROTOTYPES ********************************************************/
 /*****************************************************************************/
 /*** BEGIN Interface Used by the World ***************************************/
 
-static int opencount = 0;
+static inline int is_laguna(const struct cirrusfb_info *cinfo)
+{
+       return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB;
+}
+
+static int opencount;
 
 /*--- Open /dev/fbx ---------------------------------------------------------*/
-static int cirrusfb_open (struct fb_info *info, int user)
+static int cirrusfb_open(struct fb_info *info, int user)
 {
        if (opencount++ == 0)
-               switch_monitor (info->par, 1);
+               switch_monitor(info->par, 1);
        return 0;
 }
 
 /*--- Close /dev/fbx --------------------------------------------------------*/
-static int cirrusfb_release (struct fb_info *info, int user)
+static int cirrusfb_release(struct fb_info *info, int user)
 {
        if (--opencount == 0)
-               switch_monitor (info->par, 0);
+               switch_monitor(info->par, 0);
        return 0;
 }
 
@@ -620,191 +429,131 @@ static int cirrusfb_release (struct fb_info *info, int user)
 /****************************************************************************/
 /**** BEGIN Hardware specific Routines **************************************/
 
-/* Get a good MCLK value */
-static long cirrusfb_get_mclk (long freq, int bpp, long *div)
+/* Check if the MCLK is not a better clock source */
+static int cirrusfb_check_mclk(struct fb_info *info, long freq)
 {
-       long mclk;
-
-       assert (div != NULL);
-
-       /* Calculate MCLK, in case VCLK is high enough to require > 50MHz.
-        * Assume a 64-bit data path for now.  The formula is:
-        * ((B * PCLK * 2)/W) * 1.2
-        * B = bytes per pixel, PCLK = pixclock, W = data width in bytes */
-       mclk = ((bpp / 8) * freq * 2) / 4;
-       mclk = (mclk * 12) / 10;
-       if (mclk < 50000)
-               mclk = 50000;
-       DPRINTK ("Use MCLK of %ld kHz\n", mclk);
+       struct cirrusfb_info *cinfo = info->par;
+       long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f;
 
-       /* Calculate value for SR1F.  Multiply by 2 so we can round up. */
-       mclk = ((mclk * 16) / 14318);
-       mclk = (mclk + 1) / 2;
-       DPRINTK ("Set SR1F[5:0] to 0x%lx\n", mclk);
+       /* Read MCLK value */
+       mclk = (14318 * mclk) >> 3;
+       dev_dbg(info->device, "Read MCLK of %ld kHz\n", mclk);
 
        /* Determine if we should use MCLK instead of VCLK, and if so, what we
-          * should divide it by to get VCLK */
-       switch (freq) {
-       case 24751 ... 25249:
-               *div = 2;
-               DPRINTK ("Using VCLK = MCLK/2\n");
-               break;
-       case 49501 ... 50499:
-               *div = 1;
-               DPRINTK ("Using VCLK = MCLK\n");
-               break;
-       default:
-               *div = 0;
-               break;
+        * should divide it by to get VCLK
+        */
+
+       if (abs(freq - mclk) < 250) {
+               dev_dbg(info->device, "Using VCLK = MCLK\n");
+               return 1;
+       } else if (abs(freq - (mclk / 2)) < 250) {
+               dev_dbg(info->device, "Using VCLK = MCLK/2\n");
+               return 2;
        }
 
-       return mclk;
+       return 0;
 }
 
-static int cirrusfb_check_var(struct fb_var_screeninfo *var,
-                             struct fb_info *info)
+static int cirrusfb_check_pixclock(const struct fb_var_screeninfo *var,
+                                  struct fb_info *info)
 {
+       long freq;
+       long maxclock;
        struct cirrusfb_info *cinfo = info->par;
-       int nom, den;           /* translyting from pixels->bytes */
-       int yres, i;
-       static struct { int xres, yres; } modes[] =
-       { { 1600, 1280 },
-         { 1280, 1024 },
-         { 1024, 768 },
-         { 800, 600 },
-         { 640, 480 },
-         { -1, -1 } };
+       unsigned maxclockidx = var->bits_per_pixel >> 3;
 
-       switch (var->bits_per_pixel) {
-       case 0 ... 1:
-               var->bits_per_pixel = 1;
-               nom = 4;
-               den = 8;
-               break;          /* 8 pixel per byte, only 1/4th of mem usable */
-       case 2 ... 8:
-               var->bits_per_pixel = 8;
-               nom = 1;
-               den = 1;
-               break;          /* 1 pixel == 1 byte */
-       case 9 ... 16:
-               var->bits_per_pixel = 16;
-               nom = 2;
-               den = 1;
-               break;          /* 2 bytes per pixel */
-       case 17 ... 24:
-               var->bits_per_pixel = 24;
-               nom = 3;
-               den = 1;
-               break;          /* 3 bytes per pixel */
-       case 25 ... 32:
-               var->bits_per_pixel = 32;
-               nom = 4;
-               den = 1;
-               break;          /* 4 bytes per pixel */
-       default:
-               printk ("cirrusfb: mode %dx%dx%d rejected...color depth not supported.\n",
-                       var->xres, var->yres, var->bits_per_pixel);
-               DPRINTK ("EXIT - EINVAL error\n");
-               return -EINVAL;
-       }
+       /* convert from ps to kHz */
+       freq = PICOS2KHZ(var->pixclock);
 
-       if (var->xres * nom / den * var->yres > cinfo->size) {
-               printk ("cirrusfb: mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
-                       var->xres, var->yres, var->bits_per_pixel);
-               DPRINTK ("EXIT - EINVAL error\n");
+       dev_dbg(info->device, "desired pixclock: %ld kHz\n", freq);
+
+       maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
+       cinfo->multiplexing = 0;
+
+       /* If the frequency is greater than we can support, we might be able
+        * to use multiplexing for the video mode */
+       if (freq > maxclock) {
+               dev_err(info->device,
+                       "Frequency greater than maxclock (%ld kHz)\n",
+                       maxclock);
                return -EINVAL;
        }
+       /*
+        * Additional constraint: 8bpp uses DAC clock doubling to allow maximum
+        * pixel clock
+        */
+       if (var->bits_per_pixel == 8) {
+               switch (cinfo->btype) {
+               case BT_ALPINE:
+               case BT_SD64:
+               case BT_PICASSO4:
+                       if (freq > 85500)
+                               cinfo->multiplexing = 1;
+                       break;
+               case BT_GD5480:
+                       if (freq > 135100)
+                               cinfo->multiplexing = 1;
+                       break;
 
-       /* use highest possible virtual resolution */
-       if (var->xres_virtual == -1 &&
-           var->yres_virtual == -1) {
-               printk ("cirrusfb: using maximum available virtual resolution\n");
-               for (i = 0; modes[i].xres != -1; i++) {
-                       if (modes[i].xres * nom / den * modes[i].yres < cinfo->size / 2)
-                               break;
-               }
-               if (modes[i].xres == -1) {
-                       printk ("cirrusfb: could not find a virtual resolution that fits into video memory!!\n");
-                       DPRINTK ("EXIT - EINVAL error\n");
-                       return -EINVAL;
+               default:
+                       break;
                }
-               var->xres_virtual = modes[i].xres;
-               var->yres_virtual = modes[i].yres;
-
-               printk ("cirrusfb: virtual resolution set to maximum of %dx%d\n",
-                       var->xres_virtual, var->yres_virtual);
        }
 
-       if (var->xres_virtual < var->xres)
-               var->xres_virtual = var->xres;
-       if (var->yres_virtual < var->yres)
-               var->yres_virtual = var->yres;
+       /* If we have a 1MB 5434, we need to put ourselves in a mode where
+        * the VCLK is double the pixel clock. */
+       cinfo->doubleVCLK = 0;
+       if (cinfo->btype == BT_SD64 && info->fix.smem_len <= MB_ &&
+           var->bits_per_pixel == 16) {
+               cinfo->doubleVCLK = 1;
+       }
 
-       if (var->xoffset < 0)
-               var->xoffset = 0;
-       if (var->yoffset < 0)
-               var->yoffset = 0;
+       return 0;
+}
 
-       /* truncate xoffset and yoffset to maximum if too high */
-       if (var->xoffset > var->xres_virtual - var->xres)
-               var->xoffset = var->xres_virtual - var->xres - 1;
-       if (var->yoffset > var->yres_virtual - var->yres)
-               var->yoffset = var->yres_virtual - var->yres - 1;
+static int cirrusfb_check_var(struct fb_var_screeninfo *var,
+                             struct fb_info *info)
+{
+       int yres;
+       /* memory size in pixels */
+       unsigned pixels = info->screen_size * 8 / var->bits_per_pixel;
+       struct cirrusfb_info *cinfo = info->par;
 
        switch (var->bits_per_pixel) {
        case 1:
                var->red.offset = 0;
                var->red.length = 1;
-               var->green.offset = 0;
-               var->green.length = 1;
-               var->blue.offset = 0;
-               var->blue.length = 1;
+               var->green = var->red;
+               var->blue = var->red;
                break;
 
        case 8:
                var->red.offset = 0;
-               var->red.length = 6;
-               var->green.offset = 0;
-               var->green.length = 6;
-               var->blue.offset = 0;
-               var->blue.length = 6;
+               var->red.length = 8;
+               var->green = var->red;
+               var->blue = var->red;
                break;
 
        case 16:
-               if(isPReP) {
+               if (isPReP) {
                        var->red.offset = 2;
                        var->green.offset = -3;
                        var->blue.offset = 8;
                } else {
-                       var->red.offset = 10;
+                       var->red.offset = 11;
                        var->green.offset = 5;
                        var->blue.offset = 0;
                }
                var->red.length = 5;
-               var->green.length = 5;
+               var->green.length = 6;
                var->blue.length = 5;
                break;
 
        case 24:
-               if(isPReP) {
-                       var->red.offset = 8;
-                       var->green.offset = 16;
-                       var->blue.offset = 24;
-               } else {
-                       var->red.offset = 16;
+               if (isPReP) {
+                       var->red.offset = 0;
                        var->green.offset = 8;
-                       var->blue.offset = 0;
-               }
-               var->red.length = 8;
-               var->green.length = 8;
-               var->blue.length = 8;
-               break;
-
-       case 32:
-               if(isPReP) {
-                       var->red.offset = 8;
-                       var->green.offset = 16;
-                       var->blue.offset = 24;
+                       var->blue.offset = 16;
                } else {
                        var->red.offset = 16;
                        var->green.offset = 8;
@@ -816,12 +565,43 @@ static int cirrusfb_check_var(struct fb_var_screeninfo *var,
                break;
 
        default:
-               DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
-               assert (FALSE);
-               /* should never occur */
-               break;
+               dev_dbg(info->device,
+                       "Unsupported bpp size: %d\n", var->bits_per_pixel);
+               return -EINVAL;
+       }
+
+       if (var->xres_virtual < var->xres)
+               var->xres_virtual = var->xres;
+       /* use highest possible virtual resolution */
+       if (var->yres_virtual == -1) {
+               var->yres_virtual = pixels / var->xres_virtual;
+
+               dev_info(info->device,
+                        "virtual resolution set to maximum of %dx%d\n",
+                        var->xres_virtual, var->yres_virtual);
+       }
+       if (var->yres_virtual < var->yres)
+               var->yres_virtual = var->yres;
+
+       if (var->xres_virtual * var->yres_virtual > pixels) {
+               dev_err(info->device, "mode %dx%dx%d rejected... "
+                     "virtual resolution too high to fit into video memory!\n",
+                       var->xres_virtual, var->yres_virtual,
+                       var->bits_per_pixel);
+               return -EINVAL;
        }
 
+       if (var->xoffset < 0)
+               var->xoffset = 0;
+       if (var->yoffset < 0)
+               var->yoffset = 0;
+
+       /* truncate xoffset and yoffset to maximum if too high */
+       if (var->xoffset > var->xres_virtual - var->xres)
+               var->xoffset = var->xres_virtual - var->xres - 1;
+       if (var->yoffset > var->yres_virtual - var->yres)
+               var->yoffset = var->yres_virtual - var->yres - 1;
+
        var->red.msb_right =
            var->green.msb_right =
            var->blue.msb_right =
@@ -836,175 +616,39 @@ static int cirrusfb_check_var(struct fb_var_screeninfo *var,
                yres = (yres + 1) / 2;
 
        if (yres >= 1280) {
-               printk (KERN_WARNING "cirrusfb: ERROR: VerticalTotal >= 1280; special treatment required! (TODO)\n");
-               DPRINTK ("EXIT - EINVAL error\n");
+               dev_err(info->device, "ERROR: VerticalTotal >= 1280; "
+                       "special treatment required! (TODO)\n");
                return -EINVAL;
        }
 
+       if (cirrusfb_check_pixclock(var, info))
+               return -EINVAL;
+
+       if (!is_laguna(cinfo))
+               var->accel_flags = FB_ACCELF_TEXT;
+
        return 0;
 }
 
-static int cirrusfb_decode_var (const struct fb_var_screeninfo *var,
-                               struct cirrusfb_regs *regs,
-                               const struct fb_info *info)
+static void cirrusfb_set_mclk_as_source(const struct fb_info *info, int div)
 {
-       long freq;
-       long maxclock;
-       int maxclockidx = 0;
        struct cirrusfb_info *cinfo = info->par;
-       int xres, hfront, hsync, hback;
-       int yres, vfront, vsync, vback;
-
-       switch(var->bits_per_pixel) {
-       case 1:
-               regs->line_length = var->xres_virtual / 8;
-               regs->visual = FB_VISUAL_MONO10;
-               maxclockidx = 0;
-               break;
-
-       case 8:
-               regs->line_length = var->xres_virtual;
-               regs->visual = FB_VISUAL_PSEUDOCOLOR;
-               maxclockidx = 1;
-               break;
+       unsigned char old1f, old1e;
 
-       case 16:
-               regs->line_length = var->xres_virtual * 2;
-               regs->visual = FB_VISUAL_DIRECTCOLOR;
-               maxclockidx = 2;
-               break;
-
-       case 24:
-               regs->line_length = var->xres_virtual * 3;
-               regs->visual = FB_VISUAL_DIRECTCOLOR;
-               maxclockidx = 3;
-               break;
+       assert(cinfo != NULL);
+       old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40;
 
-       case 32:
-               regs->line_length = var->xres_virtual * 4;
-               regs->visual = FB_VISUAL_DIRECTCOLOR;
-               maxclockidx = 4;
-               break;
+       if (div) {
+               dev_dbg(info->device, "Set %s as pixclock source.\n",
+                       (div == 2) ? "MCLK/2" : "MCLK");
+               old1f |= 0x40;
+               old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1;
+               if (div == 2)
+                       old1e |= 1;
 
-       default:
-               DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
-               assert (FALSE);
-               /* should never occur */
-               break;
-       }
-
-       regs->type = FB_TYPE_PACKED_PIXELS;
-
-       /* convert from ps to kHz */
-       freq = 1000000000 / var->pixclock;
-
-       DPRINTK ("desired pixclock: %ld kHz\n", freq);
-
-       maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
-       regs->multiplexing = 0;
-
-       /* If the frequency is greater than we can support, we might be able
-        * to use multiplexing for the video mode */
-       if (freq > maxclock) {
-               switch (cinfo->btype) {
-               case BT_ALPINE:
-               case BT_GD5480:
-                       regs->multiplexing = 1;
-                       break;
-
-               default:
-                       printk (KERN_WARNING "cirrusfb: ERROR: Frequency greater than maxclock (%ld kHz)\n", maxclock);
-                       DPRINTK ("EXIT - return -EINVAL\n");
-                       return -EINVAL;
-               }
-       }
-#if 0
-       /* TODO: If we have a 1MB 5434, we need to put ourselves in a mode where
-        * the VCLK is double the pixel clock. */
-       switch (var->bits_per_pixel) {
-       case 16:
-       case 32:
-               if (regs->HorizRes <= 800)
-                       freq /= 2;      /* Xbh has this type of clock for 32-bit */
-               break;
-       }
-#endif
-
-       bestclock (freq, &regs->freq, &regs->nom, &regs->den, &regs->div,
-                  maxclock);
-       regs->mclk = cirrusfb_get_mclk (freq, var->bits_per_pixel, &regs->divMCLK);
-
-       xres = var->xres;
-       hfront = var->right_margin;
-       hsync = var->hsync_len;
-       hback = var->left_margin;
-
-       yres = var->yres;
-       vfront = var->lower_margin;
-       vsync = var->vsync_len;
-       vback = var->upper_margin;
-
-       if (var->vmode & FB_VMODE_DOUBLE) {
-               yres *= 2;
-               vfront *= 2;
-               vsync *= 2;
-               vback *= 2;
-       } else if (var->vmode & FB_VMODE_INTERLACED) {
-               yres = (yres + 1) / 2;
-               vfront = (vfront + 1) / 2;
-               vsync = (vsync + 1) / 2;
-               vback = (vback + 1) / 2;
-       }
-       regs->HorizRes = xres;
-       regs->HorizTotal = (xres + hfront + hsync + hback) / 8 - 5;
-       regs->HorizDispEnd = xres / 8 - 1;
-       regs->HorizBlankStart = xres / 8;
-       regs->HorizBlankEnd = regs->HorizTotal + 5;     /* does not count with "-5" */
-       regs->HorizSyncStart = (xres + hfront) / 8 + 1;
-       regs->HorizSyncEnd = (xres + hfront + hsync) / 8 + 1;
-
-       regs->VertRes = yres;
-       regs->VertTotal = yres + vfront + vsync + vback - 2;
-       regs->VertDispEnd = yres - 1;
-       regs->VertBlankStart = yres;
-       regs->VertBlankEnd = regs->VertTotal;
-       regs->VertSyncStart = yres + vfront - 1;
-       regs->VertSyncEnd = yres + vfront + vsync - 1;
-
-       if (regs->VertRes >= 1024) {
-               regs->VertTotal /= 2;
-               regs->VertSyncStart /= 2;
-               regs->VertSyncEnd /= 2;
-               regs->VertDispEnd /= 2;
-       }
-       if (regs->multiplexing) {
-               regs->HorizTotal /= 2;
-               regs->HorizSyncStart /= 2;
-               regs->HorizSyncEnd /= 2;
-               regs->HorizDispEnd /= 2;
-       }
-
-       return 0;
-}
-
-
-static void cirrusfb_set_mclk (const struct cirrusfb_info *cinfo, int val, int div)
-{
-       assert (cinfo != NULL);
-
-       if (div == 2) {
-               /* VCLK = MCLK/2 */
-               unsigned char old = vga_rseq (cinfo->regbase, CL_SEQR1E);
-               vga_wseq (cinfo->regbase, CL_SEQR1E, old | 0x1);
-               vga_wseq (cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
-       } else if (div == 1) {
-               /* VCLK = MCLK */
-               unsigned char old = vga_rseq (cinfo->regbase, CL_SEQR1E);
-               vga_wseq (cinfo->regbase, CL_SEQR1E, old & ~0x1);
-               vga_wseq (cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
-       } else {
-               vga_wseq (cinfo->regbase, CL_SEQR1F, val & 0x3f);
+               vga_wseq(cinfo->regbase, CL_SEQR1E, old1e);
        }
+       vga_wseq(cinfo->regbase, CL_SEQR1F, old1f);
 }
 
 /*************************************************************************
@@ -1012,168 +656,280 @@ static void cirrusfb_set_mclk (const struct cirrusfb_info *cinfo, int val, int d
 
        actually writes the values for a new video mode into the hardware,
 **************************************************************************/
-static int cirrusfb_set_par_foo (struct fb_info *info)
+static int cirrusfb_set_par_foo(struct fb_info *info)
 {
        struct cirrusfb_info *cinfo = info->par;
        struct fb_var_screeninfo *var = &info->var;
-       struct cirrusfb_regs regs;
        u8 __iomem *regbase = cinfo->regbase;
        unsigned char tmp;
-       int offset = 0, err;
+       int pitch;
        const struct cirrusfb_board_info_rec *bi;
+       int hdispend, hsyncstart, hsyncend, htotal;
+       int yres, vdispend, vsyncstart, vsyncend, vtotal;
+       long freq;
+       int nom, den, div;
+       unsigned int control = 0, format = 0, threshold = 0;
 
-       DPRINTK ("ENTER\n");
-       DPRINTK ("Requested mode: %dx%dx%d\n",
+       dev_dbg(info->device, "Requested mode: %dx%dx%d\n",
               var->xres, var->yres, var->bits_per_pixel);
-       DPRINTK ("pixclock: %d\n", var->pixclock);
 
-       init_vgachip (cinfo);
+       switch (var->bits_per_pixel) {
+       case 1:
+               info->fix.line_length = var->xres_virtual / 8;
+               info->fix.visual = FB_VISUAL_MONO10;
+               break;
 
-       err = cirrusfb_decode_var(var, &regs, info);
-       if(err) {
-               /* should never happen */
-               DPRINTK("mode change aborted.  invalid var.\n");
-               return -EINVAL;
+       case 8:
+               info->fix.line_length = var->xres_virtual;
+               info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
+               break;
+
+       case 16:
+       case 24:
+               info->fix.line_length = var->xres_virtual *
+                                       var->bits_per_pixel >> 3;
+               info->fix.visual = FB_VISUAL_TRUECOLOR;
+               break;
        }
+       info->fix.type = FB_TYPE_PACKED_PIXELS;
+
+       init_vgachip(info);
 
        bi = &cirrusfb_board_info[cinfo->btype];
 
+       hsyncstart = var->xres + var->right_margin;
+       hsyncend = hsyncstart + var->hsync_len;
+       htotal = (hsyncend + var->left_margin) / 8;
+       hdispend = var->xres / 8;
+       hsyncstart = hsyncstart / 8;
+       hsyncend = hsyncend / 8;
+
+       vdispend = var->yres;
+       vsyncstart = vdispend + var->lower_margin;
+       vsyncend = vsyncstart + var->vsync_len;
+       vtotal = vsyncend + var->upper_margin;
+
+       if (var->vmode & FB_VMODE_DOUBLE) {
+               vdispend *= 2;
+               vsyncstart *= 2;
+               vsyncend *= 2;
+               vtotal *= 2;
+       } else if (var->vmode & FB_VMODE_INTERLACED) {
+               vdispend = (vdispend + 1) / 2;
+               vsyncstart = (vsyncstart + 1) / 2;
+               vsyncend = (vsyncend + 1) / 2;
+               vtotal = (vtotal + 1) / 2;
+       }
+       yres = vdispend;
+       if (yres >= 1024) {
+               vtotal /= 2;
+               vsyncstart /= 2;
+               vsyncend /= 2;
+               vdispend /= 2;
+       }
+
+       vdispend -= 1;
+       vsyncstart -= 1;
+       vsyncend -= 1;
+       vtotal -= 2;
+
+       if (cinfo->multiplexing) {
+               htotal /= 2;
+               hsyncstart /= 2;
+               hsyncend /= 2;
+               hdispend /= 2;
+       }
+
+       htotal -= 5;
+       hdispend -= 1;
+       hsyncstart += 1;
+       hsyncend += 1;
 
        /* unlock register VGA_CRTC_H_TOTAL..CRT7 */
-       vga_wcrt (regbase, VGA_CRTC_V_SYNC_END, 0x20);  /* previously: 0x00) */
+       vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20);   /* previously: 0x00) */
 
        /* if debugging is enabled, all parameters get output before writing */
-       DPRINTK ("CRT0: %ld\n", regs.HorizTotal);
-       vga_wcrt (regbase, VGA_CRTC_H_TOTAL, regs.HorizTotal);
+       dev_dbg(info->device, "CRT0: %d\n", htotal);
+       vga_wcrt(regbase, VGA_CRTC_H_TOTAL, htotal);
 
-       DPRINTK ("CRT1: %ld\n", regs.HorizDispEnd);
-       vga_wcrt (regbase, VGA_CRTC_H_DISP, regs.HorizDispEnd);
+       dev_dbg(info->device, "CRT1: %d\n", hdispend);
+       vga_wcrt(regbase, VGA_CRTC_H_DISP, hdispend);
 
-       DPRINTK ("CRT2: %ld\n", regs.HorizBlankStart);
-       vga_wcrt (regbase, VGA_CRTC_H_BLANK_START, regs.HorizBlankStart);
+       dev_dbg(info->device, "CRT2: %d\n", var->xres / 8);
+       vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8);
 
-       DPRINTK ("CRT3: 128+%ld\n", regs.HorizBlankEnd % 32);   /*  + 128: Compatible read */
-       vga_wcrt (regbase, VGA_CRTC_H_BLANK_END, 128 + (regs.HorizBlankEnd % 32));
+       /*  + 128: Compatible read */
+       dev_dbg(info->device, "CRT3: 128+%d\n", (htotal + 5) % 32);
+       vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
+                128 + ((htotal + 5) % 32));
 
-       DPRINTK ("CRT4: %ld\n", regs.HorizSyncStart);
-       vga_wcrt (regbase, VGA_CRTC_H_SYNC_START, regs.HorizSyncStart);
+       dev_dbg(info->device, "CRT4: %d\n", hsyncstart);
+       vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, hsyncstart);
 
-       tmp = regs.HorizSyncEnd % 32;
-       if (regs.HorizBlankEnd & 32)
+       tmp = hsyncend % 32;
+       if ((htotal + 5) & 32)
                tmp += 128;
-       DPRINTK ("CRT5: %d\n", tmp);
-       vga_wcrt (regbase, VGA_CRTC_H_SYNC_END, tmp);
+       dev_dbg(info->device, "CRT5: %d\n", tmp);
+       vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
 
-       DPRINTK ("CRT6: %ld\n", regs.VertTotal & 0xff);
-       vga_wcrt (regbase, VGA_CRTC_V_TOTAL, (regs.VertTotal & 0xff));
+       dev_dbg(info->device, "CRT6: %d\n", vtotal & 0xff);
+       vga_wcrt(regbase, VGA_CRTC_V_TOTAL, vtotal & 0xff);
 
        tmp = 16;               /* LineCompare bit #9 */
-       if (regs.VertTotal & 256)
+       if (vtotal & 256)
                tmp |= 1;
-       if (regs.VertDispEnd & 256)
+       if (vdispend & 256)
                tmp |= 2;
-       if (regs.VertSyncStart & 256)
+       if (vsyncstart & 256)
                tmp |= 4;
-       if (regs.VertBlankStart & 256)
+       if ((vdispend + 1) & 256)
                tmp |= 8;
-       if (regs.VertTotal & 512)
+       if (vtotal & 512)
                tmp |= 32;
-       if (regs.VertDispEnd & 512)
+       if (vdispend & 512)
                tmp |= 64;
-       if (regs.VertSyncStart & 512)
+       if (vsyncstart & 512)
                tmp |= 128;
-       DPRINTK ("CRT7: %d\n", tmp);
-       vga_wcrt (regbase, VGA_CRTC_OVERFLOW, tmp);
+       dev_dbg(info->device, "CRT7: %d\n", tmp);
+       vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
 
        tmp = 0x40;             /* LineCompare bit #8 */
-       if (regs.VertBlankStart & 512)
+       if ((vdispend + 1) & 512)
                tmp |= 0x20;
        if (var->vmode & FB_VMODE_DOUBLE)
                tmp |= 0x80;
-       DPRINTK ("CRT9: %d\n", tmp);
-       vga_wcrt (regbase, VGA_CRTC_MAX_SCAN, tmp);
+       dev_dbg(info->device, "CRT9: %d\n", tmp);
+       vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
 
-       DPRINTK ("CRT10: %ld\n", regs.VertSyncStart & 0xff);
-       vga_wcrt (regbase, VGA_CRTC_V_SYNC_START, (regs.VertSyncStart & 0xff));
+       dev_dbg(info->device, "CRT10: %d\n", vsyncstart & 0xff);
+       vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, vsyncstart & 0xff);
 
-       DPRINTK ("CRT11: 64+32+%ld\n", regs.VertSyncEnd % 16);
-       vga_wcrt (regbase, VGA_CRTC_V_SYNC_END, (regs.VertSyncEnd % 16 + 64 + 32));
+       dev_dbg(info->device, "CRT11: 64+32+%d\n", vsyncend % 16);
+       vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, vsyncend % 16 + 64 + 32);
 
-       DPRINTK ("CRT12: %ld\n", regs.VertDispEnd & 0xff);
-       vga_wcrt (regbase, VGA_CRTC_V_DISP_END, (regs.VertDispEnd & 0xff));
+       dev_dbg(info->device, "CRT12: %d\n", vdispend & 0xff);
+       vga_wcrt(regbase, VGA_CRTC_V_DISP_END, vdispend & 0xff);
 
-       DPRINTK ("CRT15: %ld\n", regs.VertBlankStart & 0xff);
-       vga_wcrt (regbase, VGA_CRTC_V_BLANK_START, (regs.VertBlankStart & 0xff));
+       dev_dbg(info->device, "CRT15: %d\n", (vdispend + 1) & 0xff);
+       vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, (vdispend + 1) & 0xff);
 
-       DPRINTK ("CRT16: %ld\n", regs.VertBlankEnd & 0xff);
-       vga_wcrt (regbase, VGA_CRTC_V_BLANK_END, (regs.VertBlankEnd & 0xff));
+       dev_dbg(info->device, "CRT16: %d\n", vtotal & 0xff);
+       vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, vtotal & 0xff);
 
-       DPRINTK ("CRT18: 0xff\n");
-       vga_wcrt (regbase, VGA_CRTC_LINE_COMPARE, 0xff);
+       dev_dbg(info->device, "CRT18: 0xff\n");
+       vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
 
        tmp = 0;
        if (var->vmode & FB_VMODE_INTERLACED)
                tmp |= 1;
-       if (regs.HorizBlankEnd & 64)
+       if ((htotal + 5) & 64)
                tmp |= 16;
-       if (regs.HorizBlankEnd & 128)
+       if ((htotal + 5) & 128)
                tmp |= 32;
-       if (regs.VertBlankEnd & 256)
+       if (vtotal & 256)
                tmp |= 64;
-       if (regs.VertBlankEnd & 512)
+       if (vtotal & 512)
                tmp |= 128;
 
-       DPRINTK ("CRT1a: %d\n", tmp);
-       vga_wcrt (regbase, CL_CRT1A, tmp);
+       dev_dbg(info->device, "CRT1a: %d\n", tmp);
+       vga_wcrt(regbase, CL_CRT1A, tmp);
+
+       freq = PICOS2KHZ(var->pixclock);
+       if (var->bits_per_pixel == 24)
+               if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64)
+                       freq *= 3;
+       if (cinfo->multiplexing)
+               freq /= 2;
+       if (cinfo->doubleVCLK)
+               freq *= 2;
+
+       bestclock(freq, &nom, &den, &div);
+
+       dev_dbg(info->device, "VCLK freq: %ld kHz  nom: %d  den: %d  div: %d\n",
+               freq, nom, den, div);
 
        /* set VCLK0 */
        /* hardware RefClock: 14.31818 MHz */
        /* formula: VClk = (OSC * N) / (D * (1+P)) */
        /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
 
-       vga_wseq (regbase, CL_SEQRB, regs.nom);
-       tmp = regs.den << 1;
-       if (regs.div != 0)
-               tmp |= 1;
-
-       if ((cinfo->btype == BT_SD64) ||
-           (cinfo->btype == BT_ALPINE) ||
-           (cinfo->btype == BT_GD5480))
-               tmp |= 0x80;    /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
+       if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4 ||
+           cinfo->btype == BT_SD64) {
+               /* if freq is close to mclk or mclk/2 select mclk
+                * as clock source
+                */
+               int divMCLK = cirrusfb_check_mclk(info, freq);
+               if (divMCLK)
+                       nom = 0;
+               cirrusfb_set_mclk_as_source(info, divMCLK);
+       }
+       if (is_laguna(cinfo)) {
+               long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc);
+               unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407);
+               unsigned short tile_control;
+
+               if (cinfo->btype == BT_LAGUNAB) {
+                       tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4);
+                       tile_control &= ~0x80;
+                       fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4);
+               }
 
-       DPRINTK ("CL_SEQR1B: %ld\n", (long) tmp);
-       vga_wseq (regbase, CL_SEQR1B, tmp);
+               fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc);
+               fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407);
+               control = fb_readw(cinfo->laguna_mmio + 0x402);
+               threshold = fb_readw(cinfo->laguna_mmio + 0xea);
+               control &= ~0x6800;
+               format = 0;
+               threshold &= 0xffc0 & 0x3fbf;
+       }
+       if (nom) {
+               tmp = den << 1;
+               if (div != 0)
+                       tmp |= 1;
+               /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
+               if ((cinfo->btype == BT_SD64) ||
+                   (cinfo->btype == BT_ALPINE) ||
+                   (cinfo->btype == BT_GD5480))
+                       tmp |= 0x80;
+
+               /* Laguna chipset has reversed clock registers */
+               if (is_laguna(cinfo)) {
+                       vga_wseq(regbase, CL_SEQRE, tmp);
+                       vga_wseq(regbase, CL_SEQR1E, nom);
+               } else {
+                       vga_wseq(regbase, CL_SEQRE, nom);
+                       vga_wseq(regbase, CL_SEQR1E, tmp);
+               }
+       }
 
-       if (regs.VertRes >= 1024)
+       if (yres >= 1024)
                /* 1280x1024 */
-               vga_wcrt (regbase, VGA_CRTC_MODE, 0xc7);
+               vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
        else
                /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
                 * address wrap, no compat. */
-               vga_wcrt (regbase, VGA_CRTC_MODE, 0xc3);
-
-/* HAEH?        vga_wcrt (regbase, VGA_CRTC_V_SYNC_END, 0x20);  * previously: 0x00  unlock VGA_CRTC_H_TOTAL..CRT7 */
+               vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
 
        /* don't know if it would hurt to also program this if no interlaced */
        /* mode is used, but I feel better this way.. :-) */
        if (var->vmode & FB_VMODE_INTERLACED)
-               vga_wcrt (regbase, VGA_CRTC_REGS, regs.HorizTotal / 2);
+               vga_wcrt(regbase, VGA_CRTC_REGS, htotal / 2);
        else
-               vga_wcrt (regbase, VGA_CRTC_REGS, 0x00);        /* interlace control */
+               vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
 
-       vga_wseq (regbase, VGA_SEQ_CHARACTER_MAP, 0);
-
-       /* adjust horizontal/vertical sync type (low/high) */
-       tmp = 0x03;             /* enable display memory & CRTC I/O address for color mode */
+       /* adjust horizontal/vertical sync type (low/high), use VCLK3 */
+       /* enable display memory & CRTC I/O address for color mode */
+       tmp = 0x03 | 0xc;
        if (var->sync & FB_SYNC_HOR_HIGH_ACT)
                tmp |= 0x40;
        if (var->sync & FB_SYNC_VERT_HIGH_ACT)
                tmp |= 0x80;
-       WGen (cinfo, VGA_MIS_W, tmp);
+       WGen(cinfo, VGA_MIS_W, tmp);
 
-       vga_wcrt (regbase, VGA_CRTC_PRESET_ROW, 0);     /* Screen A Preset Row-Scan register */
-       vga_wcrt (regbase, VGA_CRTC_CURSOR_START, 0);   /* text cursor on and start line */
-       vga_wcrt (regbase, VGA_CRTC_CURSOR_END, 31);    /* text cursor end line */
+       /* text cursor on and start line */
+       vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
+       /* text cursor end line */
+       vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
 
        /******************************************************
         *
@@ -1183,8 +939,8 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
 
        /* programming for different color depths */
        if (var->bits_per_pixel == 1) {
-               DPRINTK ("cirrusfb: preparing for 1 bit deep display\n");
-               vga_wgfx (regbase, VGA_GFX_MODE, 0);    /* mode register */
+               dev_dbg(info->device, "preparing for 1 bit deep display\n");
+               vga_wgfx(regbase, VGA_GFX_MODE, 0);     /* mode register */
 
                /* SR07 */
                switch (cinfo->btype) {
@@ -1195,72 +951,62 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
                case BT_PICASSO4:
                case BT_ALPINE:
                case BT_GD5480:
-                       DPRINTK (" (for GD54xx)\n");
-                       vga_wseq (regbase, CL_SEQR7,
-                                 regs.multiplexing ?
+                       vga_wseq(regbase, CL_SEQR7,
+                                cinfo->multiplexing ?
                                        bi->sr07_1bpp_mux : bi->sr07_1bpp);
                        break;
 
                case BT_LAGUNA:
-                       DPRINTK (" (for GD546x)\n");
-                       vga_wseq (regbase, CL_SEQR7,
-                               vga_rseq (regbase, CL_SEQR7) & ~0x01);
+               case BT_LAGUNAB:
+                       vga_wseq(regbase, CL_SEQR7,
+                               vga_rseq(regbase, CL_SEQR7) & ~0x01);
                        break;
 
                default:
-                       printk (KERN_WARNING "cirrusfb: unknown Board\n");
+                       dev_warn(info->device, "unknown Board\n");
                        break;
                }
 
                /* Extended Sequencer Mode */
                switch (cinfo->btype) {
-               case BT_SD64:
-                       /* setting the SEQRF on SD64 is not necessary (only during init) */
-                       DPRINTK ("(for SD64)\n");
-                       vga_wseq (regbase, CL_SEQR1F, 0x1a);            /*  MCLK select */
-                       break;
 
                case BT_PICCOLO:
-                       DPRINTK ("(for Piccolo)\n");
-/* ### ueberall 0x22? */
-                       vga_wseq (regbase, CL_SEQR1F, 0x22);            /* ##vorher 1c MCLK select */
-                       vga_wseq (regbase, CL_SEQRF, 0xb0);     /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
+               case BT_SPECTRUM:
+                       /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
+                       vga_wseq(regbase, CL_SEQRF, 0xb0);
                        break;
 
                case BT_PICASSO:
-                       DPRINTK ("(for Picasso)\n");
-                       vga_wseq (regbase, CL_SEQR1F, 0x22);            /* ##vorher 22 MCLK select */
-                       vga_wseq (regbase, CL_SEQRF, 0xd0);     /* ## vorher d0 avoid FIFO underruns..? */
-                       break;
-
-               case BT_SPECTRUM:
-                       DPRINTK ("(for Spectrum)\n");
-/* ### ueberall 0x22? */
-                       vga_wseq (regbase, CL_SEQR1F, 0x22);            /* ##vorher 1c MCLK select */
-                       vga_wseq (regbase, CL_SEQRF, 0xb0);     /* evtl d0? avoid FIFO underruns..? */
+                       /* ## vorher d0 avoid FIFO underruns..? */
+                       vga_wseq(regbase, CL_SEQRF, 0xd0);
                        break;
 
+               case BT_SD64:
                case BT_PICASSO4:
                case BT_ALPINE:
                case BT_GD5480:
                case BT_LAGUNA:
-                       DPRINTK (" (for GD54xx)\n");
+               case BT_LAGUNAB:
                        /* do nothing */
                        break;
 
                default:
-                       printk (KERN_WARNING "cirrusfb: unknown Board\n");
+                       dev_warn(info->device, "unknown Board\n");
                        break;
                }
 
-               WGen (cinfo, VGA_PEL_MSK, 0x01);        /* pixel mask: pass-through for first plane */
-               if (regs.multiplexing)
-                       WHDR (cinfo, 0x4a);     /* hidden dac reg: 1280x1024 */
+               /* pixel mask: pass-through for first plane */
+               WGen(cinfo, VGA_PEL_MSK, 0x01);
+               if (cinfo->multiplexing)
+                       /* hidden dac reg: 1280x1024 */
+                       WHDR(cinfo, 0x4a);
                else
-                       WHDR (cinfo, 0);        /* hidden dac: nothing */
-               vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x06);  /* memory mode: odd/even, ext. memory */
-               vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0x01);  /* plane mask: only write to first plane */
-               offset = var->xres_virtual / 16;
+                       /* hidden dac: nothing */
+                       WHDR(cinfo, 0);
+               /* memory mode: odd/even, ext. memory */
+               vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
+               /* plane mask: only write to first plane */
+               vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
        }
 
        /******************************************************
@@ -1270,7 +1016,7 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
         */
 
        else if (var->bits_per_pixel == 8) {
-               DPRINTK ("cirrusfb: preparing for 8 bit deep display\n");
+               dev_dbg(info->device, "preparing for 8 bit deep display\n");
                switch (cinfo->btype) {
                case BT_SD64:
                case BT_PICCOLO:
@@ -1279,76 +1025,57 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
                case BT_PICASSO4:
                case BT_ALPINE:
                case BT_GD5480:
-                       DPRINTK (" (for GD54xx)\n");
-                       vga_wseq (regbase, CL_SEQR7,
-                                 regs.multiplexing ?
+                       vga_wseq(regbase, CL_SEQR7,
+                                 cinfo->multiplexing ?
                                        bi->sr07_8bpp_mux : bi->sr07_8bpp);
                        break;
 
                case BT_LAGUNA:
-                       DPRINTK (" (for GD546x)\n");
-                       vga_wseq (regbase, CL_SEQR7,
-                               vga_rseq (regbase, CL_SEQR7) | 0x01);
+               case BT_LAGUNAB:
+                       vga_wseq(regbase, CL_SEQR7,
+                               vga_rseq(regbase, CL_SEQR7) | 0x01);
+                       threshold |= 0x10;
                        break;
 
                default:
-                       printk (KERN_WARNING "cirrusfb: unknown Board\n");
+                       dev_warn(info->device, "unknown Board\n");
                        break;
                }
 
                switch (cinfo->btype) {
-               case BT_SD64:
-                       vga_wseq (regbase, CL_SEQR1F, 0x1d);            /* MCLK select */
-                       break;
-
                case BT_PICCOLO:
-                       vga_wseq (regbase, CL_SEQR1F, 0x22);            /* ### vorher 1c MCLK select */
-                       vga_wseq (regbase, CL_SEQRF, 0xb0);     /* Fast Page-Mode writes */
-                       break;
-
                case BT_PICASSO:
-                       vga_wseq (regbase, CL_SEQR1F, 0x22);            /* ### vorher 1c MCLK select */
-                       vga_wseq (regbase, CL_SEQRF, 0xb0);     /* Fast Page-Mode writes */
-                       break;
-
                case BT_SPECTRUM:
-                       vga_wseq (regbase, CL_SEQR1F, 0x22);            /* ### vorher 1c MCLK select */
-                       vga_wseq (regbase, CL_SEQRF, 0xb0);     /* Fast Page-Mode writes */
+                       /* Fast Page-Mode writes */
+                       vga_wseq(regbase, CL_SEQRF, 0xb0);
                        break;
 
                case BT_PICASSO4:
 #ifdef CONFIG_ZORRO
-                       vga_wseq (regbase, CL_SEQRF, 0xb8);     /* ### INCOMPLETE!! */
+                       /* ### INCOMPLETE!! */
+                       vga_wseq(regbase, CL_SEQRF, 0xb8);
 #endif
-/*          vga_wseq (regbase, CL_SEQR1F, 0x1c); */
-                       break;
-
                case BT_ALPINE:
-                       DPRINTK (" (for GD543x)\n");
-                       cirrusfb_set_mclk (cinfo, regs.mclk, regs.divMCLK);
-                       /* We already set SRF and SR1F */
-                       break;
-
+               case BT_SD64:
                case BT_GD5480:
                case BT_LAGUNA:
-                       DPRINTK (" (for GD54xx)\n");
+               case BT_LAGUNAB:
                        /* do nothing */
                        break;
 
                default:
-                       printk (KERN_WARNING "cirrusfb: unknown Board\n");
+                       dev_warn(info->device, "unknown board\n");
                        break;
                }
 
-               vga_wgfx (regbase, VGA_GFX_MODE, 64);   /* mode register: 256 color mode */
-               WGen (cinfo, VGA_PEL_MSK, 0xff);        /* pixel mask: pass-through all planes */
-               if (regs.multiplexing)
-                       WHDR (cinfo, 0x4a);     /* hidden dac reg: 1280x1024 */
+               /* mode register: 256 color mode */
+               vga_wgfx(regbase, VGA_GFX_MODE, 64);
+               if (cinfo->multiplexing)
+                       /* hidden dac reg: 1280x1024 */
+                       WHDR(cinfo, 0x4a);
                else
-                       WHDR (cinfo, 0);        /* hidden dac: nothing */
-               vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x0a);  /* memory mode: chain4, ext. memory */
-               vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0xff);  /* plane mask: enable writing to all 4 planes */
-               offset = var->xres_virtual / 8;
+                       /* hidden dac: nothing */
+                       WHDR(cinfo, 0);
        }
 
        /******************************************************
@@ -1358,141 +1085,110 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
         */
 
        else if (var->bits_per_pixel == 16) {
-               DPRINTK ("cirrusfb: preparing for 16 bit deep display\n");
+               dev_dbg(info->device, "preparing for 16 bit deep display\n");
                switch (cinfo->btype) {
-               case BT_SD64:
-                       vga_wseq (regbase, CL_SEQR7, 0xf7);     /* Extended Sequencer Mode: 256c col. mode */
-                       vga_wseq (regbase, CL_SEQR1F, 0x1e);            /* MCLK select */
-                       break;
-
                case BT_PICCOLO:
-                       vga_wseq (regbase, CL_SEQR7, 0x87);
-                       vga_wseq (regbase, CL_SEQRF, 0xb0);     /* Fast Page-Mode writes */
-                       vga_wseq (regbase, CL_SEQR1F, 0x22);            /* MCLK select */
+               case BT_SPECTRUM:
+                       vga_wseq(regbase, CL_SEQR7, 0x87);
+                       /* Fast Page-Mode writes */
+                       vga_wseq(regbase, CL_SEQRF, 0xb0);
                        break;
 
                case BT_PICASSO:
-                       vga_wseq (regbase, CL_SEQR7, 0x27);
-                       vga_wseq (regbase, CL_SEQRF, 0xb0);     /* Fast Page-Mode writes */
-                       vga_wseq (regbase, CL_SEQR1F, 0x22);            /* MCLK select */
-                       break;
-
-               case BT_SPECTRUM:
-                       vga_wseq (regbase, CL_SEQR7, 0x87);
-                       vga_wseq (regbase, CL_SEQRF, 0xb0);     /* Fast Page-Mode writes */
-                       vga_wseq (regbase, CL_SEQR1F, 0x22);            /* MCLK select */
+                       vga_wseq(regbase, CL_SEQR7, 0x27);
+                       /* Fast Page-Mode writes */
+                       vga_wseq(regbase, CL_SEQRF, 0xb0);
                        break;
 
+               case BT_SD64:
                case BT_PICASSO4:
-                       vga_wseq (regbase, CL_SEQR7, 0x27);
-/*          vga_wseq (regbase, CL_SEQR1F, 0x1c);  */
-                       break;
-
                case BT_ALPINE:
-                       DPRINTK (" (for GD543x)\n");
-                       if (regs.HorizRes >= 1024)
-                               vga_wseq (regbase, CL_SEQR7, 0xa7);
-                       else
-                               vga_wseq (regbase, CL_SEQR7, 0xa3);
-                       cirrusfb_set_mclk (cinfo, regs.mclk, regs.divMCLK);
+                       /* Extended Sequencer Mode: 256c col. mode */
+                       vga_wseq(regbase, CL_SEQR7,
+                                       cinfo->doubleVCLK ? 0xa3 : 0xa7);
                        break;
 
                case BT_GD5480:
-                       DPRINTK (" (for GD5480)\n");
-                       vga_wseq (regbase, CL_SEQR7, 0x17);
+                       vga_wseq(regbase, CL_SEQR7, 0x17);
                        /* We already set SRF and SR1F */
                        break;
 
                case BT_LAGUNA:
-                       DPRINTK (" (for GD546x)\n");
-                       vga_wseq (regbase, CL_SEQR7,
-                               vga_rseq (regbase, CL_SEQR7) & ~0x01);
+               case BT_LAGUNAB:
+                       vga_wseq(regbase, CL_SEQR7,
+                               vga_rseq(regbase, CL_SEQR7) & ~0x01);
+                       control |= 0x2000;
+                       format |= 0x1400;
+                       threshold |= 0x10;
                        break;
 
                default:
-                       printk (KERN_WARNING "CIRRUSFB: unknown Board\n");
+                       dev_warn(info->device, "unknown Board\n");
                        break;
                }
 
-               vga_wgfx (regbase, VGA_GFX_MODE, 64);   /* mode register: 256 color mode */
-               WGen (cinfo, VGA_PEL_MSK, 0xff);        /* pixel mask: pass-through all planes */
+               /* mode register: 256 color mode */
+               vga_wgfx(regbase, VGA_GFX_MODE, 64);
 #ifdef CONFIG_PCI
-               WHDR (cinfo, 0xc0);     /* Copy Xbh */
+               WHDR(cinfo, cinfo->doubleVCLK ? 0xe1 : 0xc1);
 #elif defined(CONFIG_ZORRO)
                /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
-               WHDR (cinfo, 0xa0);     /* hidden dac reg: nothing special */
+               WHDR(cinfo, 0xa0);      /* hidden dac reg: nothing special */
 #endif
-               vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x0a);  /* memory mode: chain4, ext. memory */
-               vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0xff);  /* plane mask: enable writing to all 4 planes */
-               offset = var->xres_virtual / 4;
        }
 
        /******************************************************
         *
-        * 32 bpp
+        * 24 bpp
         *
         */
 
-       else if (var->bits_per_pixel == 32) {
-               DPRINTK ("cirrusfb: preparing for 24/32 bit deep display\n");
+       else if (var->bits_per_pixel == 24) {
+               dev_dbg(info->device, "preparing for 24 bit deep display\n");
                switch (cinfo->btype) {
-               case BT_SD64:
-                       vga_wseq (regbase, CL_SEQR7, 0xf9);     /* Extended Sequencer Mode: 256c col. mode */
-                       vga_wseq (regbase, CL_SEQR1F, 0x1e);            /* MCLK select */
-                       break;
-
                case BT_PICCOLO:
-                       vga_wseq (regbase, CL_SEQR7, 0x85);
-                       vga_wseq (regbase, CL_SEQRF, 0xb0);     /* Fast Page-Mode writes */
-                       vga_wseq (regbase, CL_SEQR1F, 0x22);            /* MCLK select */
+               case BT_SPECTRUM:
+                       vga_wseq(regbase, CL_SEQR7, 0x85);
+                       /* Fast Page-Mode writes */
+                       vga_wseq(regbase, CL_SEQRF, 0xb0);
                        break;
 
                case BT_PICASSO:
-                       vga_wseq (regbase, CL_SEQR7, 0x25);
-                       vga_wseq (regbase, CL_SEQRF, 0xb0);     /* Fast Page-Mode writes */
-                       vga_wseq (regbase, CL_SEQR1F, 0x22);            /* MCLK select */
-                       break;
-
-               case BT_SPECTRUM:
-                       vga_wseq (regbase, CL_SEQR7, 0x85);
-                       vga_wseq (regbase, CL_SEQRF, 0xb0);     /* Fast Page-Mode writes */
-                       vga_wseq (regbase, CL_SEQR1F, 0x22);            /* MCLK select */
+                       vga_wseq(regbase, CL_SEQR7, 0x25);
+                       /* Fast Page-Mode writes */
+                       vga_wseq(regbase, CL_SEQRF, 0xb0);
                        break;
 
+               case BT_SD64:
                case BT_PICASSO4:
-                       vga_wseq (regbase, CL_SEQR7, 0x25);
-/*          vga_wseq (regbase, CL_SEQR1F, 0x1c);  */
-                       break;
-
                case BT_ALPINE:
-                       DPRINTK (" (for GD543x)\n");
-                       vga_wseq (regbase, CL_SEQR7, 0xa9);
-                       cirrusfb_set_mclk (cinfo, regs.mclk, regs.divMCLK);
+                       /* Extended Sequencer Mode: 256c col. mode */
+                       vga_wseq(regbase, CL_SEQR7, 0xa5);
                        break;
 
                case BT_GD5480:
-                       DPRINTK (" (for GD5480)\n");
-                       vga_wseq (regbase, CL_SEQR7, 0x19);
+                       vga_wseq(regbase, CL_SEQR7, 0x15);
                        /* We already set SRF and SR1F */
                        break;
 
                case BT_LAGUNA:
-                       DPRINTK (" (for GD546x)\n");
-                       vga_wseq (regbase, CL_SEQR7,
-                               vga_rseq (regbase, CL_SEQR7) & ~0x01);
+               case BT_LAGUNAB:
+                       vga_wseq(regbase, CL_SEQR7,
+                               vga_rseq(regbase, CL_SEQR7) & ~0x01);
+                       control |= 0x4000;
+                       format |= 0x2400;
+                       threshold |= 0x20;
                        break;
 
                default:
-                       printk (KERN_WARNING "cirrusfb: unknown Board\n");
+                       dev_warn(info->device, "unknown Board\n");
                        break;
                }
 
-               vga_wgfx (regbase, VGA_GFX_MODE, 64);   /* mode register: 256 color mode */
-               WGen (cinfo, VGA_PEL_MSK, 0xff);        /* pixel mask: pass-through all planes */
-               WHDR (cinfo, 0xc5);     /* hidden dac reg: 8-8-8 mode (24 or 32) */
-               vga_wseq (regbase, VGA_SEQ_MEMORY_MODE, 0x0a);  /* memory mode: chain4, ext. memory */
-               vga_wseq (regbase, VGA_SEQ_PLANE_WRITE, 0xff);  /* plane mask: enable writing to all 4 planes */
-               offset = var->xres_virtual / 4;
+               /* mode register: 256 color mode */
+               vga_wgfx(regbase, VGA_GFX_MODE, 64);
+               /* hidden dac reg: 8-8-8 mode (24 or 32) */
+               WHDR(cinfo, 0xc5);
        }
 
        /******************************************************
@@ -1501,49 +1197,56 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
         *
         */
 
-       else {
-               printk (KERN_ERR "cirrusfb: What's this?? requested color depth == %d.\n",
+       else
+               dev_err(info->device,
+                       "What's this? requested color depth == %d.\n",
                        var->bits_per_pixel);
-       }
 
-       vga_wcrt (regbase, VGA_CRTC_OFFSET, offset & 0xff);
+       pitch = info->fix.line_length >> 3;
+       vga_wcrt(regbase, VGA_CRTC_OFFSET, pitch & 0xff);
        tmp = 0x22;
-       if (offset & 0x100)
+       if (pitch & 0x100)
                tmp |= 0x10;    /* offset overflow bit */
 
-       vga_wcrt (regbase, CL_CRT1B, tmp);      /* screen start addr #16-18, fastpagemode cycles */
+       /* screen start addr #16-18, fastpagemode cycles */
+       vga_wcrt(regbase, CL_CRT1B, tmp);
+
+       /* screen start address bit 19 */
+       if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
+               vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1);
 
-       if (cinfo->btype == BT_SD64 ||
-           cinfo->btype == BT_PICASSO4 ||
-           cinfo->btype == BT_ALPINE ||
-           cinfo->btype == BT_GD5480)
-               vga_wcrt (regbase, CL_CRT1D, 0x00);     /* screen start address bit 19 */
+       if (is_laguna(cinfo)) {
+               tmp = 0;
+               if ((htotal + 5) & 256)
+                       tmp |= 128;
+               if (hdispend & 256)
+                       tmp |= 64;
+               if (hsyncstart & 256)
+                       tmp |= 48;
+               if (vtotal & 1024)
+                       tmp |= 8;
+               if (vdispend & 1024)
+                       tmp |= 4;
+               if (vsyncstart & 1024)
+                       tmp |= 3;
 
-       vga_wcrt (regbase, VGA_CRTC_CURSOR_HI, 0);      /* text cursor location high */
-       vga_wcrt (regbase, VGA_CRTC_CURSOR_LO, 0);      /* text cursor location low */
-       vga_wcrt (regbase, VGA_CRTC_UNDERLINE, 0);      /* underline row scanline = at very bottom */
+               vga_wcrt(regbase, CL_CRT1E, tmp);
+               dev_dbg(info->device, "CRT1e: %d\n", tmp);
+       }
 
-       vga_wattr (regbase, VGA_ATC_MODE, 1);   /* controller mode */
-       vga_wattr (regbase, VGA_ATC_OVERSCAN, 0);               /* overscan (border) color */
-       vga_wattr (regbase, VGA_ATC_PLANE_ENABLE, 15);  /* color plane enable */
-       vga_wattr (regbase, CL_AR33, 0);        /* pixel panning */
-       vga_wattr (regbase, VGA_ATC_COLOR_PAGE, 0);     /* color select */
+       /* pixel panning */
+       vga_wattr(regbase, CL_AR33, 0);
 
        /* [ EGS: SetOffset(); ] */
        /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
-       AttrOn (cinfo);
-
-       vga_wgfx (regbase, VGA_GFX_SR_VALUE, 0);        /* set/reset register */
-       vga_wgfx (regbase, VGA_GFX_SR_ENABLE, 0);               /* set/reset enable */
-       vga_wgfx (regbase, VGA_GFX_COMPARE_VALUE, 0);   /* color compare */
-       vga_wgfx (regbase, VGA_GFX_DATA_ROTATE, 0);     /* data rotate */
-       vga_wgfx (regbase, VGA_GFX_PLANE_READ, 0);      /* read map select */
-       vga_wgfx (regbase, VGA_GFX_MISC, 1);    /* miscellaneous register */
-       vga_wgfx (regbase, VGA_GFX_COMPARE_MASK, 15);   /* color don't care */
-       vga_wgfx (regbase, VGA_GFX_BIT_MASK, 255);      /* bit mask */
-
-       vga_wseq (regbase, CL_SEQR12, 0x0);     /* graphics cursor attributes: nothing special */
+       AttrOn(cinfo);
 
+       if (is_laguna(cinfo)) {
+               /* no tiles */
+               fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402);
+               fb_writew(format, cinfo->laguna_mmio + 0xc0);
+               fb_writew(threshold, cinfo->laguna_mmio + 0xea);
+       }
        /* finally, turn on everything - turn off "FullBandwidth" bit */
        /* also, set "DotClock%2" bit where requested */
        tmp = 0x01;
@@ -1553,36 +1256,27 @@ static int cirrusfb_set_par_foo (struct fb_info *info)
        tmp |= 0x08;
 */
 
-       vga_wseq (regbase, VGA_SEQ_CLOCK_MODE, tmp);
-       DPRINTK ("CL_SEQR1: %d\n", tmp);
-
-       cinfo->currentmode = regs;
-       info->fix.type = regs.type;
-       info->fix.visual = regs.visual;
-       info->fix.line_length = regs.line_length;
-
-       /* pan to requested offset */
-       cirrusfb_pan_display (var, info);
+       vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
+       dev_dbg(info->device, "CL_SEQR1: %d\n", tmp);
 
 #ifdef CIRRUSFB_DEBUG
-       cirrusfb_dump ();
+       cirrusfb_dbg_reg_dump(info, NULL);
 #endif
 
-       DPRINTK ("EXIT\n");
        return 0;
 }
 
 /* for some reason incomprehensible to me, cirrusfb requires that you write
  * the registers twice for the settings to take..grr. -dte */
-static int cirrusfb_set_par (struct fb_info *info)
+static int cirrusfb_set_par(struct fb_info *info)
 {
-       cirrusfb_set_par_foo (info);
-       return cirrusfb_set_par_foo (info);
+       cirrusfb_set_par_foo(info);
+       return cirrusfb_set_par_foo(info);
 }
 
-static int cirrusfb_setcolreg (unsigned regno, unsigned red, unsigned green,
-                              unsigned blue, unsigned transp,
-                              struct fb_info *info)
+static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
+                             unsigned blue, unsigned transp,
+                             struct fb_info *info)
 {
        struct cirrusfb_info *cinfo = info->par;
 
@@ -1595,34 +1289,18 @@ static int cirrusfb_setcolreg (unsigned regno, unsigned red, unsigned green,
                green >>= (16 - info->var.green.length);
                blue >>= (16 - info->var.blue.length);
 
-               if (regno>=16)
+               if (regno >= 16)
                        return 1;
                v = (red << info->var.red.offset) |
                    (green << info->var.green.offset) |
                    (blue << info->var.blue.offset);
 
-               switch (info->var.bits_per_pixel) {
-                       case 8:
-                               cinfo->pseudo_palette[regno] = v;
-                               break;
-                       case 16:
-                               cinfo->pseudo_palette[regno] = v;
-                               break;
-                       case 24:
-                       case 32:
-                               cinfo->pseudo_palette[regno] = v;
-                               break;
-               }
+               cinfo->pseudo_palette[regno] = v;
                return 0;
        }
 
-       cinfo->palette[regno].red = red;
-       cinfo->palette[regno].green = green;
-       cinfo->palette[regno].blue = blue;
-
-       if (info->var.bits_per_pixel == 8) {
-                       WClut (cinfo, regno, red >> 10, green >> 10, blue >> 10);
-       }
+       if (info->var.bits_per_pixel == 8)
+               WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
 
        return 0;
 
@@ -1633,30 +1311,22 @@ static int cirrusfb_setcolreg (unsigned regno, unsigned red, unsigned green,
 
        performs display panning - provided hardware permits this
 **************************************************************************/
-static int cirrusfb_pan_display (struct fb_var_screeninfo *var,
-                                struct fb_info *info)
+static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
+                               struct fb_info *info)
 {
-       int xoffset = 0;
-       int yoffset = 0;
+       int xoffset;
        unsigned long base;
-       unsigned char tmp = 0, tmp2 = 0, xpix;
+       unsigned char tmp, xpix;
        struct cirrusfb_info *cinfo = info->par;
 
-       DPRINTK ("ENTER\n");
-       DPRINTK ("virtual offset: (%d,%d)\n", var->xoffset, var->yoffset);
-
        /* no range checks for xoffset and yoffset,   */
        /* as fb_pan_display has already done this */
        if (var->vmode & FB_VMODE_YWRAP)
                return -EINVAL;
 
-       info->var.xoffset = var->xoffset;
-       info->var.yoffset = var->yoffset;
-
        xoffset = var->xoffset * info->var.bits_per_pixel / 8;
-       yoffset = var->yoffset;
 
-       base = yoffset * cinfo->currentmode.line_length + xoffset;
+       base = var->yoffset * info->fix.line_length + xoffset;
 
        if (info->var.bits_per_pixel == 1) {
                /* base is already correct */
@@ -1666,12 +1336,15 @@ static int cirrusfb_pan_display (struct fb_var_screeninfo *var,
                xpix = (unsigned char) ((xoffset % 4) * 2);
        }
 
-        cirrusfb_WaitBLT(cinfo->regbase); /* make sure all the BLT's are done */
+       if (!is_laguna(cinfo))
+               cirrusfb_WaitBLT(cinfo->regbase);
 
        /* lower 8 + 8 bits of screen start address */
-       vga_wcrt (cinfo->regbase, VGA_CRTC_START_LO, (unsigned char) (base & 0xff));
-       vga_wcrt (cinfo->regbase, VGA_CRTC_START_HI, (unsigned char) (base >> 8));
+       vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff);
+       vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff);
 
+       /* 0xf2 is %11110010, exclude tmp bits */
+       tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2;
        /* construct bits 16, 17 and 18 of screen start address */
        if (base & 0x10000)
                tmp |= 0x01;
@@ -1680,292 +1353,322 @@ static int cirrusfb_pan_display (struct fb_var_screeninfo *var,
        if (base & 0x40000)
                tmp |= 0x08;
 
-       tmp2 = (vga_rcrt (cinfo->regbase, CL_CRT1B) & 0xf2) | tmp;      /* 0xf2 is %11110010, exclude tmp bits */
-       vga_wcrt (cinfo->regbase, CL_CRT1B, tmp2);
+       vga_wcrt(cinfo->regbase, CL_CRT1B, tmp);
 
        /* construct bit 19 of screen start address */
        if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
-               tmp2 = 0;
-               if (base & 0x80000)
-                       tmp2 = 0x80;
-               vga_wcrt (cinfo->regbase, CL_CRT1D, tmp2);
+               tmp = vga_rcrt(cinfo->regbase, CL_CRT1D);
+               if (is_laguna(cinfo))
+                       tmp = (tmp & ~0x18) | ((base >> 16) & 0x18);
+               else
+                       tmp = (tmp & ~0x80) | ((base >> 12) & 0x80);
+               vga_wcrt(cinfo->regbase, CL_CRT1D, tmp);
        }
 
-       /* write pixel panning value to AR33; this does not quite work in 8bpp */
-       /* ### Piccolo..? Will this work? */
+       /* write pixel panning value to AR33; this does not quite work in 8bpp
+        *
+        * ### Piccolo..? Will this work?
+        */
        if (info->var.bits_per_pixel == 1)
-               vga_wattr (cinfo->regbase, CL_AR33, xpix);
+               vga_wattr(cinfo->regbase, CL_AR33, xpix);
 
-       cirrusfb_WaitBLT (cinfo->regbase);
-
-       DPRINTK ("EXIT\n");
-       return (0);
+       return 0;
 }
 
-
-static int cirrusfb_blank (int blank_mode, struct fb_info *info)
+static int cirrusfb_blank(int blank_mode, struct fb_info *info)
 {
        /*
-        *  Blank the screen if blank_mode != 0, else unblank. If blank == NULL
-        *  then the caller blanks by setting the CLUT (Color Look Up Table) to all
-        *  black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
-        *  to e.g. a video mode which doesn't support it. Implements VESA suspend
-        *  and powerdown modes on hardware that supports disabling hsync/vsync:
-        *    blank_mode == 2: suspend vsync
-        *    blank_mode == 3: suspend hsync
-        *    blank_mode == 4: powerdown
+        * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
+        * then the caller blanks by setting the CLUT (Color Look Up Table)
+        * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking
+        * failed due to e.g. a video mode which doesn't support it.
+        * Implements VESA suspend and powerdown modes on hardware that
+        * supports disabling hsync/vsync:
+        *   blank_mode == 2: suspend vsync
+        *   blank_mode == 3: suspend hsync
+        *   blank_mode == 4: powerdown
         */
        unsigned char val;
        struct cirrusfb_info *cinfo = info->par;
        int current_mode = cinfo->blank_mode;
 
-       DPRINTK ("ENTER, blank mode = %d\n", blank_mode);
+       dev_dbg(info->device, "ENTER, blank mode = %d\n", blank_mode);
 
        if (info->state != FBINFO_STATE_RUNNING ||
            current_mode == blank_mode) {
-               DPRINTK ("EXIT, returning 0\n");
+               dev_dbg(info->device, "EXIT, returning 0\n");
                return 0;
        }
 
        /* Undo current */
        if (current_mode == FB_BLANK_NORMAL ||
-           current_mode == FB_BLANK_UNBLANK) {
-               /* unblank the screen */
-               val = vga_rseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE);
-               vga_wseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE, val & 0xdf);      /* clear "FullBandwidth" bit */
-               /* and undo VESA suspend trickery */
-               vga_wgfx (cinfo->regbase, CL_GRE, 0x00);
-       }
+           current_mode == FB_BLANK_UNBLANK)
+               /* clear "FullBandwidth" bit */
+               val = 0;
+       else
+               /* set "FullBandwidth" bit */
+               val = 0x20;
 
-       /* set new */
-       if(blank_mode > FB_BLANK_NORMAL) {
-               /* blank the screen */
-               val = vga_rseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE);
-               vga_wseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE, val | 0x20);      /* set "FullBandwidth" bit */
-       }
+       val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf;
+       vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val);
 
        switch (blank_mode) {
        case FB_BLANK_UNBLANK:
        case FB_BLANK_NORMAL:
+               val = 0x00;
                break;
        case FB_BLANK_VSYNC_SUSPEND:
-               vga_wgfx (cinfo->regbase, CL_GRE, 0x04);
+               val = 0x04;
                break;
        case FB_BLANK_HSYNC_SUSPEND:
-               vga_wgfx (cinfo->regbase, CL_GRE, 0x02);
+               val = 0x02;
                break;
        case FB_BLANK_POWERDOWN:
-               vga_wgfx (cinfo->regbase, CL_GRE, 0x06);
+               val = 0x06;
                break;
        default:
-               DPRINTK ("EXIT, returning 1\n");
+               dev_dbg(info->device, "EXIT, returning 1\n");
                return 1;
        }
 
+       vga_wgfx(cinfo->regbase, CL_GRE, val);
+
        cinfo->blank_mode = blank_mode;
-       DPRINTK ("EXIT, returning 0\n");
+       dev_dbg(info->device, "EXIT, returning 0\n");
 
        /* Let fbcon do a soft blank for us */
        return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
 }
+
 /**** END   Hardware specific Routines **************************************/
 /****************************************************************************/
 /**** BEGIN Internal Routines ***********************************************/
 
-static void init_vgachip (struct cirrusfb_info *cinfo)
+static void init_vgachip(struct fb_info *info)
 {
+       struct cirrusfb_info *cinfo = info->par;
        const struct cirrusfb_board_info_rec *bi;
 
-       DPRINTK ("ENTER\n");
-
-       assert (cinfo != NULL);
+       assert(cinfo != NULL);
 
        bi = &cirrusfb_board_info[cinfo->btype];
 
        /* reset board globally */
        switch (cinfo->btype) {
        case BT_PICCOLO:
-               WSFR (cinfo, 0x01);
-               udelay (500);
-               WSFR (cinfo, 0x51);
-               udelay (500);
+               WSFR(cinfo, 0x01);
+               udelay(500);
+               WSFR(cinfo, 0x51);
+               udelay(500);
                break;
        case BT_PICASSO:
-               WSFR2 (cinfo, 0xff);
-               udelay (500);
+               WSFR2(cinfo, 0xff);
+               udelay(500);
                break;
        case BT_SD64:
        case BT_SPECTRUM:
-               WSFR (cinfo, 0x1f);
-               udelay (500);
-               WSFR (cinfo, 0x4f);
-               udelay (500);
+               WSFR(cinfo, 0x1f);
+               udelay(500);
+               WSFR(cinfo, 0x4f);
+               udelay(500);
                break;
        case BT_PICASSO4:
-               vga_wcrt (cinfo->regbase, CL_CRT51, 0x00);      /* disable flickerfixer */
-               mdelay (100);
-               vga_wgfx (cinfo->regbase, CL_GR2F, 0x00);       /* from Klaus' NetBSD driver: */
-               vga_wgfx (cinfo->regbase, CL_GR33, 0x00);       /* put blitter into 542x compat */
-               vga_wgfx (cinfo->regbase, CL_GR31, 0x00);       /* mode */
-               break;
-
-       case BT_GD5480:
-               vga_wgfx (cinfo->regbase, CL_GR2F, 0x00);       /* from Klaus' NetBSD driver: */
+               /* disable flickerfixer */
+               vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
+               mdelay(100);
+               /* mode */
+               vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
+       case BT_GD5480:  /* fall through */
+               /* from Klaus' NetBSD driver: */
+               vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
+       case BT_ALPINE:  /* fall through */
+               /* put blitter into 542x compat */
+               vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
                break;
 
-       case BT_ALPINE:
+       case BT_LAGUNA:
+       case BT_LAGUNAB:
                /* Nothing to do to reset the board. */
                break;
 
        default:
-               printk (KERN_ERR "cirrusfb: Warning: Unknown board type\n");
+               dev_err(info->device, "Warning: Unknown board type\n");
                break;
        }
 
-       assert (cinfo->size > 0); /* make sure RAM size set by this point */
+       /* make sure RAM size set by this point */
+       assert(info->screen_size > 0);
 
        /* the P4 is not fully initialized here; I rely on it having been */
        /* inited under AmigaOS already, which seems to work just fine    */
-       /* (Klaus advised to do it this way)                              */
+       /* (Klaus advised to do it this way)                          */
 
        if (cinfo->btype != BT_PICASSO4) {
-               WGen (cinfo, CL_VSSM, 0x10);    /* EGS: 0x16 */
-               WGen (cinfo, CL_POS102, 0x01);
-               WGen (cinfo, CL_VSSM, 0x08);    /* EGS: 0x0e */
+               WGen(cinfo, CL_VSSM, 0x10);     /* EGS: 0x16 */
+               WGen(cinfo, CL_POS102, 0x01);
+               WGen(cinfo, CL_VSSM, 0x08);     /* EGS: 0x0e */
 
                if (cinfo->btype != BT_SD64)
-                       WGen (cinfo, CL_VSSM2, 0x01);
+                       WGen(cinfo, CL_VSSM2, 0x01);
 
-               vga_wseq (cinfo->regbase, CL_SEQR0, 0x03);      /* reset sequencer logic */
+               /* reset sequencer logic */
+               vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03);
 
-               vga_wseq (cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);    /* FullBandwidth (video off) and 8/9 dot clock */
-               WGen (cinfo, VGA_MIS_W, 0xc1);  /* polarity (-/-), disable access to display memory, VGA_CRTC_START_HI base address: color */
+               /* FullBandwidth (video off) and 8/9 dot clock */
+               vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
 
-/*      vga_wgfx (cinfo->regbase, CL_GRA, 0xce);    "magic cookie" - doesn't make any sense to me.. */
-               vga_wseq (cinfo->regbase, CL_SEQR6, 0x12);      /* unlock all extension registers */
-
-               vga_wgfx (cinfo->regbase, CL_GR31, 0x04);       /* reset blitter */
+               /* "magic cookie" - doesn't make any sense to me.. */
+/*      vga_wgfx(cinfo->regbase, CL_GRA, 0xce);   */
+               /* unlock all extension registers */
+               vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
 
                switch (cinfo->btype) {
                case BT_GD5480:
-                       vga_wseq (cinfo->regbase, CL_SEQRF, 0x98);
+                       vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
                        break;
                case BT_ALPINE:
+               case BT_LAGUNA:
+               case BT_LAGUNAB:
                        break;
                case BT_SD64:
-                       vga_wseq (cinfo->regbase, CL_SEQRF, 0xb8);
+#ifdef CONFIG_ZORRO
+                       vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
+#endif
                        break;
                default:
-                       vga_wseq (cinfo->regbase, CL_SEQR16, 0x0f);
-                       vga_wseq (cinfo->regbase, CL_SEQRF, 0xb0);
+                       vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
+                       vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
                        break;
                }
        }
-       vga_wseq (cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);   /* plane mask: nothing */
-       vga_wseq (cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00); /* character map select: doesn't even matter in gx mode */
-       vga_wseq (cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0e);   /* memory mode: chain-4, no odd/even, ext. memory */
+       /* plane mask: nothing */
+       vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
+       /* character map select: doesn't even matter in gx mode */
+       vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
+       /* memory mode: chain4, ext. memory */
+       vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
 
        /* controller-internal base address of video memory */
        if (bi->init_sr07)
-               vga_wseq (cinfo->regbase, CL_SEQR7, bi->sr07);
+               vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
 
-       /*  vga_wseq (cinfo->regbase, CL_SEQR8, 0x00); *//* EEPROM control: shouldn't be necessary to write to this at all.. */
+       /*  vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
+       /* EEPROM control: shouldn't be necessary to write to this at all.. */
 
-       vga_wseq (cinfo->regbase, CL_SEQR10, 0x00);             /* graphics cursor X position (incomplete; position gives rem. 3 bits */
-       vga_wseq (cinfo->regbase, CL_SEQR11, 0x00);             /* graphics cursor Y position (..."... ) */
-       vga_wseq (cinfo->regbase, CL_SEQR12, 0x00);             /* graphics cursor attributes */
-       vga_wseq (cinfo->regbase, CL_SEQR13, 0x00);             /* graphics cursor pattern address */
+       /* graphics cursor X position (incomplete; position gives rem. 3 bits */
+       vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
+       /* graphics cursor Y position (..."... ) */
+       vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
+       /* graphics cursor attributes */
+       vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
+       /* graphics cursor pattern address */
+       vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
 
        /* writing these on a P4 might give problems..  */
        if (cinfo->btype != BT_PICASSO4) {
-               vga_wseq (cinfo->regbase, CL_SEQR17, 0x00);             /* configuration readback and ext. color */
-               vga_wseq (cinfo->regbase, CL_SEQR18, 0x02);             /* signature generator */
-       }
-
-       /* MCLK select etc. */
-       if (bi->init_sr1f)
-               vga_wseq (cinfo->regbase, CL_SEQR1F, bi->sr1f);
-
-       vga_wcrt (cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);   /* Screen A preset row scan: none */
-       vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20); /* Text cursor start: disable text cursor */
-       vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);   /* Text cursor end: - */
-       vga_wcrt (cinfo->regbase, VGA_CRTC_START_HI, 0x00);     /* Screen start address high: 0 */
-       vga_wcrt (cinfo->regbase, VGA_CRTC_START_LO, 0x00);     /* Screen start address low: 0 */
-       vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);    /* text cursor location high: 0 */
-       vga_wcrt (cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);    /* text cursor location low: 0 */
-
-       vga_wcrt (cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);    /* Underline Row scanline: - */
-       vga_wcrt (cinfo->regbase, VGA_CRTC_MODE, 0xc3); /* mode control: timing enable, byte mode, no compat modes */
-       vga_wcrt (cinfo->regbase, VGA_CRTC_LINE_COMPARE, 0x00); /* Line Compare: not needed */
+               /* configuration readback and ext. color */
+               vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
+               /* signature generator */
+               vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
+       }
+
+       /* Screen A preset row scan: none */
+       vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
+       /* Text cursor start: disable text cursor */
+       vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
+       /* Text cursor end: - */
+       vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
+       /* text cursor location high: 0 */
+       vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
+       /* text cursor location low: 0 */
+       vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
+
+       /* Underline Row scanline: - */
+       vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
        /* ### add 0x40 for text modes with > 30 MHz pixclock */
-       vga_wcrt (cinfo->regbase, CL_CRT1B, 0x02);      /* ext. display controls: ext.adr. wrap */
-
-       vga_wgfx (cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);      /* Set/Reset registes: - */
-       vga_wgfx (cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);     /* Set/Reset enable: - */
-       vga_wgfx (cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00); /* Color Compare: - */
-       vga_wgfx (cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);   /* Data Rotate: - */
-       vga_wgfx (cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);    /* Read Map Select: - */
-       vga_wgfx (cinfo->regbase, VGA_GFX_MODE, 0x00);  /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
-       vga_wgfx (cinfo->regbase, VGA_GFX_MISC, 0x01);  /* Miscellaneous: memory map base address, graphics mode */
-       vga_wgfx (cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);  /* Color Don't care: involve all planes */
-       vga_wgfx (cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);      /* Bit Mask: no mask at all */
-       if (cinfo->btype == BT_ALPINE)
-               vga_wgfx (cinfo->regbase, CL_GRB, 0x20);        /* (5434 can't have bit 3 set for bitblt) */
+       /* ext. display controls: ext.adr. wrap */
+       vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
+
+       /* Set/Reset registes: - */
+       vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
+       /* Set/Reset enable: - */
+       vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
+       /* Color Compare: - */
+       vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
+       /* Data Rotate: - */
+       vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
+       /* Read Map Select: - */
+       vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
+       /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
+       vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
+       /* Miscellaneous: memory map base address, graphics mode */
+       vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
+       /* Color Don't care: involve all planes */
+       vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
+       /* Bit Mask: no mask at all */
+       vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
+
+       if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64 ||
+           is_laguna(cinfo))
+               /* (5434 can't have bit 3 set for bitblt) */
+               vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
        else
-               vga_wgfx (cinfo->regbase, CL_GRB, 0x28);        /* Graphics controller mode extensions: finer granularity, 8byte data latches */
-
-       vga_wgfx (cinfo->regbase, CL_GRC, 0xff);        /* Color Key compare: - */
-       vga_wgfx (cinfo->regbase, CL_GRD, 0x00);        /* Color Key compare mask: - */
-       vga_wgfx (cinfo->regbase, CL_GRE, 0x00);        /* Miscellaneous control: - */
-       /*  vga_wgfx (cinfo->regbase, CL_GR10, 0x00); *//* Background color byte 1: - */
-/*  vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
-
-       vga_wattr (cinfo->regbase, VGA_ATC_PALETTE0, 0x00);     /* Attribute Controller palette registers: "identity mapping" */
-       vga_wattr (cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
-       vga_wattr (cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
-       vga_wattr (cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
-       vga_wattr (cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
-       vga_wattr (cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
-       vga_wattr (cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
-       vga_wattr (cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
-       vga_wattr (cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
-       vga_wattr (cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
-       vga_wattr (cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
-       vga_wattr (cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
-       vga_wattr (cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
-       vga_wattr (cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
-       vga_wattr (cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
-       vga_wattr (cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
-
-       vga_wattr (cinfo->regbase, VGA_ATC_MODE, 0x01); /* Attribute Controller mode: graphics mode */
-       vga_wattr (cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);     /* Overscan color reg.: reg. 0 */
-       vga_wattr (cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f); /* Color Plane enable: Enable all 4 planes */
-/* ###  vga_wattr (cinfo->regbase, CL_AR33, 0x00); * Pixel Panning: - */
-       vga_wattr (cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);   /* Color Select: - */
-
-       WGen (cinfo, VGA_PEL_MSK, 0xff);        /* Pixel mask: no mask */
-
-       if (cinfo->btype != BT_ALPINE && cinfo->btype != BT_GD5480)
-               WGen (cinfo, VGA_MIS_W, 0xc3);  /* polarity (-/-), enable display mem, VGA_CRTC_START_HI i/o base = color */
-
-       vga_wgfx (cinfo->regbase, CL_GR31, 0x04);       /* BLT Start/status: Blitter reset */
-       vga_wgfx (cinfo->regbase, CL_GR31, 0x00);       /* - " -           : "end-of-reset" */
+       /* Graphics controller mode extensions: finer granularity,
+        * 8byte data latches
+        */
+               vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
+
+       vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
+       vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
+       vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
+       /* Background color byte 1: - */
+       /*  vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
+       /*  vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
+
+       /* Attribute Controller palette registers: "identity mapping" */
+       vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
+       vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
+       vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
+       vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
+       vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
+       vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
+       vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
+       vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
+       vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
+       vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
+       vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
+       vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
+       vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
+       vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
+       vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
+       vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
+
+       /* Attribute Controller mode: graphics mode */
+       vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
+       /* Overscan color reg.: reg. 0 */
+       vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
+       /* Color Plane enable: Enable all 4 planes */
+       vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
+       /* Color Select: - */
+       vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
+
+       WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
+
+       /* BLT Start/status: Blitter reset */
+       vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
+       /* - " -           : "end-of-reset" */
+       vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
 
        /* misc... */
-       WHDR (cinfo, 0);        /* Hidden DAC register: - */
-
-       printk (KERN_DEBUG "cirrusfb: This board has %ld bytes of DRAM memory\n", cinfo->size);
-       DPRINTK ("EXIT\n");
+       WHDR(cinfo, 0); /* Hidden DAC register: - */
        return;
 }
 
-static void switch_monitor (struct cirrusfb_info *cinfo, int on)
+static void switch_monitor(struct cirrusfb_info *cinfo, int on)
 {
 #ifdef CONFIG_ZORRO /* only works on Zorro boards */
        static int IsOn = 0;    /* XXX not ok for multiple boards */
 
-       DPRINTK ("ENTER\n");
-
        if (cinfo->btype == BT_PICASSO4)
                return;         /* nothing to switch */
        if (cinfo->btype == BT_ALPINE)
@@ -1974,77 +1677,64 @@ static void switch_monitor (struct cirrusfb_info *cinfo, int on)
                return;         /* nothing to switch */
        if (cinfo->btype == BT_PICASSO) {
                if ((on && !IsOn) || (!on && IsOn))
-                       WSFR (cinfo, 0xff);
-
-               DPRINTK ("EXIT\n");
+                       WSFR(cinfo, 0xff);
                return;
        }
        if (on) {
                switch (cinfo->btype) {
                case BT_SD64:
-                       WSFR (cinfo, cinfo->SFR | 0x21);
+                       WSFR(cinfo, cinfo->SFR | 0x21);
                        break;
                case BT_PICCOLO:
-                       WSFR (cinfo, cinfo->SFR | 0x28);
+                       WSFR(cinfo, cinfo->SFR | 0x28);
                        break;
                case BT_SPECTRUM:
-                       WSFR (cinfo, 0x6f);
+                       WSFR(cinfo, 0x6f);
                        break;
                default: /* do nothing */ break;
                }
        } else {
                switch (cinfo->btype) {
                case BT_SD64:
-                       WSFR (cinfo, cinfo->SFR & 0xde);
+                       WSFR(cinfo, cinfo->SFR & 0xde);
                        break;
                case BT_PICCOLO:
-                       WSFR (cinfo, cinfo->SFR & 0xd7);
+                       WSFR(cinfo, cinfo->SFR & 0xd7);
                        break;
                case BT_SPECTRUM:
-                       WSFR (cinfo, 0x4f);
+                       WSFR(cinfo, 0x4f);
+                       break;
+               default: /* do nothing */
                        break;
-               default: /* do nothing */ break;
                }
        }
-
-       DPRINTK ("EXIT\n");
 #endif /* CONFIG_ZORRO */
 }
 
-
 /******************************************/
 /* Linux 2.6-style  accelerated functions */
 /******************************************/
 
-static void cirrusfb_prim_fillrect(struct cirrusfb_info *cinfo,
-                                  const struct fb_fillrect *region)
+static int cirrusfb_sync(struct fb_info *info)
 {
-       int m; /* bytes per pixel */
-       u32 color = (cinfo->info->fix.visual == FB_VISUAL_TRUECOLOR) ?
-               cinfo->pseudo_palette[region->color] : region->color;
+       struct cirrusfb_info *cinfo = info->par;
 
-       if(cinfo->info->var.bits_per_pixel == 1) {
-               cirrusfb_RectFill(cinfo->regbase, cinfo->info->var.bits_per_pixel,
-                                 region->dx / 8, region->dy,
-                                 region->width / 8, region->height,
-                                 color,
-                                 cinfo->currentmode.line_length);
-       } else {
-               m = ( cinfo->info->var.bits_per_pixel + 7 ) / 8;
-               cirrusfb_RectFill(cinfo->regbase, cinfo->info->var.bits_per_pixel,
-                                 region->dx * m, region->dy,
-                                 region->width * m, region->height,
-                                 color,
-                                 cinfo->currentmode.line_length);
+       if (!is_laguna(cinfo)) {
+               while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03)
+                       cpu_relax();
        }
-       return;
+       return 0;
 }
 
-static void cirrusfb_fillrect (struct fb_info *info, const struct fb_fillrect *region)
+static void cirrusfb_fillrect(struct fb_info *info,
+                             const struct fb_fillrect *region)
 {
-       struct cirrusfb_info *cinfo = info->par;
        struct fb_fillrect modded;
        int vxres, vyres;
+       struct cirrusfb_info *cinfo = info->par;
+       int m = info->var.bits_per_pixel;
+       u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
+               cinfo->pseudo_palette[region->color] : region->color;
 
        if (info->state != FBINFO_STATE_RUNNING)
                return;
@@ -2058,49 +1748,30 @@ static void cirrusfb_fillrect (struct fb_info *info, const struct fb_fillrect *r
 
        memcpy(&modded, region, sizeof(struct fb_fillrect));
 
-       if(!modded.width || !modded.height ||
+       if (!modded.width || !modded.height ||
           modded.dx >= vxres || modded.dy >= vyres)
                return;
 
-       if(modded.dx + modded.width  > vxres) modded.width  = vxres - modded.dx;
-       if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
-
-       cirrusfb_prim_fillrect(cinfo, &modded);
+       if (modded.dx + modded.width  > vxres)
+               modded.width  = vxres - modded.dx;
+       if (modded.dy + modded.height > vyres)
+               modded.height = vyres - modded.dy;
+
+       cirrusfb_RectFill(cinfo->regbase,
+                         info->var.bits_per_pixel,
+                         (region->dx * m) / 8, region->dy,
+                         (region->width * m) / 8, region->height,
+                         color, color,
+                         info->fix.line_length, 0x40);
 }
 
-static void cirrusfb_prim_copyarea(struct cirrusfb_info *cinfo,
-                                  const struct fb_copyarea *area)
+static void cirrusfb_copyarea(struct fb_info *info,
+                             const struct fb_copyarea *area)
 {
-       int m; /* bytes per pixel */
-       if(cinfo->info->var.bits_per_pixel == 1) {
-               cirrusfb_BitBLT(cinfo->regbase, cinfo->info->var.bits_per_pixel,
-                               area->sx / 8, area->sy,
-                               area->dx / 8, area->dy,
-                               area->width / 8, area->height,
-                               cinfo->currentmode.line_length);
-       } else {
-               m = ( cinfo->info->var.bits_per_pixel + 7 ) / 8;
-               cirrusfb_BitBLT(cinfo->regbase, cinfo->info->var.bits_per_pixel,
-                               area->sx * m, area->sy,
-                               area->dx * m, area->dy,
-                               area->width * m, area->height,
-                               cinfo->currentmode.line_length);
-       }
-       return;
-}
-
-
-static void cirrusfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
-{
-       struct cirrusfb_info *cinfo = info->par;
        struct fb_copyarea modded;
        u32 vxres, vyres;
-       modded.sx = area->sx;
-       modded.sy = area->sy;
-       modded.dx = area->dx;
-       modded.dy = area->dy;
-       modded.width  = area->width;
-       modded.height = area->height;
+       struct cirrusfb_info *cinfo = info->par;
+       int m = info->var.bits_per_pixel;
 
        if (info->state != FBINFO_STATE_RUNNING)
                return;
@@ -2111,90 +1782,140 @@ static void cirrusfb_copyarea(struct fb_info *info, const struct fb_copyarea *ar
 
        vxres = info->var.xres_virtual;
        vyres = info->var.yres_virtual;
+       memcpy(&modded, area, sizeof(struct fb_copyarea));
 
-       if(!modded.width || !modded.height ||
+       if (!modded.width || !modded.height ||
           modded.sx >= vxres || modded.sy >= vyres ||
           modded.dx >= vxres || modded.dy >= vyres)
                return;
 
-       if(modded.sx + modded.width > vxres)  modded.width = vxres - modded.sx;
-       if(modded.dx + modded.width > vxres)  modded.width = vxres - modded.dx;
-       if(modded.sy + modded.height > vyres) modded.height = vyres - modded.sy;
-       if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
+       if (modded.sx + modded.width > vxres)
+               modded.width = vxres - modded.sx;
+       if (modded.dx + modded.width > vxres)
+               modded.width = vxres - modded.dx;
+       if (modded.sy + modded.height > vyres)
+               modded.height = vyres - modded.sy;
+       if (modded.dy + modded.height > vyres)
+               modded.height = vyres - modded.dy;
+
+       cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel,
+                       (area->sx * m) / 8, area->sy,
+                       (area->dx * m) / 8, area->dy,
+                       (area->width * m) / 8, area->height,
+                       info->fix.line_length);
 
-       cirrusfb_prim_copyarea(cinfo, &modded);
 }
 
-static void cirrusfb_imageblit(struct fb_info *info, const struct fb_image *image)
+static void cirrusfb_imageblit(struct fb_info *info,
+                              const struct fb_image *image)
 {
        struct cirrusfb_info *cinfo = info->par;
+       unsigned char op = (info->var.bits_per_pixel == 24) ? 0xc : 0x4;
 
-        cirrusfb_WaitBLT(cinfo->regbase);
-       cfb_imageblit(info, image);
-}
+       if (info->state != FBINFO_STATE_RUNNING)
+               return;
+       /* Alpine/SD64 does not work at 24bpp ??? */
+       if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1)
+               cfb_imageblit(info, image);
+       else if ((cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) &&
+                 op == 0xc)
+               cfb_imageblit(info, image);
+       else {
+               unsigned size = ((image->width + 7) >> 3) * image->height;
+               int m = info->var.bits_per_pixel;
+               u32 fg, bg;
 
+               if (info->var.bits_per_pixel == 8) {
+                       fg = image->fg_color;
+                       bg = image->bg_color;
+               } else {
+                       fg = ((u32 *)(info->pseudo_palette))[image->fg_color];
+                       bg = ((u32 *)(info->pseudo_palette))[image->bg_color];
+               }
+               if (info->var.bits_per_pixel == 24) {
+                       /* clear background first */
+                       cirrusfb_RectFill(cinfo->regbase,
+                                         info->var.bits_per_pixel,
+                                         (image->dx * m) / 8, image->dy,
+                                         (image->width * m) / 8,
+                                         image->height,
+                                         bg, bg,
+                                         info->fix.line_length, 0x40);
+               }
+               cirrusfb_RectFill(cinfo->regbase,
+                                 info->var.bits_per_pixel,
+                                 (image->dx * m) / 8, image->dy,
+                                 (image->width * m) / 8, image->height,
+                                 fg, bg,
+                                 info->fix.line_length, op);
+               memcpy(info->screen_base, image->data, size);
+       }
+}
 
 #ifdef CONFIG_PPC_PREP
 #define PREP_VIDEO_BASE ((volatile unsigned long) 0xC0000000)
 #define PREP_IO_BASE    ((volatile unsigned char *) 0x80000000)
-static void get_prep_addrs (unsigned long *display, unsigned long *registers)
+static void get_prep_addrs(unsigned long *display, unsigned long *registers)
 {
-       DPRINTK ("ENTER\n");
-
        *display = PREP_VIDEO_BASE;
        *registers = (unsigned long) PREP_IO_BASE;
-
-       DPRINTK ("EXIT\n");
 }
 
 #endif                         /* CONFIG_PPC_PREP */
 
-
 #ifdef CONFIG_PCI
-static int release_io_ports = 0;
+static int release_io_ports;
 
 /* Pulled the logic from XFree86 Cirrus driver to get the memory size,
  * based on the DRAM bandwidth bit and DRAM bank switching bit.  This
  * works with 1MB, 2MB and 4MB configurations (which the Motorola boards
  * seem to have. */
-static unsigned int cirrusfb_get_memsize (u8 __iomem *regbase)
+static unsigned int __devinit cirrusfb_get_memsize(struct fb_info *info,
+                                                  u8 __iomem *regbase)
 {
        unsigned long mem;
-       unsigned char SRF;
+       struct cirrusfb_info *cinfo = info->par;
 
-       DPRINTK ("ENTER\n");
+       if (is_laguna(cinfo)) {
+               unsigned char SR14 = vga_rseq(regbase, CL_SEQR14);
 
-       SRF = vga_rseq (regbase, CL_SEQRF);
-       switch ((SRF & 0x18)) {
-           case 0x08: mem = 512 * 1024; break;
-           case 0x10: mem = 1024 * 1024; break;
-               /* 64-bit DRAM data bus width; assume 2MB. Also indicates 2MB memory
-                  * on the 5430. */
-           case 0x18: mem = 2048 * 1024; break;
-           default: printk ("CLgenfb: Unknown memory size!\n");
-               mem = 1024 * 1024;
-       }
-       if (SRF & 0x80) {
-               /* If DRAM bank switching is enabled, there must be twice as much
-                  * memory installed. (4MB on the 5434) */
-               mem *= 2;
+               mem = ((SR14 & 7) + 1) << 20;
+       } else {
+               unsigned char SRF = vga_rseq(regbase, CL_SEQRF);
+               switch ((SRF & 0x18)) {
+               case 0x08:
+                       mem = 512 * 1024;
+                       break;
+               case 0x10:
+                       mem = 1024 * 1024;
+                       break;
+               /* 64-bit DRAM data bus width; assume 2MB.
+                * Also indicates 2MB memory on the 5430.
+                */
+               case 0x18:
+                       mem = 2048 * 1024;
+                       break;
+               default:
+                       dev_warn(info->device, "Unknown memory size!\n");
+                       mem = 1024 * 1024;
+               }
+               /* If DRAM bank switching is enabled, there must be
+                * twice as much memory installed. (4MB on the 5434)
+                */
+               if (cinfo->btype != BT_ALPINE && (SRF & 0x80) != 0)
+                       mem *= 2;
        }
-       /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
 
-       DPRINTK ("EXIT\n");
+       /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
        return mem;
 }
 
-
-
-static void get_pci_addrs (const struct pci_dev *pdev,
-                          unsigned long *display, unsigned long *registers)
+static void get_pci_addrs(const struct pci_dev *pdev,
+                         unsigned long *display, unsigned long *registers)
 {
-       assert (pdev != NULL);
-       assert (display != NULL);
-       assert (registers != NULL);
-
-       DPRINTK ("ENTER\n");
+       assert(pdev != NULL);
+       assert(display != NULL);
+       assert(registers != NULL);
 
        *display = 0;
        *registers = 0;
@@ -2209,65 +1930,85 @@ static void get_pci_addrs (const struct pci_dev *pdev,
                *registers = pci_resource_start(pdev, 1);
        }
 
-       assert (*display != 0);
-
-       DPRINTK ("EXIT\n");
+       assert(*display != 0);
 }
 
-
-static void cirrusfb_pci_unmap (struct cirrusfb_info *cinfo)
+static void cirrusfb_pci_unmap(struct fb_info *info)
 {
-       struct pci_dev *pdev = cinfo->pdev;
+       struct pci_dev *pdev = to_pci_dev(info->device);
+       struct cirrusfb_info *cinfo = info->par;
 
-       iounmap(cinfo->fbmem);
+       if (cinfo->laguna_mmio == NULL)
+               iounmap(cinfo->laguna_mmio);
+       iounmap(info->screen_base);
 #if 0 /* if system didn't claim this region, we would... */
        release_mem_region(0xA0000, 65535);
 #endif
        if (release_io_ports)
                release_region(0x3C0, 32);
        pci_release_regions(pdev);
-       framebuffer_release(cinfo->info);
 }
 #endif /* CONFIG_PCI */
 
-
 #ifdef CONFIG_ZORRO
-static void __devexit cirrusfb_zorro_unmap (struct cirrusfb_info *cinfo)
+static void cirrusfb_zorro_unmap(struct fb_info *info)
 {
-       zorro_release_device(cinfo->zdev);
+       struct cirrusfb_info *cinfo = info->par;
+       struct zorro_dev *zdev = to_zorro_dev(info->device);
+
+       zorro_release_device(zdev);
 
        if (cinfo->btype == BT_PICASSO4) {
                cinfo->regbase -= 0x600000;
-               iounmap ((void *)cinfo->regbase);
-               iounmap ((void *)cinfo->fbmem);
+               iounmap((void *)cinfo->regbase);
+               iounmap(info->screen_base);
        } else {
-               if (zorro_resource_start(cinfo->zdev) > 0x01000000)
-                       iounmap ((void *)cinfo->fbmem);
+               if (zorro_resource_start(zdev) > 0x01000000)
+                       iounmap(info->screen_base);
        }
-       framebuffer_release(cinfo->info);
 }
 #endif /* CONFIG_ZORRO */
 
-static int cirrusfb_set_fbinfo(struct cirrusfb_info *cinfo)
+/* function table of the above functions */
+static struct fb_ops cirrusfb_ops = {
+       .owner          = THIS_MODULE,
+       .fb_open        = cirrusfb_open,
+       .fb_release     = cirrusfb_release,
+       .fb_setcolreg   = cirrusfb_setcolreg,
+       .fb_check_var   = cirrusfb_check_var,
+       .fb_set_par     = cirrusfb_set_par,
+       .fb_pan_display = cirrusfb_pan_display,
+       .fb_blank       = cirrusfb_blank,
+       .fb_fillrect    = cirrusfb_fillrect,
+       .fb_copyarea    = cirrusfb_copyarea,
+       .fb_sync        = cirrusfb_sync,
+       .fb_imageblit   = cirrusfb_imageblit,
+};
+
+static int __devinit cirrusfb_set_fbinfo(struct fb_info *info)
 {
-       struct fb_info *info = cinfo->info;
+       struct cirrusfb_info *cinfo = info->par;
        struct fb_var_screeninfo *var = &info->var;
 
-       info->par = cinfo;
        info->pseudo_palette = cinfo->pseudo_palette;
        info->flags = FBINFO_DEFAULT
                    | FBINFO_HWACCEL_XPAN
                    | FBINFO_HWACCEL_YPAN
                    | FBINFO_HWACCEL_FILLRECT
+                   | FBINFO_HWACCEL_IMAGEBLIT
                    | FBINFO_HWACCEL_COPYAREA;
-       if (noaccel)
+       if (noaccel || is_laguna(cinfo)) {
                info->flags |= FBINFO_HWACCEL_DISABLED;
+               info->fix.accel = FB_ACCEL_NONE;
+       } else
+               info->fix.accel = FB_ACCEL_CIRRUS_ALPINE;
+
        info->fbops = &cirrusfb_ops;
-       info->screen_base = cinfo->fbmem;
+
        if (cinfo->btype == BT_GD5480) {
                if (var->bits_per_pixel == 16)
                        info->screen_base += 1 * MB_;
-               if (var->bits_per_pixel == 24 || var->bits_per_pixel == 32)
+               if (var->bits_per_pixel == 32)
                        info->screen_base += 2 * MB_;
        }
 
@@ -2277,98 +2018,84 @@ static int cirrusfb_set_fbinfo(struct cirrusfb_info *cinfo)
 
        /* monochrome: only 1 memory plane */
        /* 8 bit and above: Use whole memory area */
-       info->fix.smem_start = cinfo->fbmem_phys;
-       info->fix.smem_len   = (var->bits_per_pixel == 1) ? cinfo->size / 4 : cinfo->size;
-       info->fix.type       = cinfo->currentmode.type;
+       info->fix.smem_len   = info->screen_size;
+       if (var->bits_per_pixel == 1)
+               info->fix.smem_len /= 4;
        info->fix.type_aux   = 0;
-       info->fix.visual     = cinfo->currentmode.visual;
        info->fix.xpanstep   = 1;
        info->fix.ypanstep   = 1;
        info->fix.ywrapstep  = 0;
-       info->fix.line_length = cinfo->currentmode.line_length;
 
        /* FIXME: map region at 0xB8000 if available, fill in here */
-       info->fix.mmio_start = cinfo->fbregs_phys;
        info->fix.mmio_len   = 0;
-       info->fix.accel = FB_ACCEL_NONE;
 
        fb_alloc_cmap(&info->cmap, 256, 0);
 
        return 0;
 }
 
-static int cirrusfb_register(struct cirrusfb_info *cinfo)
+static int __devinit cirrusfb_register(struct fb_info *info)
 {
-       struct fb_info *info;
+       struct cirrusfb_info *cinfo = info->par;
        int err;
-       cirrusfb_board_t btype;
 
-       DPRINTK ("ENTER\n");
+       /* sanity checks */
+       assert(cinfo->btype != BT_NONE);
 
-       printk (KERN_INFO "cirrusfb: Driver for Cirrus Logic based graphic boards, v" CIRRUSFB_VERSION "\n");
+       /* set all the vital stuff */
+       cirrusfb_set_fbinfo(info);
 
-       info = cinfo->info;
-       btype = cinfo->btype;
+       dev_dbg(info->device, "(RAM start set to: 0x%p)\n", info->screen_base);
 
-       /* sanity checks */
-       assert (btype != BT_NONE);
-
-       DPRINTK ("cirrusfb: (RAM start set to: 0x%p)\n", cinfo->fbmem);
+       err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
+       if (!err) {
+               dev_dbg(info->device, "wrong initial video mode\n");
+               err = -EINVAL;
+               goto err_dealloc_cmap;
+       }
 
-       /* Make pretend we've set the var so our structures are in a "good" */
-       /* state, even though we haven't written the mode to the hw yet...  */
-       info->var = cirrusfb_predefined[cirrusfb_def_mode].var;
        info->var.activate = FB_ACTIVATE_NOW;
 
-       err = cirrusfb_decode_var(&info->var, &cinfo->currentmode, info);
+       err = cirrusfb_check_var(&info->var, info);
        if (err < 0) {
                /* should never happen */
-               DPRINTK("choking on default var... umm, no good.\n");
-               goto err_unmap_cirrusfb;
+               dev_dbg(info->device,
+                       "choking on default var... umm, no good.\n");
+               goto err_dealloc_cmap;
        }
 
-       /* set all the vital stuff */
-       cirrusfb_set_fbinfo(cinfo);
-
        err = register_framebuffer(info);
        if (err < 0) {
-               printk (KERN_ERR "cirrusfb: could not register fb device; err = %d!\n", err);
+               dev_err(info->device,
+                       "could not register fb device; err = %d!\n", err);
                goto err_dealloc_cmap;
        }
 
-       DPRINTK ("EXIT, returning 0\n");
        return 0;
 
 err_dealloc_cmap:
        fb_dealloc_cmap(&info->cmap);
-err_unmap_cirrusfb:
-       cinfo->unmap(cinfo);
        return err;
 }
 
-static void __devexit cirrusfb_cleanup (struct fb_info *info)
+static void __devexit cirrusfb_cleanup(struct fb_info *info)
 {
        struct cirrusfb_info *cinfo = info->par;
-       DPRINTK ("ENTER\n");
-
-       switch_monitor (cinfo, 0);
 
-       unregister_framebuffer (info);
-       fb_dealloc_cmap (&info->cmap);
-       printk ("Framebuffer unregistered\n");
-       cinfo->unmap(cinfo);
-
-       DPRINTK ("EXIT\n");
+       switch_monitor(cinfo, 0);
+       unregister_framebuffer(info);
+       fb_dealloc_cmap(&info->cmap);
+       dev_dbg(info->device, "Framebuffer unregistered\n");
+       cinfo->unmap(info);
+       framebuffer_release(info);
 }
 
-
 #ifdef CONFIG_PCI
-static int cirrusfb_pci_register (struct pci_dev *pdev,
-                                 const struct pci_device_id *ent)
+static int __devinit cirrusfb_pci_register(struct pci_dev *pdev,
+                                          const struct pci_device_id *ent)
 {
        struct cirrusfb_info *cinfo;
        struct fb_info *info;
-       cirrusfb_board_t btype;
        unsigned long board_addr, board_size;
        int ret;
 
@@ -2382,47 +2109,50 @@ static int cirrusfb_pci_register (struct pci_dev *pdev,
        if (!info) {
                printk(KERN_ERR "cirrusfb: could not allocate memory\n");
                ret = -ENOMEM;
-               goto err_disable;
+               goto err_out;
        }
 
        cinfo = info->par;
-       cinfo->info = info;
-       cinfo->pdev = pdev;
-       cinfo->btype = btype = (cirrusfb_board_t) ent->driver_data;
+       cinfo->btype = (enum cirrus_board) ent->driver_data;
 
-       DPRINTK (" Found PCI device, base address 0 is 0x%lx, btype set to %d\n",
-               pdev->resource[0].start, btype);
-       DPRINTK (" base address 1 is 0x%lx\n", pdev->resource[1].start);
+       dev_dbg(info->device,
+               " Found PCI device, base address 0 is 0x%Lx, btype set to %d\n",
+               (unsigned long long)pdev->resource[0].start,  cinfo->btype);
+       dev_dbg(info->device, " base address 1 is 0x%Lx\n",
+               (unsigned long long)pdev->resource[1].start);
 
-       if(isPReP) {
-               pci_write_config_dword (pdev, PCI_BASE_ADDRESS_0, 0x00000000);
+       if (isPReP) {
+               pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, 0x00000000);
 #ifdef CONFIG_PPC_PREP
-               get_prep_addrs (&board_addr, &cinfo->fbregs_phys);
+               get_prep_addrs(&board_addr, &info->fix.mmio_start);
 #endif
-               /* PReP dies if we ioremap the IO registers, but it works w/out... */
-               cinfo->regbase = (char __iomem *) cinfo->fbregs_phys;
+       /* PReP dies if we ioremap the IO registers, but it works w/out... */
+               cinfo->regbase = (char __iomem *) info->fix.mmio_start;
        } else {
-               DPRINTK ("Attempt to get PCI info for Cirrus Graphics Card\n");
-               get_pci_addrs (pdev, &board_addr, &cinfo->fbregs_phys);
-               cinfo->regbase = NULL;          /* FIXME: this forces VGA.  alternatives? */
+               dev_dbg(info->device,
+                       "Attempt to get PCI info for Cirrus Graphics Card\n");
+               get_pci_addrs(pdev, &board_addr, &info->fix.mmio_start);
+               /* FIXME: this forces VGA.  alternatives? */
+               cinfo->regbase = NULL;
+               cinfo->laguna_mmio = ioremap(info->fix.mmio_start, 0x1000);
        }
 
-       DPRINTK ("Board address: 0x%lx, register address: 0x%lx\n", board_addr, cinfo->fbregs_phys);
+       dev_dbg(info->device, "Board address: 0x%lx, register address: 0x%lx\n",
+               board_addr, info->fix.mmio_start);
 
-       board_size = (btype == BT_GD5480) ?
-               32 * MB_ : cirrusfb_get_memsize (cinfo->regbase);
+       board_size = (cinfo->btype == BT_GD5480) ?
+               32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase);
 
        ret = pci_request_regions(pdev, "cirrusfb");
-       if (ret <0) {
-               printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, abort\n",
-                      board_addr);
+       if (ret < 0) {
+               dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
+                       board_addr);
                goto err_release_fb;
        }
 #if 0 /* if the system didn't claim this region, we would... */
        if (!request_mem_region(0xA0000, 65535, "cirrusfb")) {
-               printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, abort\n"
-,
-                      0xA0000L);
+               dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
+                       0xA0000L);
                ret = -EBUSY;
                goto err_release_regions;
        }
@@ -2430,22 +2160,27 @@ static int cirrusfb_pci_register (struct pci_dev *pdev,
        if (request_region(0x3C0, 32, "cirrusfb"))
                release_io_ports = 1;
 
-       cinfo->fbmem = ioremap(board_addr, board_size);
-       if (!cinfo->fbmem) {
+       info->screen_base = ioremap(board_addr, board_size);
+       if (!info->screen_base) {
                ret = -EIO;
                goto err_release_legacy;
        }
 
-       cinfo->fbmem_phys = board_addr;
-       cinfo->size = board_size;
+       info->fix.smem_start = board_addr;
+       info->screen_size = board_size;
        cinfo->unmap = cirrusfb_pci_unmap;
 
-       printk (" RAM (%lu kB) at 0xx%lx, ", cinfo->size / KB_, board_addr);
-       printk ("Cirrus Logic chipset on PCI bus\n");
+       dev_info(info->device,
+                "Cirrus Logic chipset on PCI bus, RAM (%lu kB) at 0x%lx\n",
+                info->screen_size >> 10, board_addr);
        pci_set_drvdata(pdev, info);
 
-       return cirrusfb_register(cinfo);
+       ret = cirrusfb_register(info);
+       if (!ret)
+               return 0;
 
+       pci_set_drvdata(pdev, NULL);
+       iounmap(info->screen_base);
 err_release_legacy:
        if (release_io_ports)
                release_region(0x3C0, 32);
@@ -2455,20 +2190,18 @@ err_release_regions:
 #endif
        pci_release_regions(pdev);
 err_release_fb:
+       if (cinfo->laguna_mmio != NULL)
+               iounmap(cinfo->laguna_mmio);
        framebuffer_release(info);
-err_disable:
 err_out:
        return ret;
 }
 
-static void __devexit cirrusfb_pci_unregister (struct pci_dev *pdev)
+static void __devexit cirrusfb_pci_unregister(struct pci_dev *pdev)
 {
        struct fb_info *info = pci_get_drvdata(pdev);
-       DPRINTK ("ENTER\n");
 
-       cirrusfb_cleanup (info);
-
-       DPRINTK ("EXIT\n");
+       cirrusfb_cleanup(info);
 }
 
 static struct pci_driver cirrusfb_pci_driver = {
@@ -2485,14 +2218,13 @@ static struct pci_driver cirrusfb_pci_driver = {
 };
 #endif /* CONFIG_PCI */
 
-
 #ifdef CONFIG_ZORRO
-static int cirrusfb_zorro_register(struct zorro_dev *z,
-                                  const struct zorro_device_id *ent)
+static int __devinit cirrusfb_zorro_register(struct zorro_dev *z,
+                                            const struct zorro_device_id *ent)
 {
        struct cirrusfb_info *cinfo;
        struct fb_info *info;
-       cirrusfb_board_t btype;
+       enum cirrus_board btype;
        struct zorro_dev *z2 = NULL;
        unsigned long board_addr, board_size, size;
        int ret;
@@ -2501,86 +2233,98 @@ static int cirrusfb_zorro_register(struct zorro_dev *z,
        if (cirrusfb_zorro_table2[btype].id2)
                z2 = zorro_find_device(cirrusfb_zorro_table2[btype].id2, NULL);
        size = cirrusfb_zorro_table2[btype].size;
-       printk(KERN_INFO "cirrusfb: %s board detected; ",
-              cirrusfb_board_info[btype].name);
 
        info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
        if (!info) {
-               printk (KERN_ERR "cirrusfb: could not allocate memory\n");
+               printk(KERN_ERR "cirrusfb: could not allocate memory\n");
                ret = -ENOMEM;
                goto err_out;
        }
 
+       dev_info(info->device, "%s board detected\n",
+                cirrusfb_board_info[btype].name);
+
        cinfo = info->par;
-       cinfo->info = info;
        cinfo->btype = btype;
 
-       assert (z > 0);
-       assert (z2 >= 0);
-       assert (btype != BT_NONE);
+       assert(z);
+       assert(btype != BT_NONE);
 
-       cinfo->zdev = z;
        board_addr = zorro_resource_start(z);
        board_size = zorro_resource_len(z);
-       cinfo->size = size;
+       info->screen_size = size;
 
        if (!zorro_request_device(z, "cirrusfb")) {
-               printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, abort\n",
-                      board_addr);
+               dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
+                       board_addr);
                ret = -EBUSY;
                goto err_release_fb;
        }
 
-       printk (" RAM (%lu MB) at $%lx, ", board_size / MB_, board_addr);
-
        ret = -EIO;
 
        if (btype == BT_PICASSO4) {
-               printk (" REG at $%lx\n", board_addr + 0x600000);
+               dev_info(info->device, " REG at $%lx\n", board_addr + 0x600000);
 
                /* To be precise, for the P4 this is not the */
                /* begin of the board, but the begin of RAM. */
                /* for P4, map in its address space in 2 chunks (### TEST! ) */
                /* (note the ugly hardcoded 16M number) */
-               cinfo->regbase = ioremap (board_addr, 16777216);
+               cinfo->regbase = ioremap(board_addr, 16777216);
                if (!cinfo->regbase)
                        goto err_release_region;
 
-               DPRINTK ("cirrusfb: Virtual address for board set to: $%p\n", cinfo->regbase);
+               dev_dbg(info->device, "Virtual address for board set to: $%p\n",
+                       cinfo->regbase);
                cinfo->regbase += 0x600000;
-               cinfo->fbregs_phys = board_addr + 0x600000;
+               info->fix.mmio_start = board_addr + 0x600000;
 
-               cinfo->fbmem_phys = board_addr + 16777216;
-               cinfo->fbmem = ioremap (cinfo->fbmem_phys, 16777216);
-               if (!cinfo->fbmem)
+               info->fix.smem_start = board_addr + 16777216;
+               info->screen_base = ioremap(info->fix.smem_start, 16777216);
+               if (!info->screen_base)
                        goto err_unmap_regbase;
        } else {
-               printk (" REG at $%lx\n", (unsigned long) z2->resource.start);
+               dev_info(info->device, " REG at $%lx\n",
+                        (unsigned long) z2->resource.start);
 
-               cinfo->fbmem_phys = board_addr;
+               info->fix.smem_start = board_addr;
                if (board_addr > 0x01000000)
-                       cinfo->fbmem = ioremap (board_addr, board_size);
+                       info->screen_base = ioremap(board_addr, board_size);
                else
-                       cinfo->fbmem = (caddr_t) ZTWO_VADDR (board_addr);
-               if (!cinfo->fbmem)
+                       info->screen_base = (caddr_t) ZTWO_VADDR(board_addr);
+               if (!info->screen_base)
                        goto err_release_region;
 
                /* set address for REG area of board */
-               cinfo->regbase = (caddr_t) ZTWO_VADDR (z2->resource.start);
-               cinfo->fbregs_phys = z2->resource.start;
+               cinfo->regbase = (caddr_t) ZTWO_VADDR(z2->resource.start);
+               info->fix.mmio_start = z2->resource.start;
 
-               DPRINTK ("cirrusfb: Virtual address for board set to: $%p\n", cinfo->regbase);
+               dev_dbg(info->device, "Virtual address for board set to: $%p\n",
+                       cinfo->regbase);
        }
        cinfo->unmap = cirrusfb_zorro_unmap;
 
-       printk (KERN_INFO "Cirrus Logic chipset on Zorro bus\n");
+       dev_info(info->device,
+                "Cirrus Logic chipset on Zorro bus, RAM (%lu MB) at $%lx\n",
+                board_size / MB_, board_addr);
+
        zorro_set_drvdata(z, info);
 
-       return cirrusfb_register(cinfo);
+       /* MCLK select etc. */
+       if (cirrusfb_board_info[btype].init_sr1f)
+               vga_wseq(cinfo->regbase, CL_SEQR1F,
+                        cirrusfb_board_info[btype].sr1f);
+
+       ret = cirrusfb_register(info);
+       if (!ret)
+               return 0;
+
+       if (btype == BT_PICASSO4 || board_addr > 0x01000000)
+               iounmap(info->screen_base);
 
 err_unmap_regbase:
-       /* Parental advisory: explicit hack */
-       iounmap(cinfo->regbase - 0x600000);
+       if (btype == BT_PICASSO4)
+               iounmap(cinfo->regbase - 0x600000);
 err_release_region:
        release_region(board_addr, board_size);
 err_release_fb:
@@ -2592,11 +2336,8 @@ err_out:
 void __devexit cirrusfb_zorro_unregister(struct zorro_dev *z)
 {
        struct fb_info *info = zorro_get_drvdata(z);
-       DPRINTK ("ENTER\n");
-
-       cirrusfb_cleanup (info);
 
-       DPRINTK ("EXIT\n");
+       cirrusfb_cleanup(info);
 }
 
 static struct zorro_driver cirrusfb_zorro_driver = {
@@ -2607,57 +2348,29 @@ static struct zorro_driver cirrusfb_zorro_driver = {
 };
 #endif /* CONFIG_ZORRO */
 
-static int __init cirrusfb_init(void)
-{
-       int error = 0;
-
 #ifndef MODULE
-       char *option = NULL;
-
-       if (fb_get_options("cirrusfb", &option))
-               return -ENODEV;
-       cirrusfb_setup(option);
-#endif
-
-#ifdef CONFIG_ZORRO
-       error |= zorro_register_driver(&cirrusfb_zorro_driver);
-#endif
-#ifdef CONFIG_PCI
-       error |= pci_register_driver(&cirrusfb_pci_driver);
-#endif
-       return error;
-}
-
-
-
-#ifndef MODULE
-static int __init cirrusfb_setup(char *options) {
-       char *this_opt, s[32];
-       int i;
-
-       DPRINTK ("ENTER\n");
+static int __init cirrusfb_setup(char *options)
+{
+       char *this_opt;
 
        if (!options || !*options)
                return 0;
 
-       while ((this_opt = strsep (&options, ",")) != NULL) {   
-               if (!*this_opt) continue;
-
-               DPRINTK("cirrusfb_setup: option '%s'\n", this_opt);
+       while ((this_opt = strsep(&options, ",")) != NULL) {
+               if (!*this_opt)
+                       continue;
 
-               for (i = 0; i < NUM_TOTAL_MODES; i++) {
-                       sprintf (s, "mode:%s", cirrusfb_predefined[i].name);
-                       if (strcmp (this_opt, s) == 0)
-                               cirrusfb_def_mode = i;
-               }
                if (!strcmp(this_opt, "noaccel"))
                        noaccel = 1;
+               else if (!strncmp(this_opt, "mode:", 5))
+                       mode_option = this_opt + 5;
+               else
+                       mode_option = this_opt;
        }
        return 0;
 }
 #endif
 
-
     /*
      *  Modularization
      */
@@ -2666,7 +2379,28 @@ MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>");
 MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
 MODULE_LICENSE("GPL");
 
-static void __exit cirrusfb_exit (void)
+static int __init cirrusfb_init(void)
+{
+       int error = 0;
+
+#ifndef MODULE
+       char *option = NULL;
+
+       if (fb_get_options("cirrusfb", &option))
+               return -ENODEV;
+       cirrusfb_setup(option);
+#endif
+
+#ifdef CONFIG_ZORRO
+       error |= zorro_register_driver(&cirrusfb_zorro_driver);
+#endif
+#ifdef CONFIG_PCI
+       error |= pci_register_driver(&cirrusfb_pci_driver);
+#endif
+       return error;
+}
+
+static void __exit cirrusfb_exit(void)
 {
 #ifdef CONFIG_PCI
        pci_unregister_driver(&cirrusfb_pci_driver);
@@ -2678,70 +2412,72 @@ static void __exit cirrusfb_exit (void)
 
 module_init(cirrusfb_init);
 
+module_param(mode_option, charp, 0);
+MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
+module_param(noaccel, bool, 0);
+MODULE_PARM_DESC(noaccel, "Disable acceleration");
+
 #ifdef MODULE
 module_exit(cirrusfb_exit);
 #endif
 
-
 /**********************************************************************/
 /* about the following functions - I have used the same names for the */
 /* functions as Markus Wild did in his Retina driver for NetBSD as    */
 /* they just made sense for this purpose. Apart from that, I wrote    */
-/* these functions myself.                                            */
+/* these functions myself.                                         */
 /**********************************************************************/
 
 /*** WGen() - write into one of the external/general registers ***/
-static void WGen (const struct cirrusfb_info *cinfo,
+static void WGen(const struct cirrusfb_info *cinfo,
                  int regnum, unsigned char val)
 {
        unsigned long regofs = 0;
 
        if (cinfo->btype == BT_PICASSO) {
                /* Picasso II specific hack */
-/*              if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D || regnum == CL_VSSM2) */
+/*           if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
+                 regnum == CL_VSSM2) */
                if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
                        regofs = 0xfff;
        }
 
-       vga_w (cinfo->regbase, regofs + regnum, val);
+       vga_w(cinfo->regbase, regofs + regnum, val);
 }
 
 /*** RGen() - read out one of the external/general registers ***/
-static unsigned char RGen (const struct cirrusfb_info *cinfo, int regnum)
+static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
 {
        unsigned long regofs = 0;
 
        if (cinfo->btype == BT_PICASSO) {
                /* Picasso II specific hack */
-/*              if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D || regnum == CL_VSSM2) */
+/*           if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
+                 regnum == CL_VSSM2) */
                if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
                        regofs = 0xfff;
        }
 
-       return vga_r (cinfo->regbase, regofs + regnum);
+       return vga_r(cinfo->regbase, regofs + regnum);
 }
 
 /*** AttrOn() - turn on VideoEnable for Attribute controller ***/
-static void AttrOn (const struct cirrusfb_info *cinfo)
+static void AttrOn(const struct cirrusfb_info *cinfo)
 {
-       assert (cinfo != NULL);
+       assert(cinfo != NULL);
 
-       DPRINTK ("ENTER\n");
-
-       if (vga_rcrt (cinfo->regbase, CL_CRT24) & 0x80) {
+       if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
                /* if we're just in "write value" mode, write back the */
                /* same value as before to not modify anything */
-               vga_w (cinfo->regbase, VGA_ATT_IW,
-                      vga_r (cinfo->regbase, VGA_ATT_R));
+               vga_w(cinfo->regbase, VGA_ATT_IW,
+                     vga_r(cinfo->regbase, VGA_ATT_R));
        }
        /* turn on video bit */
-/*      vga_w (cinfo->regbase, VGA_ATT_IW, 0x20); */
-       vga_w (cinfo->regbase, VGA_ATT_IW, 0x33);
+/*      vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
+       vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
 
        /* dummy write on Reg0 to be on "write index" mode next time */
-       vga_w (cinfo->regbase, VGA_ATT_IW, 0x00);
-
-       DPRINTK ("EXIT\n");
+       vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
 }
 
 /*** WHDR() - write into the Hidden DAC register ***/
@@ -2750,119 +2486,118 @@ static void AttrOn (const struct cirrusfb_info *cinfo)
  * registers of their functional group) here is a specialized routine for
  * accessing the HDR
  */
-static void WHDR (const struct cirrusfb_info *cinfo, unsigned char val)
+static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
 {
        unsigned char dummy;
 
+       if (is_laguna(cinfo))
+               return;
        if (cinfo->btype == BT_PICASSO) {
                /* Klaus' hint for correct access to HDR on some boards */
                /* first write 0 to pixel mask (3c6) */
-               WGen (cinfo, VGA_PEL_MSK, 0x00);
-               udelay (200);
+               WGen(cinfo, VGA_PEL_MSK, 0x00);
+               udelay(200);
                /* next read dummy from pixel address (3c8) */
-               dummy = RGen (cinfo, VGA_PEL_IW);
-               udelay (200);
+               dummy = RGen(cinfo, VGA_PEL_IW);
+               udelay(200);
        }
        /* now do the usual stuff to access the HDR */
 
-       dummy = RGen (cinfo, VGA_PEL_MSK);
-       udelay (200);
-       dummy = RGen (cinfo, VGA_PEL_MSK);
-       udelay (200);
-       dummy = RGen (cinfo, VGA_PEL_MSK);
-       udelay (200);
-       dummy = RGen (cinfo, VGA_PEL_MSK);
-       udelay (200);
+       dummy = RGen(cinfo, VGA_PEL_MSK);
+       udelay(200);
+       dummy = RGen(cinfo, VGA_PEL_MSK);
+       udelay(200);
+       dummy = RGen(cinfo, VGA_PEL_MSK);
+       udelay(200);
+       dummy = RGen(cinfo, VGA_PEL_MSK);
+       udelay(200);
 
-       WGen (cinfo, VGA_PEL_MSK, val);
-       udelay (200);
+       WGen(cinfo, VGA_PEL_MSK, val);
+       udelay(200);
 
        if (cinfo->btype == BT_PICASSO) {
                /* now first reset HDR access counter */
-               dummy = RGen (cinfo, VGA_PEL_IW);
-               udelay (200);
+               dummy = RGen(cinfo, VGA_PEL_IW);
+               udelay(200);
 
                /* and at the end, restore the mask value */
                /* ## is this mask always 0xff? */
-               WGen (cinfo, VGA_PEL_MSK, 0xff);
-               udelay (200);
+               WGen(cinfo, VGA_PEL_MSK, 0xff);
+               udelay(200);
        }
 }
 
-
 /*** WSFR() - write to the "special function register" (SFR) ***/
-static void WSFR (struct cirrusfb_info *cinfo, unsigned char val)
+static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
 {
 #ifdef CONFIG_ZORRO
-       assert (cinfo->regbase != NULL);
+       assert(cinfo->regbase != NULL);
        cinfo->SFR = val;
-       z_writeb (val, cinfo->regbase + 0x8000);
+       z_writeb(val, cinfo->regbase + 0x8000);
 #endif
 }
 
 /* The Picasso has a second register for switching the monitor bit */
-static void WSFR2 (struct cirrusfb_info *cinfo, unsigned char val)
+static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
 {
 #ifdef CONFIG_ZORRO
        /* writing an arbitrary value to this one causes the monitor switcher */
        /* to flip to Amiga display */
-       assert (cinfo->regbase != NULL);
+       assert(cinfo->regbase != NULL);
        cinfo->SFR = val;
-       z_writeb (val, cinfo->regbase + 0x9000);
+       z_writeb(val, cinfo->regbase + 0x9000);
 #endif
 }
 
-
 /*** WClut - set CLUT entry (range: 0..63) ***/
-static void WClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
+static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
            unsigned char green, unsigned char blue)
 {
        unsigned int data = VGA_PEL_D;
 
        /* address write mode register is not translated.. */
-       vga_w (cinfo->regbase, VGA_PEL_IW, regnum);
+       vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
 
        if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
-           cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
+           cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 ||
+           cinfo->btype == BT_SD64 || is_laguna(cinfo)) {
                /* but DAC data register IS, at least for Picasso II */
                if (cinfo->btype == BT_PICASSO)
                        data += 0xfff;
-               vga_w (cinfo->regbase, data, red);
-               vga_w (cinfo->regbase, data, green);
-               vga_w (cinfo->regbase, data, blue);
+               vga_w(cinfo->regbase, data, red);
+               vga_w(cinfo->regbase, data, green);
+               vga_w(cinfo->regbase, data, blue);
        } else {
-               vga_w (cinfo->regbase, data, blue);
-               vga_w (cinfo->regbase, data, green);
-               vga_w (cinfo->regbase, data, red);
+               vga_w(cinfo->regbase, data, blue);
+               vga_w(cinfo->regbase, data, green);
+               vga_w(cinfo->regbase, data, red);
        }
 }
 
-
 #if 0
 /*** RClut - read CLUT entry (range 0..63) ***/
-static void RClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
+static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
            unsigned char *green, unsigned char *blue)
 {
        unsigned int data = VGA_PEL_D;
 
-       vga_w (cinfo->regbase, VGA_PEL_IR, regnum);
+       vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
 
        if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
            cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
                if (cinfo->btype == BT_PICASSO)
                        data += 0xfff;
-               *red = vga_r (cinfo->regbase, data);
-               *green = vga_r (cinfo->regbase, data);
-               *blue = vga_r (cinfo->regbase, data);
+               *red = vga_r(cinfo->regbase, data);
+               *green = vga_r(cinfo->regbase, data);
+               *blue = vga_r(cinfo->regbase, data);
        } else {
-               *blue = vga_r (cinfo->regbase, data);
-               *green = vga_r (cinfo->regbase, data);
-               *red = vga_r (cinfo->regbase, data);
+               *blue = vga_r(cinfo->regbase, data);
+               *green = vga_r(cinfo->regbase, data);
+               *red = vga_r(cinfo->regbase, data);
        }
 }
 #endif
 
-
 /*******************************************************************
        cirrusfb_WaitBLT()
 
@@ -2870,11 +2605,10 @@ static void RClut (struct cirrusfb_info *cinfo, unsigned char regnum, unsigned c
 *********************************************************************/
 
 /* FIXME: use interrupts instead */
-static void cirrusfb_WaitBLT (u8 __iomem *regbase)
+static void cirrusfb_WaitBLT(u8 __iomem *regbase)
 {
-       /* now busy-wait until we're done */
-       while (vga_rgfx (regbase, CL_GR31) & 0x08)
-               /* do nothing */ ;
+       while (vga_rgfx(regbase, CL_GR31) & 0x08)
+               cpu_relax();
 }
 
 /*******************************************************************
@@ -2883,247 +2617,205 @@ static void cirrusfb_WaitBLT (u8 __iomem *regbase)
        perform accelerated "scrolling"
 ********************************************************************/
 
-static void cirrusfb_BitBLT (u8 __iomem *regbase, int bits_per_pixel,
-                            u_short curx, u_short cury, u_short destx, u_short desty,
-                            u_short width, u_short height, u_short line_length)
-{
-       u_short nwidth, nheight;
-       u_long nsrc, ndest;
-       u_char bltmode;
-
-       DPRINTK ("ENTER\n");
-
-       nwidth = width - 1;
-       nheight = height - 1;
-
-       bltmode = 0x00;
-       /* if source adr < dest addr, do the Blt backwards */
-       if (cury <= desty) {
-               if (cury == desty) {
-                       /* if src and dest are on the same line, check x */
-                       if (curx < destx)
-                               bltmode |= 0x01;
-               } else
-                       bltmode |= 0x01;
-       }
-       if (!bltmode) {
-               /* standard case: forward blitting */
-               nsrc = (cury * line_length) + curx;
-               ndest = (desty * line_length) + destx;
-       } else {
-               /* this means start addresses are at the end, counting backwards */
-               nsrc = cury * line_length + curx + nheight * line_length + nwidth;
-               ndest = desty * line_length + destx + nheight * line_length + nwidth;
-       }
-
-       /*
-          run-down of registers to be programmed:
-          destination pitch
-          source pitch
-          BLT width/height
-          source start
-          destination start
-          BLT mode
-          BLT ROP
-          VGA_GFX_SR_VALUE / VGA_GFX_SR_ENABLE: "fill color"
-          start/stop
-        */
-
-        cirrusfb_WaitBLT(regbase);
+static void cirrusfb_set_blitter(u8 __iomem *regbase,
+                           u_short nwidth, u_short nheight,
+                           u_long nsrc, u_long ndest,
+                           u_short bltmode, u_short line_length)
 
+{
        /* pitch: set to line_length */
-       vga_wgfx (regbase, CL_GR24, line_length & 0xff);        /* dest pitch low */
-       vga_wgfx (regbase, CL_GR25, (line_length >> 8));        /* dest pitch hi */
-       vga_wgfx (regbase, CL_GR26, line_length & 0xff);        /* source pitch low */
-       vga_wgfx (regbase, CL_GR27, (line_length >> 8));        /* source pitch hi */
+       /* dest pitch low */
+       vga_wgfx(regbase, CL_GR24, line_length & 0xff);
+       /* dest pitch hi */
+       vga_wgfx(regbase, CL_GR25, line_length >> 8);
+       /* source pitch low */
+       vga_wgfx(regbase, CL_GR26, line_length & 0xff);
+       /* source pitch hi */
+       vga_wgfx(regbase, CL_GR27, line_length >> 8);
 
        /* BLT width: actual number of pixels - 1 */
-       vga_wgfx (regbase, CL_GR20, nwidth & 0xff);     /* BLT width low */
-       vga_wgfx (regbase, CL_GR21, (nwidth >> 8));     /* BLT width hi */
+       /* BLT width low */
+       vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
+       /* BLT width hi */
+       vga_wgfx(regbase, CL_GR21, nwidth >> 8);
 
        /* BLT height: actual number of lines -1 */
-       vga_wgfx (regbase, CL_GR22, nheight & 0xff);    /* BLT height low */
-       vga_wgfx (regbase, CL_GR23, (nheight >> 8));    /* BLT width hi */
+       /* BLT height low */
+       vga_wgfx(regbase, CL_GR22, nheight & 0xff);
+       /* BLT width hi */
+       vga_wgfx(regbase, CL_GR23, nheight >> 8);
 
        /* BLT destination */
-       vga_wgfx (regbase, CL_GR28, (u_char) (ndest & 0xff));   /* BLT dest low */
-       vga_wgfx (regbase, CL_GR29, (u_char) (ndest >> 8));     /* BLT dest mid */
-       vga_wgfx (regbase, CL_GR2A, (u_char) (ndest >> 16));    /* BLT dest hi */
+       /* BLT dest low */
+       vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
+       /* BLT dest mid */
+       vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
+       /* BLT dest hi */
+       vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
 
        /* BLT source */
-       vga_wgfx (regbase, CL_GR2C, (u_char) (nsrc & 0xff));    /* BLT src low */
-       vga_wgfx (regbase, CL_GR2D, (u_char) (nsrc >> 8));              /* BLT src mid */
-       vga_wgfx (regbase, CL_GR2E, (u_char) (nsrc >> 16));     /* BLT src hi */
+       /* BLT src low */
+       vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
+       /* BLT src mid */
+       vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
+       /* BLT src hi */
+       vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
 
        /* BLT mode */
-       vga_wgfx (regbase, CL_GR30, bltmode);   /* BLT mode */
+       vga_wgfx(regbase, CL_GR30, bltmode);    /* BLT mode */
 
        /* BLT ROP: SrcCopy */
-       vga_wgfx (regbase, CL_GR32, 0x0d);              /* BLT ROP */
+       vga_wgfx(regbase, CL_GR32, 0x0d);       /* BLT ROP */
 
        /* and finally: GO! */
-       vga_wgfx (regbase, CL_GR31, 0x02);              /* BLT Start/status */
-
-       DPRINTK ("EXIT\n");
+       vga_wgfx(regbase, CL_GR31, 0x02);       /* BLT Start/status */
 }
 
-
 /*******************************************************************
-       cirrusfb_RectFill()
+       cirrusfb_BitBLT()
 
-       perform accelerated rectangle fill
+       perform accelerated "scrolling"
 ********************************************************************/
 
-static void cirrusfb_RectFill (u8 __iomem *regbase, int bits_per_pixel,
-                    u_short x, u_short y, u_short width, u_short height,
-                    u_char color, u_short line_length)
+static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
+                           u_short curx, u_short cury,
+                           u_short destx, u_short desty,
+                           u_short width, u_short height,
+                           u_short line_length)
 {
-       u_short nwidth, nheight;
-       u_long ndest;
-       u_char op;
-
-       DPRINTK ("ENTER\n");
-
-       nwidth = width - 1;
-       nheight = height - 1;
+       u_short nwidth = width - 1;
+       u_short nheight = height - 1;
+       u_long nsrc, ndest;
+       u_char bltmode;
 
-       ndest = (y * line_length) + x;
+       bltmode = 0x00;
+       /* if source adr < dest addr, do the Blt backwards */
+       if (cury <= desty) {
+               if (cury == desty) {
+                       /* if src and dest are on the same line, check x */
+                       if (curx < destx)
+                               bltmode |= 0x01;
+               } else
+                       bltmode |= 0x01;
+       }
+       /* standard case: forward blitting */
+       nsrc = (cury * line_length) + curx;
+       ndest = (desty * line_length) + destx;
+       if (bltmode) {
+               /* this means start addresses are at the end,
+                * counting backwards
+                */
+               nsrc += nheight * line_length + nwidth;
+               ndest += nheight * line_length + nwidth;
+       }
 
-        cirrusfb_WaitBLT(regbase);
+       cirrusfb_WaitBLT(regbase);
 
-       /* pitch: set to line_length */
-       vga_wgfx (regbase, CL_GR24, line_length & 0xff);        /* dest pitch low */
-       vga_wgfx (regbase, CL_GR25, (line_length >> 8));        /* dest pitch hi */
-       vga_wgfx (regbase, CL_GR26, line_length & 0xff);        /* source pitch low */
-       vga_wgfx (regbase, CL_GR27, (line_length >> 8));        /* source pitch hi */
+       cirrusfb_set_blitter(regbase, nwidth, nheight,
+                           nsrc, ndest, bltmode, line_length);
+}
 
-       /* BLT width: actual number of pixels - 1 */
-       vga_wgfx (regbase, CL_GR20, nwidth & 0xff);     /* BLT width low */
-       vga_wgfx (regbase, CL_GR21, (nwidth >> 8));     /* BLT width hi */
+/*******************************************************************
+       cirrusfb_RectFill()
 
-       /* BLT height: actual number of lines -1 */
-       vga_wgfx (regbase, CL_GR22, nheight & 0xff);            /* BLT height low */
-       vga_wgfx (regbase, CL_GR23, (nheight >> 8));            /* BLT width hi */
+       perform accelerated rectangle fill
+********************************************************************/
 
-       /* BLT destination */
-       vga_wgfx (regbase, CL_GR28, (u_char) (ndest & 0xff));   /* BLT dest low */
-       vga_wgfx (regbase, CL_GR29, (u_char) (ndest >> 8));     /* BLT dest mid */
-       vga_wgfx (regbase, CL_GR2A, (u_char) (ndest >> 16));            /* BLT dest hi */
+static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
+                    u_short x, u_short y, u_short width, u_short height,
+                    u32 fg_color, u32 bg_color, u_short line_length,
+                    u_char blitmode)
+{
+       u_long ndest = (y * line_length) + x;
+       u_char op;
 
-       /* BLT source: set to 0 (is a dummy here anyway) */
-       vga_wgfx (regbase, CL_GR2C, 0x00);      /* BLT src low */
-       vga_wgfx (regbase, CL_GR2D, 0x00);      /* BLT src mid */
-       vga_wgfx (regbase, CL_GR2E, 0x00);      /* BLT src hi */
+       cirrusfb_WaitBLT(regbase);
 
        /* This is a ColorExpand Blt, using the */
        /* same color for foreground and background */
-       vga_wgfx (regbase, VGA_GFX_SR_VALUE, color);    /* foreground color */
-       vga_wgfx (regbase, VGA_GFX_SR_ENABLE, color);   /* background color */
-
-       op = 0xc0;
-       if (bits_per_pixel == 16) {
-               vga_wgfx (regbase, CL_GR10, color);     /* foreground color */
-               vga_wgfx (regbase, CL_GR11, color);     /* background color */
-               op = 0x50;
-               op = 0xd0;
-       } else if (bits_per_pixel == 32) {
-               vga_wgfx (regbase, CL_GR10, color);     /* foreground color */
-               vga_wgfx (regbase, CL_GR11, color);     /* background color */
-               vga_wgfx (regbase, CL_GR12, color);     /* foreground color */
-               vga_wgfx (regbase, CL_GR13, color);     /* background color */
-               vga_wgfx (regbase, CL_GR14, 0); /* foreground color */
-               vga_wgfx (regbase, CL_GR15, 0); /* background color */
-               op = 0x50;
-               op = 0xf0;
-       }
-       /* BLT mode: color expand, Enable 8x8 copy (faster?) */
-       vga_wgfx (regbase, CL_GR30, op);        /* BLT mode */
-
-       /* BLT ROP: SrcCopy */
-       vga_wgfx (regbase, CL_GR32, 0x0d);      /* BLT ROP */
-
-       /* and finally: GO! */
-       vga_wgfx (regbase, CL_GR31, 0x02);      /* BLT Start/status */
-
-       DPRINTK ("EXIT\n");
+       vga_wgfx(regbase, VGA_GFX_SR_VALUE, bg_color);
+       vga_wgfx(regbase, VGA_GFX_SR_ENABLE, fg_color);
+
+       op = 0x80;
+       if (bits_per_pixel >= 16) {
+               vga_wgfx(regbase, CL_GR10, bg_color >> 8);
+               vga_wgfx(regbase, CL_GR11, fg_color >> 8);
+               op = 0x90;
+       }
+       if (bits_per_pixel >= 24) {
+               vga_wgfx(regbase, CL_GR12, bg_color >> 16);
+               vga_wgfx(regbase, CL_GR13, fg_color >> 16);
+               op = 0xa0;
+       }
+       if (bits_per_pixel == 32) {
+               vga_wgfx(regbase, CL_GR14, bg_color >> 24);
+               vga_wgfx(regbase, CL_GR15, fg_color >> 24);
+               op = 0xb0;
+       }
+       cirrusfb_set_blitter(regbase, width - 1, height - 1,
+                           0, ndest, op | blitmode, line_length);
 }
 
-
 /**************************************************************************
  * bestclock() - determine closest possible clock lower(?) than the
  * desired pixel clock
  **************************************************************************/
-static void bestclock (long freq, long *best, long *nom,
-                      long *den, long *div, long maxfreq)
+static void bestclock(long freq, int *nom, int *den, int *div)
 {
-       long n, h, d, f;
+       int n, d;
+       long h, diff;
 
-       assert (best != NULL);
-       assert (nom != NULL);
-       assert (den != NULL);
-       assert (div != NULL);
-       assert (maxfreq > 0);
+       assert(nom != NULL);
+       assert(den != NULL);
+       assert(div != NULL);
 
        *nom = 0;
        *den = 0;
        *div = 0;
 
-       DPRINTK ("ENTER\n");
-
        if (freq < 8000)
                freq = 8000;
 
-       if (freq > maxfreq)
-               freq = maxfreq;
-
-       *best = 0;
-       f = freq * 10;
+       diff = freq;
 
        for (n = 32; n < 128; n++) {
-               d = (143181 * n) / f;
+               int s = 0;
+
+               d = (14318 * n) / freq;
                if ((d >= 7) && (d <= 63)) {
-                       if (d > 31)
-                               d = (d / 2) * 2;
-                       h = (14318 * n) / d;
-                       if (abs (h - freq) < abs (*best - freq)) {
-                               *best = h;
+                       int temp = d;
+
+                       if (temp > 31) {
+                               s = 1;
+                               temp >>= 1;
+                       }
+                       h = ((14318 * n) / temp) >> s;
+                       h = h > freq ? h - freq : freq - h;
+                       if (h < diff) {
+                               diff = h;
                                *nom = n;
-                               if (d < 32) {
-                                       *den = d;
-                                       *div = 0;
-                               } else {
-                                       *den = d / 2;
-                                       *div = 1;
-                               }
+                               *den = temp;
+                               *div = s;
                        }
                }
-               d = ((143181 * n) + f - 1) / f;
+               d++;
                if ((d >= 7) && (d <= 63)) {
-                       if (d > 31)
-                               d = (d / 2) * 2;
-                       h = (14318 * n) / d;
-                       if (abs (h - freq) < abs (*best - freq)) {
-                               *best = h;
+                       if (d > 31) {
+                               s = 1;
+                               d >>= 1;
+                       }
+                       h = ((14318 * n) / d) >> s;
+                       h = h > freq ? h - freq : freq - h;
+                       if (h < diff) {
+                               diff = h;
                                *nom = n;
-                               if (d < 32) {
-                                       *den = d;
-                                       *div = 0;
-                               } else {
-                                       *den = d / 2;
-                                       *div = 1;
-                               }
+                               *den = d;
+                               *div = s;
                        }
                }
        }
-
-       DPRINTK ("Best possible values for given frequency:\n");
-       DPRINTK ("        best: %ld kHz  nom: %ld  den: %ld  div: %ld\n",
-                freq, *nom, *den, *div);
-
-       DPRINTK ("EXIT\n");
 }
 
-
 /* -------------------------------------------------------------------------
  *
  * debugging functions
@@ -3134,33 +2826,6 @@ static void bestclock (long freq, long *best, long *nom,
 #ifdef CIRRUSFB_DEBUG
 
 /**
- * cirrusfb_dbg_print_byte
- * @name: name associated with byte value to be displayed
- * @val: byte value to be displayed
- *
- * DESCRIPTION:
- * Display an indented string, along with a hexidecimal byte value, and
- * its decoded bits.  Bits 7 through 0 are listed in left-to-right
- * order.
- */
-
-static
-void cirrusfb_dbg_print_byte (const char *name, unsigned char val)
-{
-       DPRINTK ("%8s = 0x%02X (bits 7-0: %c%c%c%c%c%c%c%c)\n",
-                name, val,
-                val & 0x80 ? '1' : '0',
-                val & 0x40 ? '1' : '0',
-                val & 0x20 ? '1' : '0',
-                val & 0x10 ? '1' : '0',
-                val & 0x08 ? '1' : '0',
-                val & 0x04 ? '1' : '0',
-                val & 0x02 ? '1' : '0',
-                val & 0x01 ? '1' : '0');
-}
-
-
-/**
  * cirrusfb_dbg_print_regs
  * @base: If using newmmio, the newmmio base address, otherwise %NULL
  * @reg_class: type of registers to read: %CRT, or %SEQ
@@ -3171,56 +2836,42 @@ void cirrusfb_dbg_print_byte (const char *name, unsigned char val)
  * used at the given @base address to query the information.
  */
 
-static
-void cirrusfb_dbg_print_regs (caddr_t regbase, cirrusfb_dbg_reg_class_t reg_class,...)
+static void cirrusfb_dbg_print_regs(struct fb_info *info,
+                                   caddr_t regbase,
+                                   enum cirrusfb_dbg_reg_class reg_class, ...)
 {
        va_list list;
        unsigned char val = 0;
        unsigned reg;
        char *name;
 
-       va_start (list, reg_class);
+       va_start(list, reg_class);
 
-       name = va_arg (list, char *);
+       name = va_arg(list, char *);
        while (name != NULL) {
-               reg = va_arg (list, int);
+               reg = va_arg(list, int);
 
                switch (reg_class) {
                case CRT:
-                       val = vga_rcrt (regbase, (unsigned char) reg);
+                       val = vga_rcrt(regbase, (unsigned char) reg);
                        break;
                case SEQ:
-                       val = vga_rseq (regbase, (unsigned char) reg);
+                       val = vga_rseq(regbase, (unsigned char) reg);
                        break;
                default:
                        /* should never occur */
-                       assert (FALSE);
+                       assert(false);
                        break;
                }
 
-               cirrusfb_dbg_print_byte (name, val);
+               dev_dbg(info->device, "%8s = 0x%02X\n", name, val);
 
-               name = va_arg (list, char *);
+               name = va_arg(list, char *);
        }
 
-       va_end (list);
+       va_end(list);
 }
 
-
-/**
- * cirrusfb_dump
- * @cirrusfbinfo:
- *
- * DESCRIPTION:
- */
-
-static
-void cirrusfb_dump (void)
-{
-       cirrusfb_dbg_reg_dump (NULL);
-}
-
-
 /**
  * cirrusfb_dbg_reg_dump
  * @base: If using newmmio, the newmmio base address, otherwise %NULL
@@ -3231,12 +2882,11 @@ void cirrusfb_dump (void)
  * used at the given @base address to query the information.
  */
 
-static
-void cirrusfb_dbg_reg_dump (caddr_t regbase)
+static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase)
 {
-       DPRINTK ("CIRRUSFB VGA CRTC register dump:\n");
+       dev_dbg(info->device, "VGA CRTC register dump:\n");
 
-       cirrusfb_dbg_print_regs (regbase, CRT,
+       cirrusfb_dbg_print_regs(info, regbase, CRT,
                           "CR00", 0x00,
                           "CR01", 0x01,
                           "CR02", 0x02,
@@ -3286,11 +2936,11 @@ void cirrusfb_dbg_reg_dump (caddr_t regbase)
                           "CR3F", 0x3F,
                           NULL);
 
-       DPRINTK ("\n");
+       dev_dbg(info->device, "\n");
 
-       DPRINTK ("CIRRUSFB VGA SEQ register dump:\n");
+       dev_dbg(info->device, "VGA SEQ register dump:\n");
 
-       cirrusfb_dbg_print_regs (regbase, SEQ,
+       cirrusfb_dbg_print_regs(info, regbase, SEQ,
                           "SR00", 0x00,
                           "SR01", 0x01,
                           "SR02", 0x02,
@@ -3319,7 +2969,7 @@ void cirrusfb_dbg_reg_dump (caddr_t regbase)
                           "SR1F", 0x1F,
                           NULL);
 
-       DPRINTK ("\n");
+       dev_dbg(info->device, "\n");
 }
 
 #endif                         /* CIRRUSFB_DEBUG */