Merge 'akpm' patch series
[linux-2.6.git] / drivers / video / cirrusfb.c
index 53572c0..6df7c54 100644 (file)
@@ -39,7 +39,6 @@
 #include <linux/errno.h>
 #include <linux/string.h>
 #include <linux/mm.h>
-#include <linux/slab.h>
 #include <linux/delay.h>
 #include <linux/fb.h>
 #include <linux/init.h>
 /* board types */
 enum cirrus_board {
        BT_NONE = 0,
-       BT_SD64,
-       BT_PICCOLO,
-       BT_PICASSO,
-       BT_SPECTRUM,
+       BT_SD64,        /* GD5434 */
+       BT_PICCOLO,     /* GD5426 */
+       BT_PICASSO,     /* GD5426 or GD5428 */
+       BT_SPECTRUM,    /* GD5426 or GD5428 */
        BT_PICASSO4,    /* GD5446 */
        BT_ALPINE,      /* GD543x/4x */
        BT_GD5480,
-       BT_LAGUNA,      /* GD546x */
+       BT_LAGUNA,      /* GD5462/64 */
+       BT_LAGUNAB,     /* GD5465 */
 };
 
 /*
@@ -144,8 +144,10 @@ static const struct cirrusfb_board_info_rec {
                .scrn_start_bit19       = true,
                .sr07                   = 0xF0,
                .sr07_1bpp              = 0xF0,
+               .sr07_1bpp_mux          = 0xF6,
                .sr07_8bpp              = 0xF1,
-               .sr1f                   = 0x20
+               .sr07_8bpp_mux          = 0xF7,
+               .sr1f                   = 0x1E
        },
        [BT_PICCOLO] = {
                .name                   = "CL Piccolo",
@@ -197,9 +199,11 @@ static const struct cirrusfb_board_info_rec {
                .init_sr07              = true,
                .init_sr1f              = false,
                .scrn_start_bit19       = true,
-               .sr07                   = 0x20,
-               .sr07_1bpp              = 0x20,
-               .sr07_8bpp              = 0x21,
+               .sr07                   = 0xA0,
+               .sr07_1bpp              = 0xA0,
+               .sr07_1bpp_mux          = 0xA6,
+               .sr07_8bpp              = 0xA1,
+               .sr07_8bpp_mux          = 0xA7,
                .sr1f                   = 0
        },
        [BT_ALPINE] = {
@@ -212,8 +216,8 @@ static const struct cirrusfb_board_info_rec {
                .init_sr1f              = true,
                .scrn_start_bit19       = true,
                .sr07                   = 0xA0,
-               .sr07_1bpp              = 0xA1,
-               .sr07_1bpp_mux          = 0xA7,
+               .sr07_1bpp              = 0xA0,
+               .sr07_1bpp_mux          = 0xA6,
                .sr07_8bpp              = 0xA1,
                .sr07_8bpp_mux          = 0xA7,
                .sr1f                   = 0x1C
@@ -234,8 +238,18 @@ static const struct cirrusfb_board_info_rec {
        [BT_LAGUNA] = {
                .name                   = "CL Laguna",
                .maxclock               = {
-                       /* guess */
-                       135100, 135100, 135100, 135100, 135100,
+                       /* taken from X11 code */
+                       170000, 170000, 170000, 170000, 135100,
+               },
+               .init_sr07              = false,
+               .init_sr1f              = false,
+               .scrn_start_bit19       = true,
+       },
+       [BT_LAGUNAB] = {
+               .name                   = "CL Laguna AGP",
+               .maxclock               = {
+                       /* taken from X11 code */
+                       170000, 250000, 170000, 170000, 135100,
                },
                .init_sr07              = false,
                .init_sr1f              = false,
@@ -249,8 +263,8 @@ static const struct cirrusfb_board_info_rec {
 
 static struct pci_device_id cirrusfb_pci_table[] = {
        CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
-       CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE),
-       CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE),
+       CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_SD64),
+       CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_SD64),
        CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
        CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
        CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
@@ -258,7 +272,7 @@ static struct pci_device_id cirrusfb_pci_table[] = {
        CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
        CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
        CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
-       CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNA), /* CL Laguna 3DA*/
+       CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNAB), /* CL Laguna 3DA*/
        { 0, }
 };
 MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
@@ -285,6 +299,7 @@ static const struct zorro_device_id cirrusfb_zorro_table[] = {
        },
        { 0 }
 };
+MODULE_DEVICE_TABLE(zorro, cirrusfb_zorro_table);
 
 static const struct {
        zorro_id id2;
@@ -313,10 +328,6 @@ static const struct {
 };
 #endif /* CONFIG_ZORRO */
 
-struct cirrusfb_regs {
-       int multiplexing;
-};
-
 #ifdef CIRRUSFB_DEBUG
 enum cirrusfb_dbg_reg_class {
        CRT,
@@ -331,7 +342,8 @@ struct cirrusfb_info {
        enum cirrus_board btype;
        unsigned char SFR;      /* Shadow of special function register */
 
-       struct cirrusfb_regs currentmode;
+       int multiplexing;
+       int doubleVCLK;
        int blank_mode;
        u32 pseudo_palette[16];
 
@@ -345,43 +357,8 @@ static char *mode_option __devinitdata = "640x480@60";
 /**** BEGIN PROTOTYPES ******************************************************/
 
 /*--- Interface used by the world ------------------------------------------*/
-static int cirrusfb_init(void);
-#ifndef MODULE
-static int cirrusfb_setup(char *options);
-#endif
-
-static int cirrusfb_open(struct fb_info *info, int user);
-static int cirrusfb_release(struct fb_info *info, int user);
-static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
-                             unsigned blue, unsigned transp,
-                             struct fb_info *info);
-static int cirrusfb_check_var(struct fb_var_screeninfo *var,
-                             struct fb_info *info);
-static int cirrusfb_set_par(struct fb_info *info);
 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
                                struct fb_info *info);
-static int cirrusfb_blank(int blank_mode, struct fb_info *info);
-static void cirrusfb_fillrect(struct fb_info *info,
-                             const struct fb_fillrect *region);
-static void cirrusfb_copyarea(struct fb_info *info,
-                             const struct fb_copyarea *area);
-static void cirrusfb_imageblit(struct fb_info *info,
-                              const struct fb_image *image);
-
-/* function table of the above functions */
-static struct fb_ops cirrusfb_ops = {
-       .owner          = THIS_MODULE,
-       .fb_open        = cirrusfb_open,
-       .fb_release     = cirrusfb_release,
-       .fb_setcolreg   = cirrusfb_setcolreg,
-       .fb_check_var   = cirrusfb_check_var,
-       .fb_set_par     = cirrusfb_set_par,
-       .fb_pan_display = cirrusfb_pan_display,
-       .fb_blank       = cirrusfb_blank,
-       .fb_fillrect    = cirrusfb_fillrect,
-       .fb_copyarea    = cirrusfb_copyarea,
-       .fb_imageblit   = cirrusfb_imageblit,
-};
 
 /*--- Internal routines ----------------------------------------------------*/
 static void init_vgachip(struct fb_info *info);
@@ -409,7 +386,8 @@ static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
                              u_short x, u_short y,
                              u_short width, u_short height,
-                             u_char color, u_short line_length);
+                             u32 fg_color, u32 bg_color,
+                             u_short line_length, u_char blitmode);
 
 static void bestclock(long freq, int *nom, int *den, int *div);
 
@@ -424,6 +402,11 @@ static void cirrusfb_dbg_print_regs(struct fb_info *info,
 /*****************************************************************************/
 /*** BEGIN Interface Used by the World ***************************************/
 
+static inline int is_laguna(const struct cirrusfb_info *cinfo)
+{
+       return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB;
+}
+
 static int opencount;
 
 /*--- Open /dev/fbx ---------------------------------------------------------*/
@@ -471,12 +454,70 @@ static int cirrusfb_check_mclk(struct fb_info *info, long freq)
        return 0;
 }
 
+static int cirrusfb_check_pixclock(const struct fb_var_screeninfo *var,
+                                  struct fb_info *info)
+{
+       long freq;
+       long maxclock;
+       struct cirrusfb_info *cinfo = info->par;
+       unsigned maxclockidx = var->bits_per_pixel >> 3;
+
+       /* convert from ps to kHz */
+       freq = PICOS2KHZ(var->pixclock);
+
+       dev_dbg(info->device, "desired pixclock: %ld kHz\n", freq);
+
+       maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
+       cinfo->multiplexing = 0;
+
+       /* If the frequency is greater than we can support, we might be able
+        * to use multiplexing for the video mode */
+       if (freq > maxclock) {
+               dev_err(info->device,
+                       "Frequency greater than maxclock (%ld kHz)\n",
+                       maxclock);
+               return -EINVAL;
+       }
+       /*
+        * Additional constraint: 8bpp uses DAC clock doubling to allow maximum
+        * pixel clock
+        */
+       if (var->bits_per_pixel == 8) {
+               switch (cinfo->btype) {
+               case BT_ALPINE:
+               case BT_SD64:
+               case BT_PICASSO4:
+                       if (freq > 85500)
+                               cinfo->multiplexing = 1;
+                       break;
+               case BT_GD5480:
+                       if (freq > 135100)
+                               cinfo->multiplexing = 1;
+                       break;
+
+               default:
+                       break;
+               }
+       }
+
+       /* If we have a 1MB 5434, we need to put ourselves in a mode where
+        * the VCLK is double the pixel clock. */
+       cinfo->doubleVCLK = 0;
+       if (cinfo->btype == BT_SD64 && info->fix.smem_len <= MB_ &&
+           var->bits_per_pixel == 16) {
+               cinfo->doubleVCLK = 1;
+       }
+
+       return 0;
+}
+
 static int cirrusfb_check_var(struct fb_var_screeninfo *var,
                              struct fb_info *info)
 {
        int yres;
        /* memory size in pixels */
        unsigned pixels = info->screen_size * 8 / var->bits_per_pixel;
+       struct cirrusfb_info *cinfo = info->par;
 
        switch (var->bits_per_pixel) {
        case 1:
@@ -488,7 +529,7 @@ static int cirrusfb_check_var(struct fb_var_screeninfo *var,
 
        case 8:
                var->red.offset = 0;
-               var->red.length = 6;
+               var->red.length = 8;
                var->green = var->red;
                var->blue = var->red;
                break;
@@ -499,20 +540,20 @@ static int cirrusfb_check_var(struct fb_var_screeninfo *var,
                        var->green.offset = -3;
                        var->blue.offset = 8;
                } else {
-                       var->red.offset = 10;
+                       var->red.offset = 11;
                        var->green.offset = 5;
                        var->blue.offset = 0;
                }
                var->red.length = 5;
-               var->green.length = 5;
+               var->green.length = 6;
                var->blue.length = 5;
                break;
 
-       case 32:
+       case 24:
                if (isPReP) {
-                       var->red.offset = 8;
-                       var->green.offset = 16;
-                       var->blue.offset = 24;
+                       var->red.offset = 0;
+                       var->green.offset = 8;
+                       var->blue.offset = 16;
                } else {
                        var->red.offset = 16;
                        var->green.offset = 8;
@@ -526,9 +567,7 @@ static int cirrusfb_check_var(struct fb_var_screeninfo *var,
        default:
                dev_dbg(info->device,
                        "Unsupported bpp size: %d\n", var->bits_per_pixel);
-               assert(false);
-               /* should never occur */
-               break;
+               return -EINVAL;
        }
 
        if (var->xres_virtual < var->xres)
@@ -552,7 +591,6 @@ static int cirrusfb_check_var(struct fb_var_screeninfo *var,
                return -EINVAL;
        }
 
-
        if (var->xoffset < 0)
                var->xoffset = 0;
        if (var->yoffset < 0)
@@ -583,81 +621,12 @@ static int cirrusfb_check_var(struct fb_var_screeninfo *var,
                return -EINVAL;
        }
 
-       return 0;
-}
-
-static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
-                               struct cirrusfb_regs *regs,
-                               struct fb_info *info)
-{
-       long freq;
-       long maxclock;
-       int maxclockidx = var->bits_per_pixel >> 3;
-       struct cirrusfb_info *cinfo = info->par;
-
-       switch (var->bits_per_pixel) {
-       case 1:
-               info->fix.line_length = var->xres_virtual / 8;
-               info->fix.visual = FB_VISUAL_MONO10;
-               break;
-
-       case 8:
-               info->fix.line_length = var->xres_virtual;
-               info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
-               break;
-
-       case 16:
-       case 32:
-               info->fix.line_length = var->xres_virtual * maxclockidx;
-               info->fix.visual = FB_VISUAL_TRUECOLOR;
-               break;
-
-       default:
-               dev_dbg(info->device,
-                       "Unsupported bpp size: %d\n", var->bits_per_pixel);
-               assert(false);
-               /* should never occur */
-               break;
-       }
-
-       info->fix.type = FB_TYPE_PACKED_PIXELS;
-
-       /* convert from ps to kHz */
-       freq = PICOS2KHZ(var->pixclock);
-
-       dev_dbg(info->device, "desired pixclock: %ld kHz\n", freq);
-
-       maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
-       regs->multiplexing = 0;
+       if (cirrusfb_check_pixclock(var, info))
+               return -EINVAL;
 
-       /* If the frequency is greater than we can support, we might be able
-        * to use multiplexing for the video mode */
-       if (freq > maxclock) {
-               switch (cinfo->btype) {
-               case BT_ALPINE:
-               case BT_GD5480:
-                       regs->multiplexing = 1;
-                       break;
+       if (!is_laguna(cinfo))
+               var->accel_flags = FB_ACCELF_TEXT;
 
-               default:
-                       dev_err(info->device,
-                               "Frequency greater than maxclock (%ld kHz)\n",
-                               maxclock);
-                       return -EINVAL;
-               }
-       }
-#if 0
-       /* TODO: If we have a 1MB 5434, we need to put ourselves in a mode where
-        * the VCLK is double the pixel clock. */
-       switch (var->bits_per_pixel) {
-       case 16:
-       case 32:
-               if (var->xres <= 800)
-                       /* Xbh has this type of clock for 32-bit */
-                       freq /= 2;
-               break;
-       }
-#endif
        return 0;
 }
 
@@ -691,74 +660,91 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
 {
        struct cirrusfb_info *cinfo = info->par;
        struct fb_var_screeninfo *var = &info->var;
-       struct cirrusfb_regs regs;
        u8 __iomem *regbase = cinfo->regbase;
        unsigned char tmp;
-       int err;
        int pitch;
        const struct cirrusfb_board_info_rec *bi;
        int hdispend, hsyncstart, hsyncend, htotal;
        int yres, vdispend, vsyncstart, vsyncend, vtotal;
        long freq;
        int nom, den, div;
-       unsigned int control, format, threshold;
+       unsigned int control = 0, format = 0, threshold = 0;
 
        dev_dbg(info->device, "Requested mode: %dx%dx%d\n",
               var->xres, var->yres, var->bits_per_pixel);
-       dev_dbg(info->device, "pixclock: %d\n", var->pixclock);
 
-       init_vgachip(info);
+       switch (var->bits_per_pixel) {
+       case 1:
+               info->fix.line_length = var->xres_virtual / 8;
+               info->fix.visual = FB_VISUAL_MONO10;
+               break;
 
-       err = cirrusfb_decode_var(var, &regs, info);
-       if (err) {
-               /* should never happen */
-               dev_dbg(info->device, "mode change aborted.  invalid var.\n");
-               return -EINVAL;
+       case 8:
+               info->fix.line_length = var->xres_virtual;
+               info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
+               break;
+
+       case 16:
+       case 24:
+               info->fix.line_length = var->xres_virtual *
+                                       var->bits_per_pixel >> 3;
+               info->fix.visual = FB_VISUAL_TRUECOLOR;
+               break;
        }
+       info->fix.type = FB_TYPE_PACKED_PIXELS;
+
+       init_vgachip(info);
 
        bi = &cirrusfb_board_info[cinfo->btype];
 
        hsyncstart = var->xres + var->right_margin;
        hsyncend = hsyncstart + var->hsync_len;
-       htotal = (hsyncend + var->left_margin) / 8 - 5;
-       hdispend = var->xres / 8 - 1;
-       hsyncstart = hsyncstart / 8 + 1;
-       hsyncend = hsyncend / 8 + 1;
+       htotal = (hsyncend + var->left_margin) / 8;
+       hdispend = var->xres / 8;
+       hsyncstart = hsyncstart / 8;
+       hsyncend = hsyncend / 8;
 
-       yres = var->yres;
-       vsyncstart = yres + var->lower_margin;
+       vdispend = var->yres;
+       vsyncstart = vdispend + var->lower_margin;
        vsyncend = vsyncstart + var->vsync_len;
        vtotal = vsyncend + var->upper_margin;
-       vdispend = yres - 1;
 
        if (var->vmode & FB_VMODE_DOUBLE) {
-               yres *= 2;
+               vdispend *= 2;
                vsyncstart *= 2;
                vsyncend *= 2;
                vtotal *= 2;
        } else if (var->vmode & FB_VMODE_INTERLACED) {
-               yres = (yres + 1) / 2;
+               vdispend = (vdispend + 1) / 2;
                vsyncstart = (vsyncstart + 1) / 2;
                vsyncend = (vsyncend + 1) / 2;
                vtotal = (vtotal + 1) / 2;
        }
-
-       vtotal -= 2;
-       vsyncstart -= 1;
-       vsyncend -= 1;
-
+       yres = vdispend;
        if (yres >= 1024) {
                vtotal /= 2;
                vsyncstart /= 2;
                vsyncend /= 2;
                vdispend /= 2;
        }
-       if (regs.multiplexing) {
+
+       vdispend -= 1;
+       vsyncstart -= 1;
+       vsyncend -= 1;
+       vtotal -= 2;
+
+       if (cinfo->multiplexing) {
                htotal /= 2;
                hsyncstart /= 2;
                hsyncend /= 2;
                hdispend /= 2;
        }
+
+       htotal -= 5;
+       hdispend -= 1;
+       hsyncstart += 1;
+       hsyncend += 1;
+
        /* unlock register VGA_CRTC_H_TOTAL..CRT7 */
        vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20);   /* previously: 0x00) */
 
@@ -849,6 +835,14 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
        vga_wcrt(regbase, CL_CRT1A, tmp);
 
        freq = PICOS2KHZ(var->pixclock);
+       if (var->bits_per_pixel == 24)
+               if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64)
+                       freq *= 3;
+       if (cinfo->multiplexing)
+               freq /= 2;
+       if (cinfo->doubleVCLK)
+               freq *= 2;
+
        bestclock(freq, &nom, &den, &div);
 
        dev_dbg(info->device, "VCLK freq: %ld kHz  nom: %d  den: %d  div: %d\n",
@@ -859,23 +853,26 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
        /* formula: VClk = (OSC * N) / (D * (1+P)) */
        /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
 
-       if (cinfo->btype == BT_ALPINE) {
+       if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4 ||
+           cinfo->btype == BT_SD64) {
                /* if freq is close to mclk or mclk/2 select mclk
                 * as clock source
                 */
                int divMCLK = cirrusfb_check_mclk(info, freq);
-               if (divMCLK)  {
+               if (divMCLK)
                        nom = 0;
-                       cirrusfb_set_mclk_as_source(info, divMCLK);
-               }
+               cirrusfb_set_mclk_as_source(info, divMCLK);
        }
-       if (cinfo->btype == BT_LAGUNA) {
+       if (is_laguna(cinfo)) {
                long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc);
                unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407);
                unsigned short tile_control;
 
-               tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4);
-               fb_writew(tile_control & ~0x80, cinfo->laguna_mmio + 0x2c4);
+               if (cinfo->btype == BT_LAGUNAB) {
+                       tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4);
+                       tile_control &= ~0x80;
+                       fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4);
+               }
 
                fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc);
                fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407);
@@ -883,8 +880,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
                threshold = fb_readw(cinfo->laguna_mmio + 0xea);
                control &= ~0x6800;
                format = 0;
-               threshold &= 0xffe0;
-               threshold &= 0x3fbf;
+               threshold &= 0xffc0 & 0x3fbf;
        }
        if (nom) {
                tmp = den << 1;
@@ -896,14 +892,13 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
                    (cinfo->btype == BT_GD5480))
                        tmp |= 0x80;
 
-               dev_dbg(info->device, "CL_SEQR1B: %d\n", (int) tmp);
                /* Laguna chipset has reversed clock registers */
-               if (cinfo->btype == BT_LAGUNA) {
+               if (is_laguna(cinfo)) {
                        vga_wseq(regbase, CL_SEQRE, tmp);
                        vga_wseq(regbase, CL_SEQR1E, nom);
                } else {
-                       vga_wseq(regbase, CL_SEQRB, nom);
-                       vga_wseq(regbase, CL_SEQR1B, tmp);
+                       vga_wseq(regbase, CL_SEQRE, nom);
+                       vga_wseq(regbase, CL_SEQR1E, tmp);
                }
        }
 
@@ -915,9 +910,6 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
                 * address wrap, no compat. */
                vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
 
-/* HAEH?       vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20);
- * previously: 0x00  unlock VGA_CRTC_H_TOTAL..CRT7 */
-
        /* don't know if it would hurt to also program this if no interlaced */
        /* mode is used, but I feel better this way.. :-) */
        if (var->vmode & FB_VMODE_INTERLACED)
@@ -925,19 +917,15 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
        else
                vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
 
-       vga_wseq(regbase, VGA_SEQ_CHARACTER_MAP, 0);
-
-       /* adjust horizontal/vertical sync type (low/high) */
+       /* adjust horizontal/vertical sync type (low/high), use VCLK3 */
        /* enable display memory & CRTC I/O address for color mode */
-       tmp = 0x03;
+       tmp = 0x03 | 0xc;
        if (var->sync & FB_SYNC_HOR_HIGH_ACT)
                tmp |= 0x40;
        if (var->sync & FB_SYNC_VERT_HIGH_ACT)
                tmp |= 0x80;
        WGen(cinfo, VGA_MIS_W, tmp);
 
-       /* Screen A Preset Row-Scan register */
-       vga_wcrt(regbase, VGA_CRTC_PRESET_ROW, 0);
        /* text cursor on and start line */
        vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
        /* text cursor end line */
@@ -964,11 +952,12 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
                case BT_ALPINE:
                case BT_GD5480:
                        vga_wseq(regbase, CL_SEQR7,
-                                regs.multiplexing ?
+                                cinfo->multiplexing ?
                                        bi->sr07_1bpp_mux : bi->sr07_1bpp);
                        break;
 
                case BT_LAGUNA:
+               case BT_LAGUNAB:
                        vga_wseq(regbase, CL_SEQR7,
                                vga_rseq(regbase, CL_SEQR7) & ~0x01);
                        break;
@@ -980,34 +969,24 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
 
                /* Extended Sequencer Mode */
                switch (cinfo->btype) {
-               case BT_SD64:
-                       /* setting the SEQRF on SD64 is not necessary
-                        * (only during init)
-                        */
-                       /*  MCLK select */
-                       vga_wseq(regbase, CL_SEQR1F, 0x1a);
-                       break;
 
                case BT_PICCOLO:
                case BT_SPECTRUM:
-                       /* ### ueberall 0x22? */
-                       /* ##vorher 1c MCLK select */
-                       vga_wseq(regbase, CL_SEQR1F, 0x22);
                        /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
                        vga_wseq(regbase, CL_SEQRF, 0xb0);
                        break;
 
                case BT_PICASSO:
-                       /* ##vorher 22 MCLK select */
-                       vga_wseq(regbase, CL_SEQR1F, 0x22);
                        /* ## vorher d0 avoid FIFO underruns..? */
                        vga_wseq(regbase, CL_SEQRF, 0xd0);
                        break;
 
+               case BT_SD64:
                case BT_PICASSO4:
                case BT_ALPINE:
                case BT_GD5480:
                case BT_LAGUNA:
+               case BT_LAGUNAB:
                        /* do nothing */
                        break;
 
@@ -1018,7 +997,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
 
                /* pixel mask: pass-through for first plane */
                WGen(cinfo, VGA_PEL_MSK, 0x01);
-               if (regs.multiplexing)
+               if (cinfo->multiplexing)
                        /* hidden dac reg: 1280x1024 */
                        WHDR(cinfo, 0x4a);
                else
@@ -1047,11 +1026,12 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
                case BT_ALPINE:
                case BT_GD5480:
                        vga_wseq(regbase, CL_SEQR7,
-                                 regs.multiplexing ?
+                                 cinfo->multiplexing ?
                                        bi->sr07_8bpp_mux : bi->sr07_8bpp);
                        break;
 
                case BT_LAGUNA:
+               case BT_LAGUNAB:
                        vga_wseq(regbase, CL_SEQR7,
                                vga_rseq(regbase, CL_SEQR7) | 0x01);
                        threshold |= 0x10;
@@ -1063,16 +1043,9 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
                }
 
                switch (cinfo->btype) {
-               case BT_SD64:
-                       /* MCLK select */
-                       vga_wseq(regbase, CL_SEQR1F, 0x1d);
-                       break;
-
                case BT_PICCOLO:
                case BT_PICASSO:
                case BT_SPECTRUM:
-                       /* ### vorher 1c MCLK select */
-                       vga_wseq(regbase, CL_SEQR1F, 0x22);
                        /* Fast Page-Mode writes */
                        vga_wseq(regbase, CL_SEQRF, 0xb0);
                        break;
@@ -1082,15 +1055,11 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
                        /* ### INCOMPLETE!! */
                        vga_wseq(regbase, CL_SEQRF, 0xb8);
 #endif
-/*                     vga_wseq(regbase, CL_SEQR1F, 0x1c); */
-                       break;
-
                case BT_ALPINE:
-                       /* We already set SRF and SR1F */
-                       break;
-
+               case BT_SD64:
                case BT_GD5480:
                case BT_LAGUNA:
+               case BT_LAGUNAB:
                        /* do nothing */
                        break;
 
@@ -1101,18 +1070,12 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
 
                /* mode register: 256 color mode */
                vga_wgfx(regbase, VGA_GFX_MODE, 64);
-               /* pixel mask: pass-through all planes */
-               WGen(cinfo, VGA_PEL_MSK, 0xff);
-               if (regs.multiplexing)
+               if (cinfo->multiplexing)
                        /* hidden dac reg: 1280x1024 */
                        WHDR(cinfo, 0x4a);
                else
                        /* hidden dac: nothing */
                        WHDR(cinfo, 0);
-               /* memory mode: chain4, ext. memory */
-               vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
-               /* plane mask: enable writing to all 4 planes */
-               vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
        }
 
        /******************************************************
@@ -1124,37 +1087,25 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
        else if (var->bits_per_pixel == 16) {
                dev_dbg(info->device, "preparing for 16 bit deep display\n");
                switch (cinfo->btype) {
-               case BT_SD64:
-                       /* Extended Sequencer Mode: 256c col. mode */
-                       vga_wseq(regbase, CL_SEQR7, 0xf7);
-                       /* MCLK select */
-                       vga_wseq(regbase, CL_SEQR1F, 0x1e);
-                       break;
-
                case BT_PICCOLO:
                case BT_SPECTRUM:
                        vga_wseq(regbase, CL_SEQR7, 0x87);
                        /* Fast Page-Mode writes */
                        vga_wseq(regbase, CL_SEQRF, 0xb0);
-                       /* MCLK select */
-                       vga_wseq(regbase, CL_SEQR1F, 0x22);
                        break;
 
                case BT_PICASSO:
                        vga_wseq(regbase, CL_SEQR7, 0x27);
                        /* Fast Page-Mode writes */
                        vga_wseq(regbase, CL_SEQRF, 0xb0);
-                       /* MCLK select */
-                       vga_wseq(regbase, CL_SEQR1F, 0x22);
                        break;
 
+               case BT_SD64:
                case BT_PICASSO4:
-                       vga_wseq(regbase, CL_SEQR7, 0x27);
-/*                     vga_wseq(regbase, CL_SEQR1F, 0x1c);  */
-                       break;
-
                case BT_ALPINE:
-                       vga_wseq(regbase, CL_SEQR7, 0xa7);
+                       /* Extended Sequencer Mode: 256c col. mode */
+                       vga_wseq(regbase, CL_SEQR7,
+                                       cinfo->doubleVCLK ? 0xa3 : 0xa7);
                        break;
 
                case BT_GD5480:
@@ -1163,6 +1114,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
                        break;
 
                case BT_LAGUNA:
+               case BT_LAGUNAB:
                        vga_wseq(regbase, CL_SEQR7,
                                vga_rseq(regbase, CL_SEQR7) & ~0x01);
                        control |= 0x2000;
@@ -1177,72 +1129,54 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
 
                /* mode register: 256 color mode */
                vga_wgfx(regbase, VGA_GFX_MODE, 64);
-               /* pixel mask: pass-through all planes */
-               WGen(cinfo, VGA_PEL_MSK, 0xff);
 #ifdef CONFIG_PCI
-               WHDR(cinfo, 0xc0);      /* Copy Xbh */
+               WHDR(cinfo, cinfo->doubleVCLK ? 0xe1 : 0xc1);
 #elif defined(CONFIG_ZORRO)
                /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
                WHDR(cinfo, 0xa0);      /* hidden dac reg: nothing special */
 #endif
-               /* memory mode: chain4, ext. memory */
-               vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
-               /* plane mask: enable writing to all 4 planes */
-               vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
        }
 
        /******************************************************
         *
-        * 32 bpp
+        * 24 bpp
         *
         */
 
-       else if (var->bits_per_pixel == 32) {
-               dev_dbg(info->device, "preparing for 32 bit deep display\n");
+       else if (var->bits_per_pixel == 24) {
+               dev_dbg(info->device, "preparing for 24 bit deep display\n");
                switch (cinfo->btype) {
-               case BT_SD64:
-                       /* Extended Sequencer Mode: 256c col. mode */
-                       vga_wseq(regbase, CL_SEQR7, 0xf9);
-                       /* MCLK select */
-                       vga_wseq(regbase, CL_SEQR1F, 0x1e);
-                       break;
-
                case BT_PICCOLO:
                case BT_SPECTRUM:
                        vga_wseq(regbase, CL_SEQR7, 0x85);
                        /* Fast Page-Mode writes */
                        vga_wseq(regbase, CL_SEQRF, 0xb0);
-                       /* MCLK select */
-                       vga_wseq(regbase, CL_SEQR1F, 0x22);
                        break;
 
                case BT_PICASSO:
                        vga_wseq(regbase, CL_SEQR7, 0x25);
                        /* Fast Page-Mode writes */
                        vga_wseq(regbase, CL_SEQRF, 0xb0);
-                       /* MCLK select */
-                       vga_wseq(regbase, CL_SEQR1F, 0x22);
                        break;
 
+               case BT_SD64:
                case BT_PICASSO4:
-                       vga_wseq(regbase, CL_SEQR7, 0x25);
-/*                     vga_wseq(regbase, CL_SEQR1F, 0x1c);  */
-                       break;
-
                case BT_ALPINE:
-                       vga_wseq(regbase, CL_SEQR7, 0xa9);
+                       /* Extended Sequencer Mode: 256c col. mode */
+                       vga_wseq(regbase, CL_SEQR7, 0xa5);
                        break;
 
                case BT_GD5480:
-                       vga_wseq(regbase, CL_SEQR7, 0x19);
+                       vga_wseq(regbase, CL_SEQR7, 0x15);
                        /* We already set SRF and SR1F */
                        break;
 
                case BT_LAGUNA:
+               case BT_LAGUNAB:
                        vga_wseq(regbase, CL_SEQR7,
                                vga_rseq(regbase, CL_SEQR7) & ~0x01);
-                       control |= 0x6000;
-                       format |= 0x3400;
+                       control |= 0x4000;
+                       format |= 0x2400;
                        threshold |= 0x20;
                        break;
 
@@ -1253,14 +1187,8 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
 
                /* mode register: 256 color mode */
                vga_wgfx(regbase, VGA_GFX_MODE, 64);
-               /* pixel mask: pass-through all planes */
-               WGen(cinfo, VGA_PEL_MSK, 0xff);
                /* hidden dac reg: 8-8-8 mode (24 or 32) */
                WHDR(cinfo, 0xc5);
-               /* memory mode: chain4, ext. memory */
-               vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
-               /* plane mask: enable writing to all 4 planes */
-               vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
        }
 
        /******************************************************
@@ -1287,9 +1215,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
        if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
                vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1);
 
-       if (cinfo->btype == BT_LAGUNA ||
-           cinfo->btype == BT_GD5480) {
-
+       if (is_laguna(cinfo)) {
                tmp = 0;
                if ((htotal + 5) & 256)
                        tmp |= 128;
@@ -1308,50 +1234,14 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
                dev_dbg(info->device, "CRT1e: %d\n", tmp);
        }
 
-
-       /* text cursor location high */
-       vga_wcrt(regbase, VGA_CRTC_CURSOR_HI, 0);
-       /* text cursor location low */
-       vga_wcrt(regbase, VGA_CRTC_CURSOR_LO, 0);
-       /* underline row scanline = at very bottom */
-       vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0);
-
-       /* controller mode */
-       vga_wattr(regbase, VGA_ATC_MODE, 1);
-       /* overscan (border) color */
-       vga_wattr(regbase, VGA_ATC_OVERSCAN, 0);
-       /* color plane enable */
-       vga_wattr(regbase, VGA_ATC_PLANE_ENABLE, 15);
        /* pixel panning */
        vga_wattr(regbase, CL_AR33, 0);
-       /* color select */
-       vga_wattr(regbase, VGA_ATC_COLOR_PAGE, 0);
 
        /* [ EGS: SetOffset(); ] */
        /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
        AttrOn(cinfo);
 
-       /* set/reset register */
-       vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0);
-       /* set/reset enable */
-       vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0);
-       /* color compare */
-       vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0);
-       /* data rotate */
-       vga_wgfx(regbase, VGA_GFX_DATA_ROTATE, 0);
-       /* read map select */
-       vga_wgfx(regbase, VGA_GFX_PLANE_READ, 0);
-       /* miscellaneous register */
-       vga_wgfx(regbase, VGA_GFX_MISC, 1);
-       /* color don't care */
-       vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 15);
-       /* bit mask */
-       vga_wgfx(regbase, VGA_GFX_BIT_MASK, 255);
-
-       /* graphics cursor attributes: nothing special */
-       vga_wseq(regbase, CL_SEQR12, 0x0);
-
-       if (cinfo->btype == BT_LAGUNA) {
+       if (is_laguna(cinfo)) {
                /* no tiles */
                fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402);
                fb_writew(format, cinfo->laguna_mmio + 0xc0);
@@ -1369,11 +1259,6 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
        vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
        dev_dbg(info->device, "CL_SEQR1: %d\n", tmp);
 
-       cinfo->currentmode = regs;
-
-       /* pan to requested offset */
-       cirrusfb_pan_display(var, info);
-
 #ifdef CIRRUSFB_DEBUG
        cirrusfb_dbg_reg_dump(info, NULL);
 #endif
@@ -1429,27 +1314,19 @@ static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
                                struct fb_info *info)
 {
-       int xoffset = 0;
-       int yoffset = 0;
+       int xoffset;
        unsigned long base;
        unsigned char tmp, xpix;
        struct cirrusfb_info *cinfo = info->par;
 
-       dev_dbg(info->device,
-               "virtual offset: (%d,%d)\n", var->xoffset, var->yoffset);
-
        /* no range checks for xoffset and yoffset,   */
        /* as fb_pan_display has already done this */
        if (var->vmode & FB_VMODE_YWRAP)
                return -EINVAL;
 
-       info->var.xoffset = var->xoffset;
-       info->var.yoffset = var->yoffset;
-
        xoffset = var->xoffset * info->var.bits_per_pixel / 8;
-       yoffset = var->yoffset;
 
-       base = yoffset * info->fix.line_length + xoffset;
+       base = var->yoffset * info->fix.line_length + xoffset;
 
        if (info->var.bits_per_pixel == 1) {
                /* base is already correct */
@@ -1459,13 +1336,12 @@ static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
                xpix = (unsigned char) ((xoffset % 4) * 2);
        }
 
-       cirrusfb_WaitBLT(cinfo->regbase); /* make sure all the BLT's are done */
+       if (!is_laguna(cinfo))
+               cirrusfb_WaitBLT(cinfo->regbase);
 
        /* lower 8 + 8 bits of screen start address */
-       vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO,
-                (unsigned char) (base & 0xff));
-       vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI,
-                (unsigned char) (base >> 8));
+       vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff);
+       vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff);
 
        /* 0xf2 is %11110010, exclude tmp bits */
        tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2;
@@ -1480,8 +1356,14 @@ static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
        vga_wcrt(cinfo->regbase, CL_CRT1B, tmp);
 
        /* construct bit 19 of screen start address */
-       if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
-               vga_wcrt(cinfo->regbase, CL_CRT1D, (base >> 12) & 0x80);
+       if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
+               tmp = vga_rcrt(cinfo->regbase, CL_CRT1D);
+               if (is_laguna(cinfo))
+                       tmp = (tmp & ~0x18) | ((base >> 16) & 0x18);
+               else
+                       tmp = (tmp & ~0x80) | ((base >> 12) & 0x80);
+               vga_wcrt(cinfo->regbase, CL_CRT1D, tmp);
+       }
 
        /* write pixel panning value to AR33; this does not quite work in 8bpp
         *
@@ -1490,8 +1372,6 @@ static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
        if (info->var.bits_per_pixel == 1)
                vga_wattr(cinfo->regbase, CL_AR33, xpix);
 
-       cirrusfb_WaitBLT(cinfo->regbase);
-
        return 0;
 }
 
@@ -1596,20 +1476,18 @@ static void init_vgachip(struct fb_info *info)
                /* disable flickerfixer */
                vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
                mdelay(100);
-               /* from Klaus' NetBSD driver: */
-               vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
-               /* put blitter into 542x compat */
-               vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
                /* mode */
                vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
-               break;
-
-       case BT_GD5480:
+       case BT_GD5480:  /* fall through */
                /* from Klaus' NetBSD driver: */
                vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
+       case BT_ALPINE:  /* fall through */
+               /* put blitter into 542x compat */
+               vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
                break;
 
-       case BT_ALPINE:
+       case BT_LAGUNA:
+       case BT_LAGUNAB:
                /* Nothing to do to reset the board. */
                break;
 
@@ -1634,31 +1512,28 @@ static void init_vgachip(struct fb_info *info)
                        WGen(cinfo, CL_VSSM2, 0x01);
 
                /* reset sequencer logic */
-               vga_wseq(cinfo->regbase, CL_SEQR0, 0x03);
+               vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03);
 
                /* FullBandwidth (video off) and 8/9 dot clock */
                vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
-               /* polarity (-/-), disable access to display memory,
-                * VGA_CRTC_START_HI base address: color
-                */
-               WGen(cinfo, VGA_MIS_W, 0xc1);
 
                /* "magic cookie" - doesn't make any sense to me.. */
 /*      vga_wgfx(cinfo->regbase, CL_GRA, 0xce);   */
                /* unlock all extension registers */
                vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
 
-               /* reset blitter */
-               vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
-
                switch (cinfo->btype) {
                case BT_GD5480:
                        vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
                        break;
                case BT_ALPINE:
+               case BT_LAGUNA:
+               case BT_LAGUNAB:
                        break;
                case BT_SD64:
+#ifdef CONFIG_ZORRO
                        vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
+#endif
                        break;
                default:
                        vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
@@ -1670,8 +1545,8 @@ static void init_vgachip(struct fb_info *info)
        vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
        /* character map select: doesn't even matter in gx mode */
        vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
-       /* memory mode: chain-4, no odd/even, ext. memory */
-       vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0e);
+       /* memory mode: chain4, ext. memory */
+       vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
 
        /* controller-internal base address of video memory */
        if (bi->init_sr07)
@@ -1697,20 +1572,12 @@ static void init_vgachip(struct fb_info *info)
                vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
        }
 
-       /* MCLK select etc. */
-       if (bi->init_sr1f)
-               vga_wseq(cinfo->regbase, CL_SEQR1F, bi->sr1f);
-
        /* Screen A preset row scan: none */
        vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
        /* Text cursor start: disable text cursor */
        vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
        /* Text cursor end: - */
        vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
-       /* Screen start address high: 0 */
-       vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, 0x00);
-       /* Screen start address low: 0 */
-       vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, 0x00);
        /* text cursor location high: 0 */
        vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
        /* text cursor location low: 0 */
@@ -1718,10 +1585,6 @@ static void init_vgachip(struct fb_info *info)
 
        /* Underline Row scanline: - */
        vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
-       /* mode control: timing enable, byte mode, no compat modes */
-       vga_wcrt(cinfo->regbase, VGA_CRTC_MODE, 0xc3);
-       /* Line Compare: not needed */
-       vga_wcrt(cinfo->regbase, VGA_CRTC_LINE_COMPARE, 0x00);
        /* ### add 0x40 for text modes with > 30 MHz pixclock */
        /* ext. display controls: ext.adr. wrap */
        vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
@@ -1744,7 +1607,9 @@ static void init_vgachip(struct fb_info *info)
        vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
        /* Bit Mask: no mask at all */
        vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
-       if (cinfo->btype == BT_ALPINE)
+
+       if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64 ||
+           is_laguna(cinfo))
                /* (5434 can't have bit 3 set for bitblt) */
                vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
        else
@@ -1784,18 +1649,11 @@ static void init_vgachip(struct fb_info *info)
        vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
        /* Color Plane enable: Enable all 4 planes */
        vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
-/* ###  vga_wattr(cinfo->regbase, CL_AR33, 0x00); * Pixel Panning: - */
        /* Color Select: - */
        vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
 
        WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
 
-       if (cinfo->btype != BT_ALPINE && cinfo->btype != BT_GD5480)
-       /* polarity (-/-), enable display mem,
-        * VGA_CRTC_START_HI i/o base = color
-        */
-               WGen(cinfo, VGA_MIS_W, 0xc3);
-
        /* BLT Start/status: Blitter reset */
        vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
        /* - " -           : "end-of-reset" */
@@ -1857,6 +1715,17 @@ static void switch_monitor(struct cirrusfb_info *cinfo, int on)
 /* Linux 2.6-style  accelerated functions */
 /******************************************/
 
+static int cirrusfb_sync(struct fb_info *info)
+{
+       struct cirrusfb_info *cinfo = info->par;
+
+       if (!is_laguna(cinfo)) {
+               while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03)
+                       cpu_relax();
+       }
+       return 0;
+}
+
 static void cirrusfb_fillrect(struct fb_info *info,
                              const struct fb_fillrect *region)
 {
@@ -1892,8 +1761,8 @@ static void cirrusfb_fillrect(struct fb_info *info,
                          info->var.bits_per_pixel,
                          (region->dx * m) / 8, region->dy,
                          (region->width * m) / 8, region->height,
-                         color,
-                         info->fix.line_length);
+                         color, color,
+                         info->fix.line_length, 0x40);
 }
 
 static void cirrusfb_copyarea(struct fb_info *info,
@@ -1941,9 +1810,46 @@ static void cirrusfb_imageblit(struct fb_info *info,
                               const struct fb_image *image)
 {
        struct cirrusfb_info *cinfo = info->par;
+       unsigned char op = (info->var.bits_per_pixel == 24) ? 0xc : 0x4;
 
-       cirrusfb_WaitBLT(cinfo->regbase);
-       cfb_imageblit(info, image);
+       if (info->state != FBINFO_STATE_RUNNING)
+               return;
+       /* Alpine/SD64 does not work at 24bpp ??? */
+       if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1)
+               cfb_imageblit(info, image);
+       else if ((cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) &&
+                 op == 0xc)
+               cfb_imageblit(info, image);
+       else {
+               unsigned size = ((image->width + 7) >> 3) * image->height;
+               int m = info->var.bits_per_pixel;
+               u32 fg, bg;
+
+               if (info->var.bits_per_pixel == 8) {
+                       fg = image->fg_color;
+                       bg = image->bg_color;
+               } else {
+                       fg = ((u32 *)(info->pseudo_palette))[image->fg_color];
+                       bg = ((u32 *)(info->pseudo_palette))[image->bg_color];
+               }
+               if (info->var.bits_per_pixel == 24) {
+                       /* clear background first */
+                       cirrusfb_RectFill(cinfo->regbase,
+                                         info->var.bits_per_pixel,
+                                         (image->dx * m) / 8, image->dy,
+                                         (image->width * m) / 8,
+                                         image->height,
+                                         bg, bg,
+                                         info->fix.line_length, 0x40);
+               }
+               cirrusfb_RectFill(cinfo->regbase,
+                                 info->var.bits_per_pixel,
+                                 (image->dx * m) / 8, image->dy,
+                                 (image->width * m) / 8, image->height,
+                                 fg, bg,
+                                 info->fix.line_length, op);
+               memcpy(info->screen_base, image->data, size);
+       }
 }
 
 #ifdef CONFIG_PPC_PREP
@@ -1970,7 +1876,7 @@ static unsigned int __devinit cirrusfb_get_memsize(struct fb_info *info,
        unsigned long mem;
        struct cirrusfb_info *cinfo = info->par;
 
-       if (cinfo->btype == BT_LAGUNA) {
+       if (is_laguna(cinfo)) {
                unsigned char SR14 = vga_rseq(regbase, CL_SEQR14);
 
                mem = ((SR14 & 7) + 1) << 20;
@@ -1996,7 +1902,7 @@ static unsigned int __devinit cirrusfb_get_memsize(struct fb_info *info,
                /* If DRAM bank switching is enabled, there must be
                 * twice as much memory installed. (4MB on the 5434)
                 */
-               if (SRF & 0x80)
+               if (cinfo->btype != BT_ALPINE && (SRF & 0x80) != 0)
                        mem *= 2;
        }
 
@@ -2063,6 +1969,22 @@ static void cirrusfb_zorro_unmap(struct fb_info *info)
 }
 #endif /* CONFIG_ZORRO */
 
+/* function table of the above functions */
+static struct fb_ops cirrusfb_ops = {
+       .owner          = THIS_MODULE,
+       .fb_open        = cirrusfb_open,
+       .fb_release     = cirrusfb_release,
+       .fb_setcolreg   = cirrusfb_setcolreg,
+       .fb_check_var   = cirrusfb_check_var,
+       .fb_set_par     = cirrusfb_set_par,
+       .fb_pan_display = cirrusfb_pan_display,
+       .fb_blank       = cirrusfb_blank,
+       .fb_fillrect    = cirrusfb_fillrect,
+       .fb_copyarea    = cirrusfb_copyarea,
+       .fb_sync        = cirrusfb_sync,
+       .fb_imageblit   = cirrusfb_imageblit,
+};
+
 static int __devinit cirrusfb_set_fbinfo(struct fb_info *info)
 {
        struct cirrusfb_info *cinfo = info->par;
@@ -2073,10 +1995,16 @@ static int __devinit cirrusfb_set_fbinfo(struct fb_info *info)
                    | FBINFO_HWACCEL_XPAN
                    | FBINFO_HWACCEL_YPAN
                    | FBINFO_HWACCEL_FILLRECT
+                   | FBINFO_HWACCEL_IMAGEBLIT
                    | FBINFO_HWACCEL_COPYAREA;
-       if (noaccel)
+       if (noaccel || is_laguna(cinfo)) {
                info->flags |= FBINFO_HWACCEL_DISABLED;
+               info->fix.accel = FB_ACCEL_NONE;
+       } else
+               info->fix.accel = FB_ACCEL_CIRRUS_ALPINE;
+
        info->fbops = &cirrusfb_ops;
+
        if (cinfo->btype == BT_GD5480) {
                if (var->bits_per_pixel == 16)
                        info->screen_base += 1 * MB_;
@@ -2100,7 +2028,6 @@ static int __devinit cirrusfb_set_fbinfo(struct fb_info *info)
 
        /* FIXME: map region at 0xB8000 if available, fill in here */
        info->fix.mmio_len   = 0;
-       info->fix.accel = FB_ACCEL_NONE;
 
        fb_alloc_cmap(&info->cmap, 256, 0);
 
@@ -2111,12 +2038,9 @@ static int __devinit cirrusfb_register(struct fb_info *info)
 {
        struct cirrusfb_info *cinfo = info->par;
        int err;
-       enum cirrus_board btype;
-
-       btype = cinfo->btype;
 
        /* sanity checks */
-       assert(btype != BT_NONE);
+       assert(cinfo->btype != BT_NONE);
 
        /* set all the vital stuff */
        cirrusfb_set_fbinfo(info);
@@ -2132,7 +2056,7 @@ static int __devinit cirrusfb_register(struct fb_info *info)
 
        info->var.activate = FB_ACTIVATE_NOW;
 
-       err = cirrusfb_decode_var(&info->var, &cinfo->currentmode, info);
+       err = cirrusfb_check_var(&info->var, info);
        if (err < 0) {
                /* should never happen */
                dev_dbg(info->device,
@@ -2151,8 +2075,6 @@ static int __devinit cirrusfb_register(struct fb_info *info)
 
 err_dealloc_cmap:
        fb_dealloc_cmap(&info->cmap);
-       cinfo->unmap(info);
-       framebuffer_release(info);
        return err;
 }
 
@@ -2174,7 +2096,6 @@ static int __devinit cirrusfb_pci_register(struct pci_dev *pdev,
 {
        struct cirrusfb_info *cinfo;
        struct fb_info *info;
-       enum cirrus_board btype;
        unsigned long board_addr, board_size;
        int ret;
 
@@ -2188,15 +2109,15 @@ static int __devinit cirrusfb_pci_register(struct pci_dev *pdev,
        if (!info) {
                printk(KERN_ERR "cirrusfb: could not allocate memory\n");
                ret = -ENOMEM;
-               goto err_disable;
+               goto err_out;
        }
 
        cinfo = info->par;
-       cinfo->btype = btype = (enum cirrus_board) ent->driver_data;
+       cinfo->btype = (enum cirrus_board) ent->driver_data;
 
        dev_dbg(info->device,
                " Found PCI device, base address 0 is 0x%Lx, btype set to %d\n",
-               (unsigned long long)pdev->resource[0].start, btype);
+               (unsigned long long)pdev->resource[0].start,  cinfo->btype);
        dev_dbg(info->device, " base address 1 is 0x%Lx\n",
                (unsigned long long)pdev->resource[1].start);
 
@@ -2219,7 +2140,7 @@ static int __devinit cirrusfb_pci_register(struct pci_dev *pdev,
        dev_dbg(info->device, "Board address: 0x%lx, register address: 0x%lx\n",
                board_addr, info->fix.mmio_start);
 
-       board_size = (btype == BT_GD5480) ?
+       board_size = (cinfo->btype == BT_GD5480) ?
                32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase);
 
        ret = pci_request_regions(pdev, "cirrusfb");
@@ -2255,10 +2176,11 @@ static int __devinit cirrusfb_pci_register(struct pci_dev *pdev,
        pci_set_drvdata(pdev, info);
 
        ret = cirrusfb_register(info);
-       if (ret)
-               iounmap(info->screen_base);
-       return ret;
+       if (!ret)
+               return 0;
 
+       pci_set_drvdata(pdev, NULL);
+       iounmap(info->screen_base);
 err_release_legacy:
        if (release_io_ports)
                release_region(0x3C0, 32);
@@ -2268,10 +2190,9 @@ err_release_regions:
 #endif
        pci_release_regions(pdev);
 err_release_fb:
-       if (cinfo->laguna_mmio == NULL)
+       if (cinfo->laguna_mmio != NULL)
                iounmap(cinfo->laguna_mmio);
        framebuffer_release(info);
-err_disable:
 err_out:
        return ret;
 }
@@ -2389,19 +2310,21 @@ static int __devinit cirrusfb_zorro_register(struct zorro_dev *z,
 
        zorro_set_drvdata(z, info);
 
+       /* MCLK select etc. */
+       if (cirrusfb_board_info[btype].init_sr1f)
+               vga_wseq(cinfo->regbase, CL_SEQR1F,
+                        cirrusfb_board_info[btype].sr1f);
+
        ret = cirrusfb_register(info);
-       if (ret) {
-               if (btype == BT_PICASSO4) {
-                       iounmap(info->screen_base);
-                       iounmap(cinfo->regbase - 0x600000);
-               } else if (board_addr > 0x01000000)
-                       iounmap(info->screen_base);
-       }
-       return ret;
+       if (!ret)
+               return 0;
+
+       if (btype == BT_PICASSO4 || board_addr > 0x01000000)
+               iounmap(info->screen_base);
 
 err_unmap_regbase:
-       /* Parental advisory: explicit hack */
-       iounmap(cinfo->regbase - 0x600000);
+       if (btype == BT_PICASSO4)
+               iounmap(cinfo->regbase - 0x600000);
 err_release_region:
        release_region(board_addr, board_size);
 err_release_fb:
@@ -2425,27 +2348,6 @@ static struct zorro_driver cirrusfb_zorro_driver = {
 };
 #endif /* CONFIG_ZORRO */
 
-static int __init cirrusfb_init(void)
-{
-       int error = 0;
-
-#ifndef MODULE
-       char *option = NULL;
-
-       if (fb_get_options("cirrusfb", &option))
-               return -ENODEV;
-       cirrusfb_setup(option);
-#endif
-
-#ifdef CONFIG_ZORRO
-       error |= zorro_register_driver(&cirrusfb_zorro_driver);
-#endif
-#ifdef CONFIG_PCI
-       error |= pci_register_driver(&cirrusfb_pci_driver);
-#endif
-       return error;
-}
-
 #ifndef MODULE
 static int __init cirrusfb_setup(char *options)
 {
@@ -2477,6 +2379,27 @@ MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>");
 MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
 MODULE_LICENSE("GPL");
 
+static int __init cirrusfb_init(void)
+{
+       int error = 0;
+
+#ifndef MODULE
+       char *option = NULL;
+
+       if (fb_get_options("cirrusfb", &option))
+               return -ENODEV;
+       cirrusfb_setup(option);
+#endif
+
+#ifdef CONFIG_ZORRO
+       error |= zorro_register_driver(&cirrusfb_zorro_driver);
+#endif
+#ifdef CONFIG_PCI
+       error |= pci_register_driver(&cirrusfb_pci_driver);
+#endif
+       return error;
+}
+
 static void __exit cirrusfb_exit(void)
 {
 #ifdef CONFIG_PCI
@@ -2567,6 +2490,8 @@ static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
 {
        unsigned char dummy;
 
+       if (is_laguna(cinfo))
+               return;
        if (cinfo->btype == BT_PICASSO) {
                /* Klaus' hint for correct access to HDR on some boards */
                /* first write 0 to pixel mask (3c6) */
@@ -2634,7 +2559,8 @@ static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned ch
        vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
 
        if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
-           cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
+           cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 ||
+           cinfo->btype == BT_SD64 || is_laguna(cinfo)) {
                /* but DAC data register IS, at least for Picasso II */
                if (cinfo->btype == BT_PICASSO)
                        data += 0xfff;
@@ -2681,9 +2607,8 @@ static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned ch
 /* FIXME: use interrupts instead */
 static void cirrusfb_WaitBLT(u8 __iomem *regbase)
 {
-       /* now busy-wait until we're done */
        while (vga_rgfx(regbase, CL_GR31) & 0x08)
-               /* do nothing */ ;
+               cpu_relax();
 }
 
 /*******************************************************************
@@ -2692,58 +2617,12 @@ static void cirrusfb_WaitBLT(u8 __iomem *regbase)
        perform accelerated "scrolling"
 ********************************************************************/
 
-static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
-                           u_short curx, u_short cury,
-                           u_short destx, u_short desty,
-                           u_short width, u_short height,
-                           u_short line_length)
-{
-       u_short nwidth, nheight;
-       u_long nsrc, ndest;
-       u_char bltmode;
-
-       nwidth = width - 1;
-       nheight = height - 1;
-
-       bltmode = 0x00;
-       /* if source adr < dest addr, do the Blt backwards */
-       if (cury <= desty) {
-               if (cury == desty) {
-                       /* if src and dest are on the same line, check x */
-                       if (curx < destx)
-                               bltmode |= 0x01;
-               } else
-                       bltmode |= 0x01;
-       }
-       if (!bltmode) {
-               /* standard case: forward blitting */
-               nsrc = (cury * line_length) + curx;
-               ndest = (desty * line_length) + destx;
-       } else {
-               /* this means start addresses are at the end,
-                * counting backwards
-                */
-               nsrc = cury * line_length + curx +
-                       nheight * line_length + nwidth;
-               ndest = desty * line_length + destx +
-                       nheight * line_length + nwidth;
-       }
-
-       /*
-          run-down of registers to be programmed:
-          destination pitch
-          source pitch
-          BLT width/height
-          source start
-          destination start
-          BLT mode
-          BLT ROP
-          VGA_GFX_SR_VALUE / VGA_GFX_SR_ENABLE: "fill color"
-          start/stop
-        */
-
-       cirrusfb_WaitBLT(regbase);
+static void cirrusfb_set_blitter(u8 __iomem *regbase,
+                           u_short nwidth, u_short nheight,
+                           u_long nsrc, u_long ndest,
+                           u_short bltmode, u_short line_length)
 
+{
        /* pitch: set to line_length */
        /* dest pitch low */
        vga_wgfx(regbase, CL_GR24, line_length & 0xff);
@@ -2793,82 +2672,88 @@ static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
 }
 
 /*******************************************************************
-       cirrusfb_RectFill()
+       cirrusfb_BitBLT()
 
-       perform accelerated rectangle fill
+       perform accelerated "scrolling"
 ********************************************************************/
 
-static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
-                    u_short x, u_short y, u_short width, u_short height,
-                    u_char color, u_short line_length)
+static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
+                           u_short curx, u_short cury,
+                           u_short destx, u_short desty,
+                           u_short width, u_short height,
+                           u_short line_length)
 {
-       u_short nwidth, nheight;
-       u_long ndest;
-       u_char op;
-
-       nwidth = width - 1;
-       nheight = height - 1;
+       u_short nwidth = width - 1;
+       u_short nheight = height - 1;
+       u_long nsrc, ndest;
+       u_char bltmode;
 
-       ndest = (y * line_length) + x;
+       bltmode = 0x00;
+       /* if source adr < dest addr, do the Blt backwards */
+       if (cury <= desty) {
+               if (cury == desty) {
+                       /* if src and dest are on the same line, check x */
+                       if (curx < destx)
+                               bltmode |= 0x01;
+               } else
+                       bltmode |= 0x01;
+       }
+       /* standard case: forward blitting */
+       nsrc = (cury * line_length) + curx;
+       ndest = (desty * line_length) + destx;
+       if (bltmode) {
+               /* this means start addresses are at the end,
+                * counting backwards
+                */
+               nsrc += nheight * line_length + nwidth;
+               ndest += nheight * line_length + nwidth;
+       }
 
        cirrusfb_WaitBLT(regbase);
 
-       /* pitch: set to line_length */
-       vga_wgfx(regbase, CL_GR24, line_length & 0xff); /* dest pitch low */
-       vga_wgfx(regbase, CL_GR25, line_length >> 8);   /* dest pitch hi */
-       vga_wgfx(regbase, CL_GR26, line_length & 0xff); /* source pitch low */
-       vga_wgfx(regbase, CL_GR27, line_length >> 8);   /* source pitch hi */
+       cirrusfb_set_blitter(regbase, nwidth, nheight,
+                           nsrc, ndest, bltmode, line_length);
+}
 
-       /* BLT width: actual number of pixels - 1 */
-       vga_wgfx(regbase, CL_GR20, nwidth & 0xff);      /* BLT width low */
-       vga_wgfx(regbase, CL_GR21, nwidth >> 8);        /* BLT width hi */
+/*******************************************************************
+       cirrusfb_RectFill()
 
-       /* BLT height: actual number of lines -1 */
-       vga_wgfx(regbase, CL_GR22, nheight & 0xff);     /* BLT height low */
-       vga_wgfx(regbase, CL_GR23, nheight >> 8);       /* BLT width hi */
+       perform accelerated rectangle fill
+********************************************************************/
 
-       /* BLT destination */
-       /* BLT dest low */
-       vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
-       /* BLT dest mid */
-       vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
-       /* BLT dest hi */
-       vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
+static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
+                    u_short x, u_short y, u_short width, u_short height,
+                    u32 fg_color, u32 bg_color, u_short line_length,
+                    u_char blitmode)
+{
+       u_long ndest = (y * line_length) + x;
+       u_char op;
 
-       /* BLT source: set to 0 (is a dummy here anyway) */
-       vga_wgfx(regbase, CL_GR2C, 0x00);       /* BLT src low */
-       vga_wgfx(regbase, CL_GR2D, 0x00);       /* BLT src mid */
-       vga_wgfx(regbase, CL_GR2E, 0x00);       /* BLT src hi */
+       cirrusfb_WaitBLT(regbase);
 
        /* This is a ColorExpand Blt, using the */
        /* same color for foreground and background */
-       vga_wgfx(regbase, VGA_GFX_SR_VALUE, color);     /* foreground color */
-       vga_wgfx(regbase, VGA_GFX_SR_ENABLE, color);    /* background color */
-
-       op = 0xc0;
-       if (bits_per_pixel == 16) {
-               vga_wgfx(regbase, CL_GR10, color);      /* foreground color */
-               vga_wgfx(regbase, CL_GR11, color);      /* background color */
-               op = 0x50;
-               op = 0xd0;
-       } else if (bits_per_pixel == 32) {
-               vga_wgfx(regbase, CL_GR10, color);      /* foreground color */
-               vga_wgfx(regbase, CL_GR11, color);      /* background color */
-               vga_wgfx(regbase, CL_GR12, color);      /* foreground color */
-               vga_wgfx(regbase, CL_GR13, color);      /* background color */
-               vga_wgfx(regbase, CL_GR14, 0);  /* foreground color */
-               vga_wgfx(regbase, CL_GR15, 0);  /* background color */
-               op = 0x50;
-               op = 0xf0;
-       }
-       /* BLT mode: color expand, Enable 8x8 copy (faster?) */
-       vga_wgfx(regbase, CL_GR30, op); /* BLT mode */
-
-       /* BLT ROP: SrcCopy */
-       vga_wgfx(regbase, CL_GR32, 0x0d);       /* BLT ROP */
-
-       /* and finally: GO! */
-       vga_wgfx(regbase, CL_GR31, 0x02);       /* BLT Start/status */
+       vga_wgfx(regbase, VGA_GFX_SR_VALUE, bg_color);
+       vga_wgfx(regbase, VGA_GFX_SR_ENABLE, fg_color);
+
+       op = 0x80;
+       if (bits_per_pixel >= 16) {
+               vga_wgfx(regbase, CL_GR10, bg_color >> 8);
+               vga_wgfx(regbase, CL_GR11, fg_color >> 8);
+               op = 0x90;
+       }
+       if (bits_per_pixel >= 24) {
+               vga_wgfx(regbase, CL_GR12, bg_color >> 16);
+               vga_wgfx(regbase, CL_GR13, fg_color >> 16);
+               op = 0xa0;
+       }
+       if (bits_per_pixel == 32) {
+               vga_wgfx(regbase, CL_GR14, bg_color >> 24);
+               vga_wgfx(regbase, CL_GR15, fg_color >> 24);
+               op = 0xb0;
+       }
+       cirrusfb_set_blitter(regbase, width - 1, height - 1,
+                           0, ndest, op | blitmode, line_length);
 }
 
 /**************************************************************************