* problems with architectures I can't test on (because I don't have one,
* such as the Alpha based systems) which happen to give faults for
* non-aligned memory accesses, care was taken to align this structure
- * in a way that gauranteed all accesses larger than 8 bits were aligned
+ * in a way that guaranteed all accesses larger than 8 bits were aligned
* on the appropriate boundary. It's also organized to try and be more
* cache line efficient. Be careful when changing this lest you might hurt
* overall performance and bring down the wrath of the masses.
* the card's registers in a hex dump format tailored to each model of
* controller.
*
- * NOTE: THE CONTROLLER IS LEFT IN AN UNUSEABLE STATE BY THIS OPTION.
+ * NOTE: THE CONTROLLER IS LEFT IN AN UNUSABLE STATE BY THIS OPTION.
* YOU CANNOT BOOT UP WITH THIS OPTION, IT IS FOR DEBUGGING PURPOSES
* ONLY
*/
{
pci_unmap_single(p->pdev,
le32_to_cpu(scb->sg_list[0].address),
- sizeof(cmd->sense_buffer),
+ SCSI_SENSE_BUFFERSIZE,
PCI_DMA_FROMDEVICE);
}
if (scb->flags & SCB_RECOVERY_SCB)
aic_dev->r_total++;
ptr = aic_dev->r_bins;
}
- if(cmd->device->simple_tags && cmd->request->cmd_flags & REQ_HARDBARRIER)
- {
- aic_dev->barrier_total++;
- if(scb->tag_action == MSG_ORDERED_Q_TAG)
- aic_dev->ordered_total++;
- }
x = scb->sg_length;
x >>= 10;
for(i=0; i<6; i++)
/* Turn off the bus' current operations, after all, we shouldn't have any
* valid commands left to cause a RSELI and SELO once we've tossed the
* bus away with this reset, so we might as well shut down the sequencer
- * until the bus is restarted as oppossed to saving the current settings
+ * until the bus is restarted as opposed to saving the current settings
* and restoring them (which makes no sense to me). */
/* Turn on the bus reset. */
aic_dev->max_q_depth = aic_dev->temp_q_depth = 1;
/*
* We set this command up as a bus device reset. However, we have
- * to clear the tag type as it's causing us problems. We shouldnt
+ * to clear the tag type as it's causing us problems. We shouldn't
* have to worry about any other commands being active, since if
* the device is refusing tagged commands, this should be the
* first tagged command sent to the device, however, we do have
sizeof(generic_sense));
scb->sense_cmd[1] = (cmd->device->lun << 5);
- scb->sense_cmd[4] = sizeof(cmd->sense_buffer);
+ scb->sense_cmd[4] = SCSI_SENSE_BUFFERSIZE;
scb->sg_list[0].length =
- cpu_to_le32(sizeof(cmd->sense_buffer));
+ cpu_to_le32(SCSI_SENSE_BUFFERSIZE);
scb->sg_list[0].address =
cpu_to_le32(pci_map_single(p->pdev, cmd->sense_buffer,
- sizeof(cmd->sense_buffer),
+ SCSI_SENSE_BUFFERSIZE,
PCI_DMA_FROMDEVICE));
/*
hscb->residual_data_count[2] = 0;
scb->sg_count = hscb->SG_segment_count = 1;
- scb->sg_length = sizeof(cmd->sense_buffer);
+ scb->sg_length = SCSI_SENSE_BUFFERSIZE;
scb->tag_action = 0;
scb->flags |= SCB_SENSE;
/*
unsigned long cpu_flags;
struct aic7xxx_host *p;
- p = (struct aic7xxx_host *)dev_id;
+ p = dev_id;
if(!p)
return IRQ_NONE;
spin_lock_irqsave(p->host->host_lock, cpu_flags);
}
/*
- * We are commited now, everything has been checked and this card
+ * We are committed now, everything has been checked and this card
* has been found, now we just set it up
*/
* 2: All PCI controllers with BIOS_ENABLED next, according to BIOS
* address, going from lowest to highest.
* 3: Remaining VLB/EISA controllers going in slot order.
- * 4: Remaining PCI controllers, going in PCI device order (reversable)
+ * 4: Remaining PCI controllers, going in PCI device order (reversible)
*/
{
struct aic_dev_data *aic_dev = cmd->device->hostdata;
struct scsi_device *sdptr = cmd->device;
unsigned char tindex = TARGET_INDEX(cmd);
- struct request *req = cmd->request;
int use_sg;
mask = (0x01 << tindex);
/* We always force TEST_UNIT_READY to untagged */
if (cmd->cmnd[0] != TEST_UNIT_READY && sdptr->simple_tags)
{
- if (req->cmd_flags & REQ_HARDBARRIER)
- {
- if(sdptr->ordered_tags)
- {
- hscb->control |= MSG_ORDERED_Q_TAG;
- scb->tag_action = MSG_ORDERED_Q_TAG;
- }
- }
- else
- {
- hscb->control |= MSG_SIMPLE_Q_TAG;
- scb->tag_action = MSG_SIMPLE_Q_TAG;
- }
+ hscb->control |= MSG_SIMPLE_Q_TAG;
+ scb->tag_action = MSG_SIMPLE_Q_TAG;
}
}
if ( !(aic_dev->dtr_pending) &&
* Description:
* Queue a SCB to the controller.
*-F*************************************************************************/
-static int aic7xxx_queue(struct scsi_cmnd *cmd, void (*fn)(struct scsi_cmnd *))
+static int aic7xxx_queue_lck(struct scsi_cmnd *cmd, void (*fn)(struct scsi_cmnd *))
{
struct aic7xxx_host *p;
struct aic7xxx_scb *scb;
aic7xxx_position(cmd) = scb->hscb->tag;
cmd->scsi_done = fn;
cmd->result = DID_OK;
- memset(cmd->sense_buffer, 0, sizeof(cmd->sense_buffer));
aic7xxx_error(cmd) = DID_OK;
aic7xxx_status(cmd) = 0;
cmd->host_scribble = NULL;
return (0);
}
+static DEF_SCSI_QCMD(aic7xxx_queue)
+
/*+F*************************************************************************
* Function:
* aic7xxx_bus_device_reset
.max_sectors = 2048,
.cmd_per_lun = 3,
.use_clustering = ENABLE_CLUSTERING,
- .use_sg_chaining = ENABLE_SG_CHAINING,
};
#include "scsi_module.c"