Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-2.6.git] / drivers / net / wireless / b43 / phy_lp.c
index 7e70c07..daec1d9 100644 (file)
@@ -1,9 +1,10 @@
 /*
 
   Broadcom B43 wireless driver
-  IEEE 802.11g LP-PHY driver
+  IEEE 802.11a/g LP-PHY driver
 
   Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
+  Copyright (c) 2009 Gábor Stefanik <netrolller.3d@gmail.com>
 
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
@@ -22,6 +23,8 @@
 
 */
 
+#include <linux/slab.h>
+
 #include "b43.h"
 #include "main.h"
 #include "phy_lp.h"
@@ -44,7 +47,7 @@ static inline u16 channel2freq_lp(u8 channel)
 static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
 {
        if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
-               return 7; //FIXME temporary - channel 1 is broken
+               return 1;
        return 36;
 }
 
@@ -66,6 +69,7 @@ static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
        struct b43_phy_lp *lpphy = phy->lp;
 
        memset(lpphy, 0, sizeof(*lpphy));
+       lpphy->antenna = B43_ANTENNA_DEFAULT;
 
        //TODO
 }
@@ -78,35 +82,42 @@ static void b43_lpphy_op_free(struct b43_wldev *dev)
        dev->phy.lp = NULL;
 }
 
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/LP/ReadBandSrom */
 static void lpphy_read_band_sprom(struct b43_wldev *dev)
 {
+       struct ssb_sprom *sprom = dev->dev->bus_sprom;
        struct b43_phy_lp *lpphy = dev->phy.lp;
-       struct ssb_bus *bus = dev->dev->bus;
        u16 cckpo, maxpwr;
        u32 ofdmpo;
        int i;
 
        if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
-               lpphy->tx_isolation_med_band = bus->sprom.tri2g;
-               lpphy->bx_arch = bus->sprom.bxa2g;
-               lpphy->rx_pwr_offset = bus->sprom.rxpo2g;
-               lpphy->rssi_vf = bus->sprom.rssismf2g;
-               lpphy->rssi_vc = bus->sprom.rssismc2g;
-               lpphy->rssi_gs = bus->sprom.rssisav2g;
-               lpphy->txpa[0] = bus->sprom.pa0b0;
-               lpphy->txpa[1] = bus->sprom.pa0b1;
-               lpphy->txpa[2] = bus->sprom.pa0b2;
-               maxpwr = bus->sprom.maxpwr_bg;
+               lpphy->tx_isolation_med_band = sprom->tri2g;
+               lpphy->bx_arch = sprom->bxa2g;
+               lpphy->rx_pwr_offset = sprom->rxpo2g;
+               lpphy->rssi_vf = sprom->rssismf2g;
+               lpphy->rssi_vc = sprom->rssismc2g;
+               lpphy->rssi_gs = sprom->rssisav2g;
+               lpphy->txpa[0] = sprom->pa0b0;
+               lpphy->txpa[1] = sprom->pa0b1;
+               lpphy->txpa[2] = sprom->pa0b2;
+               maxpwr = sprom->maxpwr_bg;
                lpphy->max_tx_pwr_med_band = maxpwr;
-               cckpo = bus->sprom.cck2gpo;
-               ofdmpo = bus->sprom.ofdm2gpo;
+               cckpo = sprom->cck2gpo;
+               /*
+                * We don't read SPROM's opo as specs say. On rev8 SPROMs
+                * opo == ofdm2gpo and we don't know any SSB with LP-PHY
+                * and SPROM rev below 8.
+                */
+               B43_WARN_ON(sprom->revision < 8);
+               ofdmpo = sprom->ofdm2gpo;
                if (cckpo) {
                        for (i = 0; i < 4; i++) {
                                lpphy->tx_max_rate[i] =
                                        maxpwr - (ofdmpo & 0xF) * 2;
                                ofdmpo >>= 4;
                        }
-                       ofdmpo = bus->sprom.ofdm2gpo;
+                       ofdmpo = sprom->ofdm2gpo;
                        for (i = 4; i < 15; i++) {
                                lpphy->tx_max_rate[i] =
                                        maxpwr - (ofdmpo & 0xF) * 2;
@@ -120,39 +131,39 @@ static void lpphy_read_band_sprom(struct b43_wldev *dev)
                                lpphy->tx_max_rate[i] = maxpwr - ofdmpo;
                }
        } else { /* 5GHz */
-               lpphy->tx_isolation_low_band = bus->sprom.tri5gl;
-               lpphy->tx_isolation_med_band = bus->sprom.tri5g;
-               lpphy->tx_isolation_hi_band = bus->sprom.tri5gh;
-               lpphy->bx_arch = bus->sprom.bxa5g;
-               lpphy->rx_pwr_offset = bus->sprom.rxpo5g;
-               lpphy->rssi_vf = bus->sprom.rssismf5g;
-               lpphy->rssi_vc = bus->sprom.rssismc5g;
-               lpphy->rssi_gs = bus->sprom.rssisav5g;
-               lpphy->txpa[0] = bus->sprom.pa1b0;
-               lpphy->txpa[1] = bus->sprom.pa1b1;
-               lpphy->txpa[2] = bus->sprom.pa1b2;
-               lpphy->txpal[0] = bus->sprom.pa1lob0;
-               lpphy->txpal[1] = bus->sprom.pa1lob1;
-               lpphy->txpal[2] = bus->sprom.pa1lob2;
-               lpphy->txpah[0] = bus->sprom.pa1hib0;
-               lpphy->txpah[1] = bus->sprom.pa1hib1;
-               lpphy->txpah[2] = bus->sprom.pa1hib2;
-               maxpwr = bus->sprom.maxpwr_al;
-               ofdmpo = bus->sprom.ofdm5glpo;
+               lpphy->tx_isolation_low_band = sprom->tri5gl;
+               lpphy->tx_isolation_med_band = sprom->tri5g;
+               lpphy->tx_isolation_hi_band = sprom->tri5gh;
+               lpphy->bx_arch = sprom->bxa5g;
+               lpphy->rx_pwr_offset = sprom->rxpo5g;
+               lpphy->rssi_vf = sprom->rssismf5g;
+               lpphy->rssi_vc = sprom->rssismc5g;
+               lpphy->rssi_gs = sprom->rssisav5g;
+               lpphy->txpa[0] = sprom->pa1b0;
+               lpphy->txpa[1] = sprom->pa1b1;
+               lpphy->txpa[2] = sprom->pa1b2;
+               lpphy->txpal[0] = sprom->pa1lob0;
+               lpphy->txpal[1] = sprom->pa1lob1;
+               lpphy->txpal[2] = sprom->pa1lob2;
+               lpphy->txpah[0] = sprom->pa1hib0;
+               lpphy->txpah[1] = sprom->pa1hib1;
+               lpphy->txpah[2] = sprom->pa1hib2;
+               maxpwr = sprom->maxpwr_al;
+               ofdmpo = sprom->ofdm5glpo;
                lpphy->max_tx_pwr_low_band = maxpwr;
                for (i = 4; i < 12; i++) {
                        lpphy->tx_max_ratel[i] = maxpwr - (ofdmpo & 0xF) * 2;
                        ofdmpo >>= 4;
                }
-               maxpwr = bus->sprom.maxpwr_a;
-               ofdmpo = bus->sprom.ofdm5gpo;
+               maxpwr = sprom->maxpwr_a;
+               ofdmpo = sprom->ofdm5gpo;
                lpphy->max_tx_pwr_med_band = maxpwr;
                for (i = 4; i < 12; i++) {
                        lpphy->tx_max_rate[i] = maxpwr - (ofdmpo & 0xF) * 2;
                        ofdmpo >>= 4;
                }
-               maxpwr = bus->sprom.maxpwr_ah;
-               ofdmpo = bus->sprom.ofdm5ghpo;
+               maxpwr = sprom->maxpwr_ah;
+               ofdmpo = sprom->ofdm5ghpo;
                lpphy->max_tx_pwr_hi_band = maxpwr;
                for (i = 4; i < 12; i++) {
                        lpphy->tx_max_rateh[i] = maxpwr - (ofdmpo & 0xF) * 2;
@@ -182,8 +193,8 @@ static void lpphy_adjust_gain_table(struct b43_wldev *dev, u32 freq)
        temp[1] = temp[0] + 0x1000;
        temp[2] = temp[0] + 0x2000;
 
-       b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp);
        b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), 3, temp);
+       b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp);
 }
 
 static void lpphy_table_init(struct b43_wldev *dev)
@@ -203,7 +214,8 @@ static void lpphy_table_init(struct b43_wldev *dev)
 
 static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
 {
-       struct ssb_bus *bus = dev->dev->bus;
+       struct ssb_bus *bus = dev->dev->sdev->bus;
+       struct ssb_sprom *sprom = dev->dev->bus_sprom;
        struct b43_phy_lp *lpphy = dev->phy.lp;
        u16 tmp, tmp2;
 
@@ -223,37 +235,33 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
        b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0x0006);
        b43_phy_mask(dev, B43_LPPHY_RX_RADIO_CTL, 0xFFFE);
        b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x0005);
-       b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC10, 0x0180);
-       b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x3800);
+       b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0x0180);
+       b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x3C00);
        b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFFF0, 0x0005);
        b43_phy_maskset(dev, B43_LPPHY_GAIN_MISMATCH_LIMIT, 0xFFC0, 0x001A);
        b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0x00B3);
        b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
        b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB,
                        0xFF00, lpphy->rx_pwr_offset);
-       if ((bus->sprom.boardflags_lo & B43_BFL_FEM) &&
+       if ((sprom->boardflags_lo & B43_BFL_FEM) &&
           ((b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
-          (bus->sprom.boardflags_hi & B43_BFH_PAREF))) {
-               /* TODO:
-                * Set the LDO voltage to 0x0028 - FIXME: What is this?
-                * Call sb_pmu_set_ldo_voltage with 4 and the LDO voltage
-                *      as arguments
-                * Call sb_pmu_paref_ldo_enable with argument TRUE
-                */
+          (sprom->boardflags_hi & B43_BFH_PAREF))) {
+               ssb_pmu_set_ldo_voltage(&bus->chipco, LDO_PAREF, 0x28);
+               ssb_pmu_set_ldo_paref(&bus->chipco, true);
                if (dev->phy.rev == 0) {
                        b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
                                        0xFFCF, 0x0010);
                }
                b43_lptab_write(dev, B43_LPTAB16(11, 7), 60);
        } else {
-               //TODO: Call ssb_pmu_paref_ldo_enable with argument FALSE
+               ssb_pmu_set_ldo_paref(&bus->chipco, false);
                b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
                                0xFFCF, 0x0020);
                b43_lptab_write(dev, B43_LPTAB16(11, 7), 100);
        }
        tmp = lpphy->rssi_vf | lpphy->rssi_vc << 4 | 0xA000;
        b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, tmp);
-       if (bus->sprom.boardflags_hi & B43_BFH_RSSIINV)
+       if (sprom->boardflags_hi & B43_BFH_RSSIINV)
                b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x0AAA);
        else
                b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x02AA);
@@ -261,7 +269,7 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
        b43_phy_maskset(dev, B43_LPPHY_RX_RADIO_CTL,
                        0xFFF9, (lpphy->bx_arch << 1));
        if (dev->phy.rev == 1 &&
-          (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) {
+          (sprom->boardflags_hi & B43_BFH_FEM_BT)) {
                b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
                b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
                b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
@@ -279,8 +287,8 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
                b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
                b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
        } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
-                 (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) &&
-                 (bus->sprom.boardflags_lo & B43_BFL_FEM))) {
+                 (dev->dev->board_type == 0x048A) || ((dev->phy.rev == 0) &&
+                 (sprom->boardflags_lo & B43_BFL_FEM))) {
                b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
                b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
                b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
@@ -290,7 +298,7 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
                b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
                b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
        } else if (dev->phy.rev == 1 ||
-                 (bus->sprom.boardflags_lo & B43_BFL_FEM)) {
+                 (sprom->boardflags_lo & B43_BFL_FEM)) {
                b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
                b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
                b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
@@ -309,15 +317,15 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
                b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
                b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
        }
-       if (dev->phy.rev == 1 && (bus->sprom.boardflags_hi & B43_BFH_PAREF)) {
+       if (dev->phy.rev == 1 && (sprom->boardflags_hi & B43_BFH_PAREF)) {
                b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
                b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
                b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
                b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
        }
-       if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) &&
-           (bus->chip_id == 0x5354) &&
-           (bus->chip_package == SSB_CHIPPACK_BCM4712S)) {
+       if ((sprom->boardflags_hi & B43_BFH_FEM_BT) &&
+           (dev->dev->chip_id == 0x5354) &&
+           (dev->dev->chip_pkg == SSB_CHIPPACK_BCM4712S)) {
                b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
                b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
                b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
@@ -340,11 +348,11 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
        if (dev->phy.rev == 1) {
                tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
                tmp2 = (tmp & 0x03E0) >> 5;
-               tmp2 |= tmp << 5;
+               tmp2 |= tmp2 << 5;
                b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
-               tmp = b43_phy_read(dev, B43_LPPHY_OFDMSYNCTHRESH0);
+               tmp = b43_phy_read(dev, B43_LPPHY_GAINDIRECTMISMATCH);
                tmp2 = (tmp & 0x1F00) >> 8;
-               tmp2 |= tmp << 5;
+               tmp2 |= tmp2 << 5;
                b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
                tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
                tmp2 = tmp & 0x00FF;
@@ -405,7 +413,6 @@ static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
 
 static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
 {
-       struct ssb_bus *bus = dev->dev->bus;
        struct b43_phy_lp *lpphy = dev->phy.lp;
 
        b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
@@ -425,7 +432,7 @@ static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
        b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
        b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
        b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
-       if (bus->boardinfo.rev >= 0x18) {
+       if (dev->dev->board_rev >= 0x18) {
                b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC);
                b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14);
        } else {
@@ -442,7 +449,7 @@ static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
        b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0xA0);
        b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
        b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
-       if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
+       if ((dev->dev->chip_id == 0x4325) && (dev->dev->chip_rev == 0)) {
                b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
                b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
        } else {
@@ -460,7 +467,7 @@ static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
        b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
        b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
 
-       if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
+       if ((dev->dev->chip_id == 0x4325) && (dev->dev->chip_rev == 0)) {
                b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
                b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
        }
@@ -485,7 +492,7 @@ static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
                      0x2000 | ((u16)lpphy->rssi_gs << 10) |
                      ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
 
-       if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
+       if ((dev->dev->chip_id == 0x4325) && (dev->dev->chip_rev == 0)) {
                b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C);
                b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800);
                b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400);
@@ -512,7 +519,7 @@ struct b2062_freqdata {
 static void lpphy_2062_init(struct b43_wldev *dev)
 {
        struct b43_phy_lp *lpphy = dev->phy.lp;
-       struct ssb_bus *bus = dev->dev->bus;
+       struct ssb_bus *bus = dev->dev->sdev->bus;
        u32 crystalfreq, tmp, ref;
        unsigned int i;
        const struct b2062_freqdata *fd = NULL;
@@ -690,7 +697,7 @@ static void lpphy_radio_init(struct b43_wldev *dev)
                lpphy_sync_stx(dev);
                b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
                b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
-               if (dev->dev->bus->chip_id == 0x4325) {
+               if (dev->dev->chip_id == 0x4325) {
                        // TODO SSB PMU recalibration
                }
        }
@@ -754,14 +761,20 @@ static void lpphy_clear_deaf(struct b43_wldev *dev, bool user)
        }
 }
 
+static void lpphy_set_trsw_over(struct b43_wldev *dev, bool tx, bool rx)
+{
+       u16 trsw = (tx << 1) | rx;
+       b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, trsw);
+       b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
+}
+
 static void lpphy_disable_crs(struct b43_wldev *dev, bool user)
 {
        lpphy_set_deaf(dev, user);
-       b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x1);
-       b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
+       lpphy_set_trsw_over(dev, false, true);
        b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB);
        b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4);
-       b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFF7);
+       b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFF7);
        b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
        b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x10);
        b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
@@ -793,6 +806,60 @@ static void lpphy_restore_crs(struct b43_wldev *dev, bool user)
 
 struct lpphy_tx_gains { u16 gm, pga, pad, dac; };
 
+static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
+{
+       b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
+       b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
+       b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
+       if (dev->phy.rev >= 2) {
+               b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
+               if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
+                       b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
+                       b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7);
+               }
+       } else {
+               b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
+       }
+}
+
+static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
+{
+       b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
+       b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
+       b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
+       if (dev->phy.rev >= 2) {
+               b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
+               if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
+                       b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
+                       b43_phy_set(dev, B43_PHY_OFDM(0xE5), 0x8);
+               }
+       } else {
+               b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
+       }
+}
+
+static void lpphy_disable_tx_gain_override(struct b43_wldev *dev)
+{
+       if (dev->phy.rev < 2)
+               b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
+       else {
+               b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F);
+               b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF);
+       }
+       b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF);
+}
+
+static void lpphy_enable_tx_gain_override(struct b43_wldev *dev)
+{
+       if (dev->phy.rev < 2)
+               b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
+       else {
+               b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x80);
+               b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x4000);
+       }
+       b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 0x40);
+}
+
 static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev)
 {
        struct lpphy_tx_gains gains;
@@ -822,6 +889,17 @@ static void lpphy_set_dac_gain(struct b43_wldev *dev, u16 dac)
        b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl);
 }
 
+static u16 lpphy_get_pa_gain(struct b43_wldev *dev)
+{
+       return b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x7F;
+}
+
+static void lpphy_set_pa_gain(struct b43_wldev *dev, u16 gain)
+{
+       b43_phy_maskset(dev, B43_PHY_OFDM(0xFB), 0xE03F, gain << 6);
+       b43_phy_maskset(dev, B43_PHY_OFDM(0xFD), 0x80FF, gain << 8);
+}
+
 static void lpphy_set_tx_gains(struct b43_wldev *dev,
                               struct lpphy_tx_gains gains)
 {
@@ -832,25 +910,22 @@ static void lpphy_set_tx_gains(struct b43_wldev *dev,
                b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
                                0xF800, rf_gain);
        } else {
-               pa_gain = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x1FC0;
-               pa_gain <<= 2;
+               pa_gain = lpphy_get_pa_gain(dev);
                b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
                              (gains.pga << 8) | gains.gm);
+               /*
+                * SPEC FIXME The spec calls for (pa_gain << 8) here, but that
+                * conflicts with the spec for set_pa_gain! Vendor driver bug?
+                */
                b43_phy_maskset(dev, B43_PHY_OFDM(0xFB),
-                               0x8000, gains.pad | pa_gain);
+                               0x8000, gains.pad | (pa_gain << 6));
                b43_phy_write(dev, B43_PHY_OFDM(0xFC),
                              (gains.pga << 8) | gains.gm);
                b43_phy_maskset(dev, B43_PHY_OFDM(0xFD),
-                               0x8000, gains.pad | pa_gain);
+                               0x8000, gains.pad | (pa_gain << 8));
        }
        lpphy_set_dac_gain(dev, gains.dac);
-       if (dev->phy.rev < 2) {
-               b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF, 1 << 8);
-       } else {
-               b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F, 1 << 7);
-               b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF, 1 << 14);
-       }
-       b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF, 1 << 6);
+       lpphy_enable_tx_gain_override(dev);
 }
 
 static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain)
@@ -890,38 +965,6 @@ static void lpphy_rev2plus_set_rx_gain(struct b43_wldev *dev, u32 gain)
        }
 }
 
-static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
-{
-       b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
-       b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
-       b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
-       if (dev->phy.rev >= 2) {
-               b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
-               if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
-                       b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
-                       b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7);
-               }
-       } else {
-               b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
-       }
-}
-
-static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
-{
-       b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
-       b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
-       b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
-       if (dev->phy.rev >= 2) {
-               b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
-               if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
-                       b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
-                       b43_phy_set(dev, B43_PHY_OFDM(0xE5), 0x8);
-               }
-       } else {
-               b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
-       }
-}
-
 static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain)
 {
        if (dev->phy.rev < 2)
@@ -956,7 +999,7 @@ static void lpphy_run_ddfs(struct b43_wldev *dev, int i_on, int q_on,
        b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFF9F, scale_idx << 5);
        b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB);
        b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x2);
-       b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x20);
+       b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x20);
 }
 
 static bool lpphy_rx_iq_est(struct b43_wldev *dev, u16 samples, u8 time,
@@ -968,7 +1011,7 @@ static bool lpphy_rx_iq_est(struct b43_wldev *dev, u16 samples, u8 time,
        b43_phy_write(dev, B43_LPPHY_IQ_NUM_SMPLS_ADDR, samples);
        b43_phy_maskset(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFF00, time);
        b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF);
-       b43_phy_set(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFDFF);
+       b43_phy_set(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0x200);
 
        for (i = 0; i < 500; i++) {
                if (!(b43_phy_read(dev,
@@ -1006,8 +1049,7 @@ static int lpphy_loopback(struct b43_wldev *dev)
 
        memset(&iq_est, 0, sizeof(iq_est));
 
-       b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x3);
-       b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
+       lpphy_set_trsw_over(dev, true, true);
        b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 1);
        b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
        b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
@@ -1032,9 +1074,10 @@ static int lpphy_loopback(struct b43_wldev *dev)
        return index;
 }
 
+/* Fixed-point division algorithm using only integer math. */
 static u32 lpphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
 {
-       u32 quotient, remainder, rbit, roundup, tmp;
+       u32 quotient, remainder;
 
        if (divisor == 0)
                return 0;
@@ -1042,20 +1085,16 @@ static u32 lpphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
        quotient = dividend / divisor;
        remainder = dividend % divisor;
 
-       rbit = divisor & 0x1;
-       roundup = (divisor >> 1) + rbit;
-
-       while (precision != 0) {
-               tmp = remainder - roundup;
+       while (precision > 0) {
                quotient <<= 1;
-               if (remainder >= roundup)
-                       remainder = (tmp << 1) + rbit;
-               else
-                       remainder <<= 1;
+               if (remainder << 1 >= divisor) {
+                       quotient++;
+                       remainder = (remainder << 1) - divisor;
+               }
                precision--;
        }
 
-       if (remainder >= roundup)
+       if (remainder << 1 >= divisor)
                quotient++;
 
        return quotient;
@@ -1106,7 +1145,7 @@ static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
                B43_WARN_ON(1);
        }
        b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
-                       (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE, ctl);
+                       ~B43_LPPHY_TX_PWR_CTL_CMD_MODE & 0xFFFF, ctl);
 }
 
 static void lpphy_set_tx_power_control(struct b43_wldev *dev,
@@ -1132,15 +1171,15 @@ static void lpphy_set_tx_power_control(struct b43_wldev *dev,
                        b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
                                        0x8FFF, ((u16)lpphy->tssi_npt << 16));
                        //TODO Set "TSSI Transmit Count" variable to total transmitted frame count
-                       //TODO Disable TX gain override
+                       lpphy_disable_tx_gain_override(dev);
                        lpphy->tx_pwr_idx_over = -1;
                }
        }
        if (dev->phy.rev >= 2) {
                if (mode == B43_LPPHY_TXPCTL_HW)
-                       b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0x2);
+                       b43_phy_set(dev, B43_PHY_OFDM(0xD0), 0x2);
                else
-                       b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0);
+                       b43_phy_mask(dev, B43_PHY_OFDM(0xD0), 0xFFFD);
        }
        lpphy_write_tx_pctl_mode_to_hardware(dev);
 }
@@ -1172,7 +1211,7 @@ static void lpphy_rev0_1_rc_calib(struct b43_wldev *dev)
        err = b43_lpphy_op_switch_channel(dev, 7);
        if (err) {
                b43dbg(dev->wl,
-                      "RC calib: Failed to switch to channel 7, error = %d",
+                      "RC calib: Failed to switch to channel 7, error = %d\n",
                       err);
        }
        old_txg_ovr = !!(b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40);
@@ -1250,7 +1289,7 @@ finish:
 
 static void lpphy_rev2plus_rc_calib(struct b43_wldev *dev)
 {
-       struct ssb_bus *bus = dev->dev->bus;
+       struct ssb_bus *bus = dev->dev->sdev->bus;
        u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
        u8 tmp = b43_radio_read(dev, B2063_RX_BB_SP8) & 0xFF;
        int i;
@@ -1318,15 +1357,73 @@ static void lpphy_calibrate_rc(struct b43_wldev *dev)
        }
 }
 
+static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
+{
+       if (dev->phy.rev >= 2)
+               return; // rev2+ doesn't support antenna diversity
+
+       if (B43_WARN_ON(antenna > B43_ANTENNA_AUTO1))
+               return;
+
+       b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP);
+
+       b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFD, antenna & 0x2);
+       b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFE, antenna & 0x1);
+
+       b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP);
+
+       dev->phy.lp->antenna = antenna;
+}
+
+static void lpphy_set_tx_iqcc(struct b43_wldev *dev, u16 a, u16 b)
+{
+       u16 tmp[2];
+
+       tmp[0] = a;
+       tmp[1] = b;
+       b43_lptab_write_bulk(dev, B43_LPTAB16(0, 80), 2, tmp);
+}
+
 static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
 {
        struct b43_phy_lp *lpphy = dev->phy.lp;
+       struct lpphy_tx_gains gains;
+       u32 iq_comp, tx_gain, coeff, rf_power;
 
        lpphy->tx_pwr_idx_over = index;
+       lpphy_read_tx_pctl_mode_from_hardware(dev);
        if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
                lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
-
-       //TODO
+       if (dev->phy.rev >= 2) {
+               iq_comp = b43_lptab_read(dev, B43_LPTAB32(7, index + 320));
+               tx_gain = b43_lptab_read(dev, B43_LPTAB32(7, index + 192));
+               gains.pad = (tx_gain >> 16) & 0xFF;
+               gains.gm = tx_gain & 0xFF;
+               gains.pga = (tx_gain >> 8) & 0xFF;
+               gains.dac = (iq_comp >> 28) & 0xFF;
+               lpphy_set_tx_gains(dev, gains);
+       } else {
+               iq_comp = b43_lptab_read(dev, B43_LPTAB32(10, index + 320));
+               tx_gain = b43_lptab_read(dev, B43_LPTAB32(10, index + 192));
+               b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
+                               0xF800, (tx_gain >> 4) & 0x7FFF);
+               lpphy_set_dac_gain(dev, tx_gain & 0x7);
+               lpphy_set_pa_gain(dev, (tx_gain >> 24) & 0x7F);
+       }
+       lpphy_set_bb_mult(dev, (iq_comp >> 20) & 0xFF);
+       lpphy_set_tx_iqcc(dev, (iq_comp >> 10) & 0x3FF, iq_comp & 0x3FF);
+       if (dev->phy.rev >= 2) {
+               coeff = b43_lptab_read(dev, B43_LPTAB32(7, index + 448));
+       } else {
+               coeff = b43_lptab_read(dev, B43_LPTAB32(10, index + 448));
+       }
+       b43_lptab_write(dev, B43_LPTAB16(0, 85), coeff & 0xFFFF);
+       if (dev->phy.rev >= 2) {
+               rf_power = b43_lptab_read(dev, B43_LPTAB32(7, index + 576));
+               b43_phy_maskset(dev, B43_LPPHY_RF_PWR_OVERRIDE, 0xFF00,
+                               rf_power & 0xFFFF);//SPEC FIXME mask & set != 0
+       }
+       lpphy_enable_tx_gain_override(dev);
 }
 
 static void lpphy_btcoex_override(struct b43_wldev *dev)
@@ -1335,58 +1432,45 @@ static void lpphy_btcoex_override(struct b43_wldev *dev)
        b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
 }
 
-static void lpphy_pr41573_workaround(struct b43_wldev *dev)
+static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
+                                        bool blocked)
 {
-       struct b43_phy_lp *lpphy = dev->phy.lp;
-       u32 *saved_tab;
-       const unsigned int saved_tab_size = 256;
-       enum b43_lpphy_txpctl_mode txpctl_mode;
-       s8 tx_pwr_idx_over;
-       u16 tssi_npt, tssi_idx;
-
-       saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
-       if (!saved_tab) {
-               b43err(dev->wl, "PR41573 failed. Out of memory!\n");
-               return;
-       }
-
-       lpphy_read_tx_pctl_mode_from_hardware(dev);
-       txpctl_mode = lpphy->txpctl_mode;
-       tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
-       tssi_npt = lpphy->tssi_npt;
-       tssi_idx = lpphy->tssi_idx;
-
-       if (dev->phy.rev < 2) {
-               b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
-                                   saved_tab_size, saved_tab);
+       //TODO check MAC control register
+       if (blocked) {
+               if (dev->phy.rev >= 2) {
+                       b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x83FF);
+                       b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1F00);
+                       b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0x80FF);
+                       b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xDFFF);
+                       b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x0808);
+               } else {
+                       b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xE0FF);
+                       b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1F00);
+                       b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFCFF);
+                       b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x0018);
+               }
        } else {
-               b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
-                                   saved_tab_size, saved_tab);
+               b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xE0FF);
+               if (dev->phy.rev >= 2)
+                       b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xF7F7);
+               else
+                       b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFE7);
        }
-       //TODO
-
-       kfree(saved_tab);
 }
 
-static void lpphy_calibration(struct b43_wldev *dev)
+/* This was previously called lpphy_japan_filter */
+static void lpphy_set_analog_filter(struct b43_wldev *dev, int channel)
 {
        struct b43_phy_lp *lpphy = dev->phy.lp;
-       enum b43_lpphy_txpctl_mode saved_pctl_mode;
-
-       b43_mac_suspend(dev);
-
-       lpphy_btcoex_override(dev);
-       lpphy_read_tx_pctl_mode_from_hardware(dev);
-       saved_pctl_mode = lpphy->txpctl_mode;
-       lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
-       //TODO Perform transmit power table I/Q LO calibration
-       if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
-               lpphy_pr41573_workaround(dev);
-       //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
-       lpphy_set_tx_power_control(dev, saved_pctl_mode);
-       //TODO Perform I/Q calibration with a single control value set
+       u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
 
-       b43_mac_enable(dev);
+       if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
+               b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
+               if ((dev->phy.rev == 1) && (lpphy->rc_cap))
+                       lpphy_set_rc_cap(dev);
+       } else {
+               b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
+       }
 }
 
 static void lpphy_set_tssi_mux(struct b43_wldev *dev, enum tssi_mux_mode mode)
@@ -1438,11 +1522,11 @@ static void lpphy_tx_pctl_init_hw(struct b43_wldev *dev)
        b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xFF);
        b43_phy_write(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xA);
        b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
-                       (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
+                       ~B43_LPPHY_TX_PWR_CTL_CMD_MODE & 0xFFFF,
                        B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF);
        b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xF8FF);
        b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
-                       (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
+                       ~B43_LPPHY_TX_PWR_CTL_CMD_MODE & 0xFFFF,
                        B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW);
 
        if (dev->phy.rev < 2) {
@@ -1495,6 +1579,418 @@ static void lpphy_tx_pctl_init(struct b43_wldev *dev)
        }
 }
 
+static void lpphy_pr41573_workaround(struct b43_wldev *dev)
+{
+       struct b43_phy_lp *lpphy = dev->phy.lp;
+       u32 *saved_tab;
+       const unsigned int saved_tab_size = 256;
+       enum b43_lpphy_txpctl_mode txpctl_mode;
+       s8 tx_pwr_idx_over;
+       u16 tssi_npt, tssi_idx;
+
+       saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
+       if (!saved_tab) {
+               b43err(dev->wl, "PR41573 failed. Out of memory!\n");
+               return;
+       }
+
+       lpphy_read_tx_pctl_mode_from_hardware(dev);
+       txpctl_mode = lpphy->txpctl_mode;
+       tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
+       tssi_npt = lpphy->tssi_npt;
+       tssi_idx = lpphy->tssi_idx;
+
+       if (dev->phy.rev < 2) {
+               b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
+                                   saved_tab_size, saved_tab);
+       } else {
+               b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
+                                   saved_tab_size, saved_tab);
+       }
+       //FIXME PHY reset
+       lpphy_table_init(dev); //FIXME is table init needed?
+       lpphy_baseband_init(dev);
+       lpphy_tx_pctl_init(dev);
+       b43_lpphy_op_software_rfkill(dev, false);
+       lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
+       if (dev->phy.rev < 2) {
+               b43_lptab_write_bulk(dev, B43_LPTAB32(10, 0x140),
+                                    saved_tab_size, saved_tab);
+       } else {
+               b43_lptab_write_bulk(dev, B43_LPTAB32(7, 0x140),
+                                    saved_tab_size, saved_tab);
+       }
+       b43_write16(dev, B43_MMIO_CHANNEL, lpphy->channel);
+       lpphy->tssi_npt = tssi_npt;
+       lpphy->tssi_idx = tssi_idx;
+       lpphy_set_analog_filter(dev, lpphy->channel);
+       if (tx_pwr_idx_over != -1)
+               lpphy_set_tx_power_by_index(dev, tx_pwr_idx_over);
+       if (lpphy->rc_cap)
+               lpphy_set_rc_cap(dev);
+       b43_lpphy_op_set_rx_antenna(dev, lpphy->antenna);
+       lpphy_set_tx_power_control(dev, txpctl_mode);
+       kfree(saved_tab);
+}
+
+struct lpphy_rx_iq_comp { u8 chan; s8 c1, c0; };
+
+static const struct lpphy_rx_iq_comp lpphy_5354_iq_table[] = {
+       { .chan = 1, .c1 = -66, .c0 = 15, },
+       { .chan = 2, .c1 = -66, .c0 = 15, },
+       { .chan = 3, .c1 = -66, .c0 = 15, },
+       { .chan = 4, .c1 = -66, .c0 = 15, },
+       { .chan = 5, .c1 = -66, .c0 = 15, },
+       { .chan = 6, .c1 = -66, .c0 = 15, },
+       { .chan = 7, .c1 = -66, .c0 = 14, },
+       { .chan = 8, .c1 = -66, .c0 = 14, },
+       { .chan = 9, .c1 = -66, .c0 = 14, },
+       { .chan = 10, .c1 = -66, .c0 = 14, },
+       { .chan = 11, .c1 = -66, .c0 = 14, },
+       { .chan = 12, .c1 = -66, .c0 = 13, },
+       { .chan = 13, .c1 = -66, .c0 = 13, },
+       { .chan = 14, .c1 = -66, .c0 = 13, },
+};
+
+static const struct lpphy_rx_iq_comp lpphy_rev0_1_iq_table[] = {
+       { .chan = 1, .c1 = -64, .c0 = 13, },
+       { .chan = 2, .c1 = -64, .c0 = 13, },
+       { .chan = 3, .c1 = -64, .c0 = 13, },
+       { .chan = 4, .c1 = -64, .c0 = 13, },
+       { .chan = 5, .c1 = -64, .c0 = 12, },
+       { .chan = 6, .c1 = -64, .c0 = 12, },
+       { .chan = 7, .c1 = -64, .c0 = 12, },
+       { .chan = 8, .c1 = -64, .c0 = 12, },
+       { .chan = 9, .c1 = -64, .c0 = 12, },
+       { .chan = 10, .c1 = -64, .c0 = 11, },
+       { .chan = 11, .c1 = -64, .c0 = 11, },
+       { .chan = 12, .c1 = -64, .c0 = 11, },
+       { .chan = 13, .c1 = -64, .c0 = 11, },
+       { .chan = 14, .c1 = -64, .c0 = 10, },
+       { .chan = 34, .c1 = -62, .c0 = 24, },
+       { .chan = 38, .c1 = -62, .c0 = 24, },
+       { .chan = 42, .c1 = -62, .c0 = 24, },
+       { .chan = 46, .c1 = -62, .c0 = 23, },
+       { .chan = 36, .c1 = -62, .c0 = 24, },
+       { .chan = 40, .c1 = -62, .c0 = 24, },
+       { .chan = 44, .c1 = -62, .c0 = 23, },
+       { .chan = 48, .c1 = -62, .c0 = 23, },
+       { .chan = 52, .c1 = -62, .c0 = 23, },
+       { .chan = 56, .c1 = -62, .c0 = 22, },
+       { .chan = 60, .c1 = -62, .c0 = 22, },
+       { .chan = 64, .c1 = -62, .c0 = 22, },
+       { .chan = 100, .c1 = -62, .c0 = 16, },
+       { .chan = 104, .c1 = -62, .c0 = 16, },
+       { .chan = 108, .c1 = -62, .c0 = 15, },
+       { .chan = 112, .c1 = -62, .c0 = 14, },
+       { .chan = 116, .c1 = -62, .c0 = 14, },
+       { .chan = 120, .c1 = -62, .c0 = 13, },
+       { .chan = 124, .c1 = -62, .c0 = 12, },
+       { .chan = 128, .c1 = -62, .c0 = 12, },
+       { .chan = 132, .c1 = -62, .c0 = 12, },
+       { .chan = 136, .c1 = -62, .c0 = 11, },
+       { .chan = 140, .c1 = -62, .c0 = 10, },
+       { .chan = 149, .c1 = -61, .c0 = 9, },
+       { .chan = 153, .c1 = -61, .c0 = 9, },
+       { .chan = 157, .c1 = -61, .c0 = 9, },
+       { .chan = 161, .c1 = -61, .c0 = 8, },
+       { .chan = 165, .c1 = -61, .c0 = 8, },
+       { .chan = 184, .c1 = -62, .c0 = 25, },
+       { .chan = 188, .c1 = -62, .c0 = 25, },
+       { .chan = 192, .c1 = -62, .c0 = 25, },
+       { .chan = 196, .c1 = -62, .c0 = 25, },
+       { .chan = 200, .c1 = -62, .c0 = 25, },
+       { .chan = 204, .c1 = -62, .c0 = 25, },
+       { .chan = 208, .c1 = -62, .c0 = 25, },
+       { .chan = 212, .c1 = -62, .c0 = 25, },
+       { .chan = 216, .c1 = -62, .c0 = 26, },
+};
+
+static const struct lpphy_rx_iq_comp lpphy_rev2plus_iq_comp = {
+       .chan = 0,
+       .c1 = -64,
+       .c0 = 0,
+};
+
+static int lpphy_calc_rx_iq_comp(struct b43_wldev *dev, u16 samples)
+{
+       struct lpphy_iq_est iq_est;
+       u16 c0, c1;
+       int prod, ipwr, qpwr, prod_msb, q_msb, tmp1, tmp2, tmp3, tmp4, ret;
+
+       c1 = b43_phy_read(dev, B43_LPPHY_RX_COMP_COEFF_S);
+       c0 = c1 >> 8;
+       c1 |= 0xFF;
+
+       b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, 0x00C0);
+       b43_phy_mask(dev, B43_LPPHY_RX_COMP_COEFF_S, 0x00FF);
+
+       ret = lpphy_rx_iq_est(dev, samples, 32, &iq_est);
+       if (!ret)
+               goto out;
+
+       prod = iq_est.iq_prod;
+       ipwr = iq_est.i_pwr;
+       qpwr = iq_est.q_pwr;
+
+       if (ipwr + qpwr < 2) {
+               ret = 0;
+               goto out;
+       }
+
+       prod_msb = fls(abs(prod));
+       q_msb = fls(abs(qpwr));
+       tmp1 = prod_msb - 20;
+
+       if (tmp1 >= 0) {
+               tmp3 = ((prod << (30 - prod_msb)) + (ipwr >> (1 + tmp1))) /
+                       (ipwr >> tmp1);
+       } else {
+               tmp3 = ((prod << (30 - prod_msb)) + (ipwr << (-1 - tmp1))) /
+                       (ipwr << -tmp1);
+       }
+
+       tmp2 = q_msb - 11;
+
+       if (tmp2 >= 0)
+               tmp4 = (qpwr << (31 - q_msb)) / (ipwr >> tmp2);
+       else
+               tmp4 = (qpwr << (31 - q_msb)) / (ipwr << -tmp2);
+
+       tmp4 -= tmp3 * tmp3;
+       tmp4 = -int_sqrt(tmp4);
+
+       c0 = tmp3 >> 3;
+       c1 = tmp4 >> 4;
+
+out:
+       b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, c1);
+       b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0x00FF, c0 << 8);
+       return ret;
+}
+
+static void lpphy_run_samples(struct b43_wldev *dev, u16 samples, u16 loops,
+                             u16 wait)
+{
+       b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_BUFFER_CTL,
+                       0xFFC0, samples - 1);
+       if (loops != 0xFFFF)
+               loops--;
+       b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_COUNT, 0xF000, loops);
+       b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_BUFFER_CTL, 0x3F, wait << 6);
+       b43_phy_set(dev, B43_LPPHY_A_PHY_CTL_ADDR, 0x1);
+}
+
+//SPEC FIXME what does a negative freq mean?
+static void lpphy_start_tx_tone(struct b43_wldev *dev, s32 freq, u16 max)
+{
+       struct b43_phy_lp *lpphy = dev->phy.lp;
+       u16 buf[64];
+       int i, samples = 0, angle = 0;
+       int rotation = (((36 * freq) / 20) << 16) / 100;
+       struct b43_c32 sample;
+
+       lpphy->tx_tone_freq = freq;
+
+       if (freq) {
+               /* Find i for which abs(freq) integrally divides 20000 * i */
+               for (i = 1; samples * abs(freq) != 20000 * i; i++) {
+                       samples = (20000 * i) / abs(freq);
+                       if(B43_WARN_ON(samples > 63))
+                               return;
+               }
+       } else {
+               samples = 2;
+       }
+
+       for (i = 0; i < samples; i++) {
+               sample = b43_cordic(angle);
+               angle += rotation;
+               buf[i] = CORDIC_CONVERT((sample.i * max) & 0xFF) << 8;
+               buf[i] |= CORDIC_CONVERT((sample.q * max) & 0xFF);
+       }
+
+       b43_lptab_write_bulk(dev, B43_LPTAB16(5, 0), samples, buf);
+
+       lpphy_run_samples(dev, samples, 0xFFFF, 0);
+}
+
+static void lpphy_stop_tx_tone(struct b43_wldev *dev)
+{
+       struct b43_phy_lp *lpphy = dev->phy.lp;
+       int i;
+
+       lpphy->tx_tone_freq = 0;
+
+       b43_phy_mask(dev, B43_LPPHY_SMPL_PLAY_COUNT, 0xF000);
+       for (i = 0; i < 31; i++) {
+               if (!(b43_phy_read(dev, B43_LPPHY_A_PHY_CTL_ADDR) & 0x1))
+                       break;
+               udelay(100);
+       }
+}
+
+
+static void lpphy_papd_cal(struct b43_wldev *dev, struct lpphy_tx_gains gains,
+                          int mode, bool useindex, u8 index)
+{
+       //TODO
+}
+
+static void lpphy_papd_cal_txpwr(struct b43_wldev *dev)
+{
+       struct b43_phy_lp *lpphy = dev->phy.lp;
+       struct lpphy_tx_gains gains, oldgains;
+       int old_txpctl, old_afe_ovr, old_rf, old_bbmult;
+
+       lpphy_read_tx_pctl_mode_from_hardware(dev);
+       old_txpctl = lpphy->txpctl_mode;
+       old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40;
+       if (old_afe_ovr)
+               oldgains = lpphy_get_tx_gains(dev);
+       old_rf = b43_phy_read(dev, B43_LPPHY_RF_PWR_OVERRIDE) & 0xFF;
+       old_bbmult = lpphy_get_bb_mult(dev);
+
+       lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
+
+       if (dev->dev->chip_id == 0x4325 && dev->dev->chip_rev == 0)
+               lpphy_papd_cal(dev, gains, 0, 1, 30);
+       else
+               lpphy_papd_cal(dev, gains, 0, 1, 65);
+
+       if (old_afe_ovr)
+               lpphy_set_tx_gains(dev, oldgains);
+       lpphy_set_bb_mult(dev, old_bbmult);
+       lpphy_set_tx_power_control(dev, old_txpctl);
+       b43_phy_maskset(dev, B43_LPPHY_RF_PWR_OVERRIDE, 0xFF00, old_rf);
+}
+
+static int lpphy_rx_iq_cal(struct b43_wldev *dev, bool noise, bool tx,
+                           bool rx, bool pa, struct lpphy_tx_gains *gains)
+{
+       struct b43_phy_lp *lpphy = dev->phy.lp;
+       const struct lpphy_rx_iq_comp *iqcomp = NULL;
+       struct lpphy_tx_gains nogains, oldgains;
+       u16 tmp;
+       int i, ret;
+
+       memset(&nogains, 0, sizeof(nogains));
+       memset(&oldgains, 0, sizeof(oldgains));
+
+       if (dev->dev->chip_id == 0x5354) {
+               for (i = 0; i < ARRAY_SIZE(lpphy_5354_iq_table); i++) {
+                       if (lpphy_5354_iq_table[i].chan == lpphy->channel) {
+                               iqcomp = &lpphy_5354_iq_table[i];
+                       }
+               }
+       } else if (dev->phy.rev >= 2) {
+               iqcomp = &lpphy_rev2plus_iq_comp;
+       } else {
+               for (i = 0; i < ARRAY_SIZE(lpphy_rev0_1_iq_table); i++) {
+                       if (lpphy_rev0_1_iq_table[i].chan == lpphy->channel) {
+                               iqcomp = &lpphy_rev0_1_iq_table[i];
+                       }
+               }
+       }
+
+       if (B43_WARN_ON(!iqcomp))
+               return 0;
+
+       b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, iqcomp->c1);
+       b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S,
+                       0x00FF, iqcomp->c0 << 8);
+
+       if (noise) {
+               tx = true;
+               rx = false;
+               pa = false;
+       }
+
+       lpphy_set_trsw_over(dev, tx, rx);
+
+       if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
+               b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
+               b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0,
+                               0xFFF7, pa << 3);
+       } else {
+               b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20);
+               b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0,
+                               0xFFDF, pa << 5);
+       }
+
+       tmp = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40;
+
+       if (noise)
+               lpphy_set_rx_gain(dev, 0x2D5D);
+       else {
+               if (tmp)
+                       oldgains = lpphy_get_tx_gains(dev);
+               if (!gains)
+                       gains = &nogains;
+               lpphy_set_tx_gains(dev, *gains);
+       }
+
+       b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE);
+       b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
+       b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
+       b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800);
+       lpphy_set_deaf(dev, false);
+       if (noise)
+               ret = lpphy_calc_rx_iq_comp(dev, 0xFFF0);
+       else {
+               lpphy_start_tx_tone(dev, 4000, 100);
+               ret = lpphy_calc_rx_iq_comp(dev, 0x4000);
+               lpphy_stop_tx_tone(dev);
+       }
+       lpphy_clear_deaf(dev, false);
+       b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFC);
+       b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFF7);
+       b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFDF);
+       if (!noise) {
+               if (tmp)
+                       lpphy_set_tx_gains(dev, oldgains);
+               else
+                       lpphy_disable_tx_gain_override(dev);
+       }
+       lpphy_disable_rx_gain_override(dev);
+       b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE);
+       b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xF7FF);
+       return ret;
+}
+
+static void lpphy_calibration(struct b43_wldev *dev)
+{
+       struct b43_phy_lp *lpphy = dev->phy.lp;
+       enum b43_lpphy_txpctl_mode saved_pctl_mode;
+       bool full_cal = false;
+
+       if (lpphy->full_calib_chan != lpphy->channel) {
+               full_cal = true;
+               lpphy->full_calib_chan = lpphy->channel;
+       }
+
+       b43_mac_suspend(dev);
+
+       lpphy_btcoex_override(dev);
+       if (dev->phy.rev >= 2)
+               lpphy_save_dig_flt_state(dev);
+       lpphy_read_tx_pctl_mode_from_hardware(dev);
+       saved_pctl_mode = lpphy->txpctl_mode;
+       lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
+       //TODO Perform transmit power table I/Q LO calibration
+       if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
+               lpphy_pr41573_workaround(dev);
+       if ((dev->phy.rev >= 2) && full_cal) {
+               lpphy_papd_cal_txpwr(dev);
+       }
+       lpphy_set_tx_power_control(dev, saved_pctl_mode);
+       if (dev->phy.rev >= 2)
+               lpphy_restore_dig_flt_state(dev);
+       lpphy_rx_iq_cal(dev, true, true, false, false, NULL);
+
+       b43_mac_enable(dev);
+}
+
 static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
 {
        b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
@@ -1507,6 +2003,14 @@ static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
        b43_write16(dev, B43_MMIO_PHY_DATA, value);
 }
 
+static void b43_lpphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
+                                u16 set)
+{
+       b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
+       b43_write16(dev, B43_MMIO_PHY_DATA,
+                   (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
+}
+
 static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
 {
        /* Register 1 is a 32-bit register. */
@@ -1531,12 +2035,6 @@ static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
        b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
 }
 
-static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
-                                        bool blocked)
-{
-       //TODO
-}
-
 struct b206x_channel {
        u8 channel;
        u16 freq;
@@ -1908,11 +2406,9 @@ static const struct b206x_channel b2063_chantbl[] = {
 
 static void lpphy_b2062_reset_pll_bias(struct b43_wldev *dev)
 {
-       struct ssb_bus *bus = dev->dev->bus;
-
        b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0xFF);
        udelay(20);
-       if (bus->chip_id == 0x5354) {
+       if (dev->dev->chip_id == 0x5354) {
                b43_radio_write(dev, B2062_N_COMM1, 4);
                b43_radio_write(dev, B2062_S_RFPLL_CTL2, 4);
        } else {
@@ -1923,8 +2419,8 @@ static void lpphy_b2062_reset_pll_bias(struct b43_wldev *dev)
 
 static void lpphy_b2062_vco_calib(struct b43_wldev *dev)
 {
-       b43_phy_write(dev, B2062_S_RFPLL_CTL21, 0x42);
-       b43_phy_write(dev, B2062_S_RFPLL_CTL21, 0x62);
+       b43_radio_write(dev, B2062_S_RFPLL_CTL21, 0x42);
+       b43_radio_write(dev, B2062_S_RFPLL_CTL21, 0x62);
        udelay(200);
 }
 
@@ -1932,7 +2428,7 @@ static int lpphy_b2062_tune(struct b43_wldev *dev,
                            unsigned int channel)
 {
        struct b43_phy_lp *lpphy = dev->phy.lp;
-       struct ssb_bus *bus = dev->dev->bus;
+       struct ssb_bus *bus = dev->dev->sdev->bus;
        const struct b206x_channel *chandata = NULL;
        u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
        u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9;
@@ -1983,7 +2479,7 @@ static int lpphy_b2062_tune(struct b43_wldev *dev,
        tmp6 = tmp5 / tmp4;
        tmp7 = tmp5 % tmp4;
        b43_radio_write(dev, B2062_S_RFPLL_CTL29, tmp6 + ((2 * tmp7) / tmp4));
-       tmp8 = b43_phy_read(dev, B2062_S_RFPLL_CTL19);
+       tmp8 = b43_radio_read(dev, B2062_S_RFPLL_CTL19);
        tmp9 = ((2 * tmp3 * (tmp8 + 1)) + (3 * tmp1)) / (6 * tmp1);
        b43_radio_write(dev, B2062_S_RFPLL_CTL23, (tmp9 >> 8) + 16);
        b43_radio_write(dev, B2062_S_RFPLL_CTL24, tmp9 & 0xFF);
@@ -2002,43 +2498,27 @@ static int lpphy_b2062_tune(struct b43_wldev *dev,
        return err;
 }
 
-
-/* This was previously called lpphy_japan_filter */
-static void lpphy_set_analog_filter(struct b43_wldev *dev, int channel)
-{
-       struct b43_phy_lp *lpphy = dev->phy.lp;
-       u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
-
-       if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
-               b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
-               if ((dev->phy.rev == 1) && (lpphy->rc_cap))
-                       lpphy_set_rc_cap(dev);
-       } else {
-               b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
-       }
-}
-
 static void lpphy_b2063_vco_calib(struct b43_wldev *dev)
 {
        u16 tmp;
 
-       b43_phy_mask(dev, B2063_PLL_SP1, ~0x40);
-       tmp = b43_phy_read(dev, B2063_PLL_JTAG_CALNRST) & 0xF8;
-       b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp);
+       b43_radio_mask(dev, B2063_PLL_SP1, ~0x40);
+       tmp = b43_radio_read(dev, B2063_PLL_JTAG_CALNRST) & 0xF8;
+       b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp);
        udelay(1);
-       b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x4);
+       b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x4);
        udelay(1);
-       b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x6);
+       b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x6);
        udelay(1);
-       b43_phy_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x7);
+       b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x7);
        udelay(300);
-       b43_phy_set(dev, B2063_PLL_SP1, 0x40);
+       b43_radio_set(dev, B2063_PLL_SP1, 0x40);
 }
 
 static int lpphy_b2063_tune(struct b43_wldev *dev,
                            unsigned int channel)
 {
-       struct ssb_bus *bus = dev->dev->bus;
+       struct ssb_bus *bus = dev->dev->sdev->bus;
 
        static const struct b206x_channel *chandata = NULL;
        u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
@@ -2127,31 +2607,31 @@ static int lpphy_b2063_tune(struct b43_wldev *dev,
                scale = 0;
                tmp5 = ((tmp4 + (tmp3 >> 1)) / tmp3) - 8;
        }
-       b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFC0, tmp5);
-       b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFBF, scale << 6);
+       b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFC0, tmp5);
+       b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFBF, scale << 6);
 
        tmp6 = lpphy_qdiv_roundup(100 * val1, val3, 16);
        tmp6 *= (tmp5 * 8) * (scale + 1);
        if (tmp6 > 150)
                tmp6 = 0;
 
-       b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFE0, tmp6);
-       b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFDF, scale << 5);
+       b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFE0, tmp6);
+       b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFDF, scale << 5);
 
-       b43_phy_maskset(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFFFB, 0x4);
+       b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFFFB, 0x4);
        if (crystal_freq > 26000000)
-               b43_phy_set(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0x2);
+               b43_radio_set(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0x2);
        else
-               b43_phy_mask(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFD);
+               b43_radio_mask(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFD);
 
        if (val1 == 45)
-               b43_phy_set(dev, B2063_PLL_JTAG_PLL_VCO1, 0x2);
+               b43_radio_set(dev, B2063_PLL_JTAG_PLL_VCO1, 0x2);
        else
-               b43_phy_mask(dev, B2063_PLL_JTAG_PLL_VCO1, 0xFD);
+               b43_radio_mask(dev, B2063_PLL_JTAG_PLL_VCO1, 0xFD);
 
-       b43_phy_set(dev, B2063_PLL_SP2, 0x3);
+       b43_radio_set(dev, B2063_PLL_SP2, 0x3);
        udelay(1);
-       b43_phy_mask(dev, B2063_PLL_SP2, 0xFFFC);
+       b43_radio_mask(dev, B2063_PLL_SP2, 0xFFFC);
        lpphy_b2063_vco_calib(dev);
        b43_radio_write(dev, B2063_COMM15, old_comm15);
 
@@ -2161,10 +2641,9 @@ static int lpphy_b2063_tune(struct b43_wldev *dev,
 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
                                       unsigned int new_channel)
 {
+       struct b43_phy_lp *lpphy = dev->phy.lp;
        int err;
 
-       b43_write16(dev, B43_MMIO_CHANNEL, new_channel);
-
        if (dev->phy.radio_ver == 0x2063) {
                err = lpphy_b2063_tune(dev, new_channel);
                if (err)
@@ -2177,6 +2656,9 @@ static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
                lpphy_adjust_gain_table(dev, channel2freq_lp(new_channel));
        }
 
+       lpphy->channel = new_channel;
+       b43_write16(dev, B43_MMIO_CHANNEL, new_channel);
+
        return 0;
 }
 
@@ -2184,14 +2666,18 @@ static int b43_lpphy_op_init(struct b43_wldev *dev)
 {
        int err;
 
+       if (dev->dev->bus_type != B43_BUS_SSB) {
+               b43err(dev->wl, "LP-PHY is supported only on SSB!\n");
+               return -EOPNOTSUPP;
+       }
+
        lpphy_read_band_sprom(dev); //FIXME should this be in prepare_structs?
        lpphy_baseband_init(dev);
        lpphy_radio_init(dev);
        lpphy_calibrate_rc(dev);
-       err = b43_lpphy_op_switch_channel(dev,
-                               b43_lpphy_op_get_default_chan(dev));
+       err = b43_lpphy_op_switch_channel(dev, 7);
        if (err) {
-               b43dbg(dev->wl, "Switch to init channel failed, error = %d.\n",
+               b43dbg(dev->wl, "Switch to channel 7 failed, error = %d.\n",
                       err);
        }
        lpphy_tx_pctl_init(dev);
@@ -2201,11 +2687,6 @@ static int b43_lpphy_op_init(struct b43_wldev *dev)
        return 0;
 }
 
-static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
-{
-       //TODO
-}
-
 static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
 {
        //TODO
@@ -2218,6 +2699,21 @@ static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
        return B43_TXPWR_RES_DONE;
 }
 
+static void b43_lpphy_op_switch_analog(struct b43_wldev *dev, bool on)
+{
+       if (on) {
+               b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xfff8);
+       } else {
+               b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0x0007);
+               b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 0x0007);
+       }
+}
+
+static void b43_lpphy_op_pwork_15sec(struct b43_wldev *dev)
+{
+       //TODO
+}
+
 const struct b43_phy_operations b43_phyops_lp = {
        .allocate               = b43_lpphy_op_allocate,
        .free                   = b43_lpphy_op_free,
@@ -2225,13 +2721,16 @@ const struct b43_phy_operations b43_phyops_lp = {
        .init                   = b43_lpphy_op_init,
        .phy_read               = b43_lpphy_op_read,
        .phy_write              = b43_lpphy_op_write,
+       .phy_maskset            = b43_lpphy_op_maskset,
        .radio_read             = b43_lpphy_op_radio_read,
        .radio_write            = b43_lpphy_op_radio_write,
        .software_rfkill        = b43_lpphy_op_software_rfkill,
-       .switch_analog          = b43_phyop_switch_analog_generic,
+       .switch_analog          = b43_lpphy_op_switch_analog,
        .switch_channel         = b43_lpphy_op_switch_channel,
        .get_default_chan       = b43_lpphy_op_get_default_chan,
        .set_rx_antenna         = b43_lpphy_op_set_rx_antenna,
        .recalc_txpower         = b43_lpphy_op_recalc_txpower,
        .adjust_txpower         = b43_lpphy_op_adjust_txpower,
+       .pwork_15sec            = b43_lpphy_op_pwork_15sec,
+       .pwork_60sec            = lpphy_calibration,
 };