Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / hw.c
index 633fe8b..f00f5c7 100644 (file)
 #include <linux/io.h>
 #include <asm/unaligned.h>
 
-#include "ath9k.h"
+#include "hw.h"
+#include "rc.h"
 #include "initvals.h"
 
-static int btcoex_enable;
-module_param(btcoex_enable, bool, 0);
-MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
-
 #define ATH9K_CLOCK_RATE_CCK           22
 #define ATH9K_CLOCK_RATE_5GHZ_OFDM     40
 #define ATH9K_CLOCK_RATE_2GHZ_OFDM     44
 
 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
-static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
-                             enum ath9k_ht_macmode macmode);
+static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
                              struct ar5416_eeprom_def *pEepData,
                              u32 reg, u32 value);
-static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
-static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
 
-/********************/
-/* Helper Functions */
-/********************/
+MODULE_AUTHOR("Atheros Communications");
+MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
+MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
+MODULE_LICENSE("Dual BSD/GPL");
 
-static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
+static int __init ath9k_init(void)
 {
-       struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
-
-       if (!ah->curchan) /* should really check for CCK instead */
-               return clks / ATH9K_CLOCK_RATE_CCK;
-       if (conf->channel->band == IEEE80211_BAND_2GHZ)
-               return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
-
-       return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
+       return 0;
 }
+module_init(ath9k_init);
 
-static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
+static void __exit ath9k_exit(void)
 {
-       struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
-
-       if (conf_is_ht40(conf))
-               return ath9k_hw_mac_usec(ah, clks) / 2;
-       else
-               return ath9k_hw_mac_usec(ah, clks);
+       return;
 }
+module_exit(ath9k_exit);
+
+/********************/
+/* Helper Functions */
+/********************/
 
 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
 {
-       struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
+       struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 
        if (!ah->curchan) /* should really check for CCK instead */
                return usecs *ATH9K_CLOCK_RATE_CCK;
@@ -76,7 +65,7 @@ static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
 
 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
 {
-       struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
+       struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 
        if (conf_is_ht40(conf))
                return ath9k_hw_mac_clks(ah, usecs) * 2;
@@ -84,38 +73,6 @@ static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
                return ath9k_hw_mac_clks(ah, usecs);
 }
 
-/*
- * Read and write, they both share the same lock. We do this to serialize
- * reads and writes on Atheros 802.11n PCI devices only. This is required
- * as the FIFO on these devices can only accept sanely 2 requests. After
- * that the device goes bananas. Serializing the reads/writes prevents this
- * from happening.
- */
-
-void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
-{
-       if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
-               unsigned long flags;
-               spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
-               iowrite32(val, ah->ah_sc->mem + reg_offset);
-               spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
-       } else
-               iowrite32(val, ah->ah_sc->mem + reg_offset);
-}
-
-unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
-{
-       u32 val;
-       if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
-               unsigned long flags;
-               spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
-               val = ioread32(ah->ah_sc->mem + reg_offset);
-               spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
-       } else
-               val = ioread32(ah->ah_sc->mem + reg_offset);
-       return val;
-}
-
 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 {
        int i;
@@ -129,12 +86,13 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
                udelay(AH_TIME_QUANTUM);
        }
 
-       DPRINTF(ah->ah_sc, ATH_DBG_ANY,
-               "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
-               timeout, reg, REG_READ(ah, reg), mask, val);
+       ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
+                 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
+                 timeout, reg, REG_READ(ah, reg), mask, val);
 
        return false;
 }
+EXPORT_SYMBOL(ath9k_hw_wait);
 
 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 {
@@ -168,22 +126,19 @@ bool ath9k_get_channel_edges(struct ath_hw *ah,
 }
 
 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
-                          const struct ath_rate_table *rates,
+                          u8 phy, int kbps,
                           u32 frameLen, u16 rateix,
                           bool shortPreamble)
 {
        u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
-       u32 kbps;
-
-       kbps = rates->info[rateix].ratekbps;
 
        if (kbps == 0)
                return 0;
 
-       switch (rates->info[rateix].phy) {
+       switch (phy) {
        case WLAN_RC_PHY_CCK:
                phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
-               if (shortPreamble && rates->info[rateix].short_preamble)
+               if (shortPreamble)
                        phyTime >>= 1;
                numBits = frameLen << 3;
                txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
@@ -213,15 +168,15 @@ u16 ath9k_hw_computetxtime(struct ath_hw *ah,
                }
                break;
        default:
-               DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
-                       "Unknown phy %u (rate ix %u)\n",
-                       rates->info[rateix].phy, rateix);
+               ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
+                         "Unknown phy %u (rate ix %u)\n", phy, rateix);
                txTime = 0;
                break;
        }
 
        return txTime;
 }
+EXPORT_SYMBOL(ath9k_hw_computetxtime);
 
 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
                                  struct ath9k_channel *chan,
@@ -248,10 +203,9 @@ void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 
        centers->ctl_center =
                centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
+       /* 25 MHz spacing is supported by hw but not on upper layers */
        centers->ext_center =
-               centers->synth_center + (extoff *
-                        ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
-                         HT40_CHANNEL_CENTER_SHIFT : 15));
+               centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 }
 
 /******************/
@@ -320,6 +274,7 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
 
 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 {
+       struct ath_common *common = ath9k_hw_common(ah);
        u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
        u32 regHold[2];
        u32 patternData[4] = { 0x55555555,
@@ -338,10 +293,11 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
                        REG_WRITE(ah, addr, wrData);
                        rdData = REG_READ(ah, addr);
                        if (rdData != wrData) {
-                               DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
-                                       "address test failed "
-                                       "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
-                                       addr, wrData, rdData);
+                               ath_print(common, ATH_DBG_FATAL,
+                                         "address test failed "
+                                         "addr: 0x%08x - wr:0x%08x != "
+                                         "rd:0x%08x\n",
+                                         addr, wrData, rdData);
                                return false;
                        }
                }
@@ -350,10 +306,11 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
                        REG_WRITE(ah, addr, wrData);
                        rdData = REG_READ(ah, addr);
                        if (wrData != rdData) {
-                               DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
-                                       "address test failed "
-                                       "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
-                                       addr, wrData, rdData);
+                               ath_print(common, ATH_DBG_FATAL,
+                                         "address test failed "
+                                         "addr: 0x%08x - wr:0x%08x != "
+                                         "rd:0x%08x\n",
+                                         addr, wrData, rdData);
                                return false;
                        }
                }
@@ -364,30 +321,6 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
        return true;
 }
 
-static const char *ath9k_hw_devname(u16 devid)
-{
-       switch (devid) {
-       case AR5416_DEVID_PCI:
-               return "Atheros 5416";
-       case AR5416_DEVID_PCIE:
-               return "Atheros 5418";
-       case AR9160_DEVID_PCI:
-               return "Atheros 9160";
-       case AR5416_AR9100_DEVID:
-               return "Atheros 9100";
-       case AR9280_DEVID_PCI:
-       case AR9280_DEVID_PCIE:
-               return "Atheros 9280";
-       case AR9285_DEVID_PCIE:
-               return "Atheros 9285";
-       case AR5416_DEVID_AR9287_PCI:
-       case AR5416_DEVID_AR9287_PCIE:
-               return "Atheros 9287";
-       }
-
-       return NULL;
-}
-
 static void ath9k_hw_init_config(struct ath_hw *ah)
 {
        int i;
@@ -401,21 +334,23 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
        ah->config.pcie_clock_req = 0;
        ah->config.pcie_waen = 0;
        ah->config.analog_shiftreg = 1;
-       ah->config.ht_enable = 1;
        ah->config.ofdm_trig_low = 200;
        ah->config.ofdm_trig_high = 500;
        ah->config.cck_trig_high = 200;
        ah->config.cck_trig_low = 100;
        ah->config.enable_ani = 1;
-       ah->config.diversity_control = 0;
-       ah->config.antenna_switch_swap = 0;
 
        for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
                ah->config.spurchans[i][0] = AR_NO_SPUR;
                ah->config.spurchans[i][1] = AR_NO_SPUR;
        }
 
-       ah->config.intr_mitigation = true;
+       if (ah->hw_version.devid != AR2427_DEVID_PCIE)
+               ah->config.ht_enable = 1;
+       else
+               ah->config.ht_enable = 0;
+
+       ah->config.rx_intr_mitigation = true;
 
        /*
         * We need this for PCI devices only (Cardbus, PCI, miniPCI)
@@ -436,11 +371,17 @@ static void ath9k_hw_init_config(struct ath_hw *ah)
        if (num_possible_cpus() > 1)
                ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 }
+EXPORT_SYMBOL(ath9k_hw_init);
 
 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 {
+       struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
+
+       regulatory->country_code = CTRY_DEFAULT;
+       regulatory->power_limit = MAX_RATE_POWER;
+       regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
+
        ah->hw_version.magic = AR5416_MAGIC;
-       ah->regulatory.country_code = CTRY_DEFAULT;
        ah->hw_version.subvendorid = 0;
 
        ah->ah_flags = 0;
@@ -449,40 +390,15 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
        if (!AR_SREV_9100(ah))
                ah->ah_flags = AH_USE_EEPROM;
 
-       ah->regulatory.power_limit = MAX_RATE_POWER;
-       ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
        ah->atim_window = 0;
-       ah->diversity_control = ah->config.diversity_control;
-       ah->antenna_switch_swap =
-               ah->config.antenna_switch_swap;
        ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
        ah->beacon_interval = 100;
        ah->enable_32kHz_clock = DONT_USE_32KHZ;
        ah->slottime = (u32) -1;
-       ah->acktimeout = (u32) -1;
-       ah->ctstimeout = (u32) -1;
        ah->globaltxtimeout = (u32) -1;
-
-       ah->gbeacon_rate = 0;
-
        ah->power_mode = ATH9K_PM_UNDEFINED;
 }
 
-static int ath9k_hw_rfattach(struct ath_hw *ah)
-{
-       bool rfStatus = false;
-       int ecode = 0;
-
-       rfStatus = ath9k_hw_init_rf(ah, &ecode);
-       if (!rfStatus) {
-               DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
-                       "RF setup failed, status: %u\n", ecode);
-               return ecode;
-       }
-
-       return 0;
-}
-
 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 {
        u32 val;
@@ -500,9 +416,9 @@ static int ath9k_hw_rf_claim(struct ath_hw *ah)
        case AR_RAD2122_SREV_MAJOR:
                break;
        default:
-               DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
-                       "Radio Chip Rev 0x%02X not supported\n",
-                       val & AR_RADIO_SREV_MAJOR);
+               ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
+                         "Radio Chip Rev 0x%02X not supported\n",
+                         val & AR_RADIO_SREV_MAJOR);
                return -EOPNOTSUPP;
        }
 
@@ -513,6 +429,7 @@ static int ath9k_hw_rf_claim(struct ath_hw *ah)
 
 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 {
+       struct ath_common *common = ath9k_hw_common(ah);
        u32 sum;
        int i;
        u16 eeval;
@@ -521,8 +438,8 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah)
        for (i = 0; i < 3; i++) {
                eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
                sum += eeval;
-               ah->macaddr[2 * i] = eeval >> 8;
-               ah->macaddr[2 * i + 1] = eeval & 0xff;
+               common->macaddr[2 * i] = eeval >> 8;
+               common->macaddr[2 * i + 1] = eeval & 0xff;
        }
        if (sum == 0 || sum == 0xffff * 3)
                return -EADDRNOTAVAIL;
@@ -593,12 +510,20 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
        if (ecode != 0)
                return ecode;
 
-       DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
-               ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
-
-       ecode = ath9k_hw_rfattach(ah);
-       if (ecode != 0)
-               return ecode;
+       ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
+                 "Eeprom VER: %d, REV: %d\n",
+                 ah->eep_ops->get_eeprom_ver(ah),
+                 ah->eep_ops->get_eeprom_rev(ah));
+
+        if (!AR_SREV_9280_10_OR_LATER(ah)) {
+               ecode = ath9k_hw_rf_alloc_ext_banks(ah);
+               if (ecode) {
+                       ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
+                                 "Failed allocating banks for "
+                                 "external radio\n");
+                       return ecode;
+               }
+       }
 
        if (!AR_SREV_9100(ah)) {
                ath9k_hw_ani_setup(ah);
@@ -620,6 +545,8 @@ static bool ath9k_hw_devid_supported(u16 devid)
        case AR9285_DEVID_PCIE:
        case AR5416_DEVID_AR9287_PCI:
        case AR5416_DEVID_AR9287_PCIE:
+       case AR9271_USB:
+       case AR2427_DEVID_PCIE:
                return true;
        default:
                break;
@@ -637,6 +564,7 @@ static bool ath9k_hw_macversion_supported(u32 macversion)
        case AR_SREV_VERSION_9280:
        case AR_SREV_VERSION_9285:
        case AR_SREV_VERSION_9287:
+       case AR_SREV_VERSION_9271:
                return true;
        default:
                break;
@@ -670,6 +598,17 @@ static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
 
 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
 {
+       if (AR_SREV_9271(ah)) {
+               INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
+                              ARRAY_SIZE(ar9271Modes_9271), 6);
+               INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
+                              ARRAY_SIZE(ar9271Common_9271), 2);
+               INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
+                              ar9271Modes_9271_1_0_only,
+                              ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
+               return;
+       }
+
        if (AR_SREV_9287_11_OR_LATER(ah)) {
                INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
                                ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
@@ -835,7 +774,7 @@ static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
 
 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
 {
-       if (AR_SREV_9287_11(ah))
+       if (AR_SREV_9287_11_OR_LATER(ah))
                INIT_INI_ARRAY(&ah->iniModesRxGain,
                ar9287Modes_rx_gain_9287_1_1,
                ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
@@ -846,7 +785,7 @@ static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
        else if (AR_SREV_9280_20(ah))
                ath9k_hw_init_rxgain_ini(ah);
 
-       if (AR_SREV_9287_11(ah)) {
+       if (AR_SREV_9287_11_OR_LATER(ah)) {
                INIT_INI_ARRAY(&ah->iniModesTxGain,
                ar9287Modes_tx_gain_9287_1_1,
                ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
@@ -873,12 +812,11 @@ static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
        }
 }
 
-static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
+static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
 {
        u32 i, j;
 
-       if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
-           test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
+       if (ah->hw_version.devid == AR9280_DEVID_PCI) {
 
                /* EEPROM Fixup */
                for (i = 0; i < ah->iniModes.ia_rows; i++) {
@@ -898,26 +836,28 @@ static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
 
 int ath9k_hw_init(struct ath_hw *ah)
 {
-       int r;
+       struct ath_common *common = ath9k_hw_common(ah);
+       int r = 0;
 
        if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
-               r = -EOPNOTSUPP;
-               goto bad;
+               ath_print(common, ATH_DBG_FATAL,
+                         "Unsupported device ID: 0x%0x\n",
+                         ah->hw_version.devid);
+               return -EOPNOTSUPP;
        }
 
        ath9k_hw_init_defaults(ah);
        ath9k_hw_init_config(ah);
 
        if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
-               DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
-               r = -EIO;
-               goto bad;
+               ath_print(common, ATH_DBG_FATAL,
+                         "Couldn't reset chip\n");
+               return -EIO;
        }
 
        if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
-               DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
-               r = -EIO;
-               goto bad;
+               ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
+               return -EIO;
        }
 
        if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
@@ -931,16 +871,20 @@ int ath9k_hw_init(struct ath_hw *ah)
                }
        }
 
-       DPRINTF(ah->ah_sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
+       ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
                ah->config.serialize_regmode);
 
+       if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
+               ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
+       else
+               ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
+
        if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
-               DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
-                       "Mac Chip Rev 0x%02x.%x is not supported by "
-                       "this driver\n", ah->hw_version.macVersion,
-                       ah->hw_version.macRev);
-               r = -EOPNOTSUPP;
-               goto bad;
+               ath_print(common, ATH_DBG_FATAL,
+                         "Mac Chip Rev 0x%02x.%x is not supported by "
+                         "this driver\n", ah->hw_version.macVersion,
+                         ah->hw_version.macRev);
+               return -EOPNOTSUPP;
        }
 
        if (AR_SREV_9100(ah)) {
@@ -948,47 +892,69 @@ int ath9k_hw_init(struct ath_hw *ah)
                ah->supp_cals = IQ_MISMATCH_CAL;
                ah->is_pciexpress = false;
        }
+
+       if (AR_SREV_9271(ah))
+               ah->is_pciexpress = false;
+
        ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 
        ath9k_hw_init_cal_settings(ah);
 
        ah->ani_function = ATH9K_ANI_ALL;
-       if (AR_SREV_9280_10_OR_LATER(ah))
+       if (AR_SREV_9280_10_OR_LATER(ah)) {
                ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
+               ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
+               ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
+       } else {
+               ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
+               ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
+       }
 
        ath9k_hw_init_mode_regs(ah);
 
        if (ah->is_pciexpress)
-               ath9k_hw_configpcipowersave(ah, 0);
+               ath9k_hw_configpcipowersave(ah, 0, 0);
        else
                ath9k_hw_disablepcie(ah);
 
+       /* Support for Japan ch.14 (2484) spread */
+       if (AR_SREV_9287_11_OR_LATER(ah)) {
+               INIT_INI_ARRAY(&ah->iniCckfirNormal,
+                      ar9287Common_normal_cck_fir_coeff_92871_1,
+                      ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
+               INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
+                      ar9287Common_japan_2484_cck_fir_coeff_92871_1,
+                      ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
+       }
+
        r = ath9k_hw_post_init(ah);
        if (r)
-               goto bad;
+               return r;
 
        ath9k_hw_init_mode_gain_regs(ah);
-       ath9k_hw_fill_cap_info(ah);
-       ath9k_hw_init_11a_eeprom_fix(ah);
+       r = ath9k_hw_fill_cap_info(ah);
+       if (r)
+               return r;
+
+       ath9k_hw_init_eeprom_fix(ah);
 
        r = ath9k_hw_init_macaddr(ah);
        if (r) {
-               DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
-                       "Failed to initialize MAC address\n");
-               goto bad;
+               ath_print(common, ATH_DBG_FATAL,
+                         "Failed to initialize MAC address\n");
+               return r;
        }
 
-       if (AR_SREV_9285(ah))
+       if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
                ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
        else
                ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 
        ath9k_init_nfcal_hist_buffer(ah);
 
+       common->state = ATH_HW_INITIALIZED;
+
        return 0;
-bad:
-       ath9k_hw_detach(ah);
-       return r;
 }
 
 static void ath9k_hw_init_bb(struct ath_hw *ah,
@@ -1024,6 +990,22 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
        REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 }
 
+static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
+{
+       u32 lcr;
+       u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
+
+       lcr = REG_READ(ah , 0x5100c);
+       lcr |= 0x80;
+
+       REG_WRITE(ah, 0x5100c, lcr);
+       REG_WRITE(ah, 0x51004, (baud_divider >> 8));
+       REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
+
+       lcr &= ~0x80;
+       REG_WRITE(ah, 0x5100c, lcr);
+}
+
 static void ath9k_hw_init_pll(struct ath_hw *ah,
                              struct ath9k_channel *chan)
 {
@@ -1087,6 +1069,26 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
        }
        REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 
+       /* Switch the core clock for ar9271 to 117Mhz */
+       if (AR_SREV_9271(ah)) {
+               if ((pll == 0x142c) || (pll == 0x2850) ) {
+                       udelay(500);
+                       /* set CLKOBS to output AHB clock */
+                       REG_WRITE(ah, 0x7020, 0xe);
+                       /*
+                        * 0x304: 117Mhz, ahb_ratio: 1x1
+                        * 0x306: 40Mhz, ahb_ratio: 1x1
+                        */
+                       REG_WRITE(ah, 0x50040, 0x304);
+                       /*
+                        * makes adjustments for the baud dividor to keep the
+                        * targetted baud rate based on the used core clock.
+                        */
+                       ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
+                                                   AR9271_TARGET_BAUD_RATE);
+               }
+       }
+
        udelay(RTC_PLL_SETTLE_DELAY);
 
        REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
@@ -1104,7 +1106,7 @@ static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
                REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
                            AR_PHY_SWAP_ALT_CHAIN);
        case 0x3:
-               if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
+               if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
                        REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
                        REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
                        break;
@@ -1138,7 +1140,7 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
                AR_IMR_RXORN |
                AR_IMR_BCNMISC;
 
-       if (ah->config.intr_mitigation)
+       if (ah->config.rx_intr_mitigation)
                ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
        else
                ah->mask_reg |= AR_IMR_RXOK;
@@ -1158,39 +1160,32 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
        }
 }
 
-static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
+static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
 {
-       if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
-               DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
-               ah->acktimeout = (u32) -1;
-               return false;
-       } else {
-               REG_RMW_FIELD(ah, AR_TIME_OUT,
-                             AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
-               ah->acktimeout = us;
-               return true;
-       }
+       u32 val = ath9k_hw_mac_to_clks(ah, us);
+       val = min(val, (u32) 0xFFFF);
+       REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
 }
 
-static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
+static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
 {
-       if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
-               DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
-               ah->ctstimeout = (u32) -1;
-               return false;
-       } else {
-               REG_RMW_FIELD(ah, AR_TIME_OUT,
-                             AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
-               ah->ctstimeout = us;
-               return true;
-       }
+       u32 val = ath9k_hw_mac_to_clks(ah, us);
+       val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
+       REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
+}
+
+static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
+{
+       u32 val = ath9k_hw_mac_to_clks(ah, us);
+       val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
+       REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
 }
 
 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
 {
        if (tu > 0xFFFF) {
-               DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
-                       "bad global tx timeout %u\n", tu);
+               ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
+                         "bad global tx timeout %u\n", tu);
                ah->globaltxtimeout = (u32) -1;
                return false;
        } else {
@@ -1200,40 +1195,66 @@ static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
        }
 }
 
-static void ath9k_hw_init_user_settings(struct ath_hw *ah)
+void ath9k_hw_init_global_settings(struct ath_hw *ah)
 {
-       DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
-               ah->misc_mode);
+       struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
+       int acktimeout;
+       int slottime;
+       int sifstime;
+
+       ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
+                 ah->misc_mode);
 
        if (ah->misc_mode != 0)
                REG_WRITE(ah, AR_PCU_MISC,
                          REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
-       if (ah->slottime != (u32) -1)
-               ath9k_hw_setslottime(ah, ah->slottime);
-       if (ah->acktimeout != (u32) -1)
-               ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
-       if (ah->ctstimeout != (u32) -1)
-               ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
+
+       if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
+               sifstime = 16;
+       else
+               sifstime = 10;
+
+       /* As defined by IEEE 802.11-2007 17.3.8.6 */
+       slottime = ah->slottime + 3 * ah->coverage_class;
+       acktimeout = slottime + sifstime;
+
+       /*
+        * Workaround for early ACK timeouts, add an offset to match the
+        * initval's 64us ack timeout value.
+        * This was initially only meant to work around an issue with delayed
+        * BA frames in some implementations, but it has been found to fix ACK
+        * timeout issues in other cases as well.
+        */
+       if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
+               acktimeout += 64 - sifstime - ah->slottime;
+
+       ath9k_hw_setslottime(ah, slottime);
+       ath9k_hw_set_ack_timeout(ah, acktimeout);
+       ath9k_hw_set_cts_timeout(ah, acktimeout);
        if (ah->globaltxtimeout != (u32) -1)
                ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
 }
+EXPORT_SYMBOL(ath9k_hw_init_global_settings);
 
-const char *ath9k_hw_probe(u16 vendorid, u16 devid)
+void ath9k_hw_deinit(struct ath_hw *ah)
 {
-       return vendorid == ATHEROS_VENDOR_ID ?
-               ath9k_hw_devname(devid) : NULL;
-}
+       struct ath_common *common = ath9k_hw_common(ah);
+
+       if (common->state <= ATH_HW_INITIALIZED)
+               goto free_hw;
 
-void ath9k_hw_detach(struct ath_hw *ah)
-{
        if (!AR_SREV_9100(ah))
                ath9k_hw_ani_disable(ah);
 
-       ath9k_hw_rf_free(ah);
        ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
+
+free_hw:
+       if (!AR_SREV_9280_10_OR_LATER(ah))
+               ath9k_hw_rf_free_ext_banks(ah);
        kfree(ah);
        ah = NULL;
 }
+EXPORT_SYMBOL(ath9k_hw_deinit);
 
 /*******/
 /* INI */
@@ -1242,6 +1263,28 @@ void ath9k_hw_detach(struct ath_hw *ah)
 static void ath9k_hw_override_ini(struct ath_hw *ah,
                                  struct ath9k_channel *chan)
 {
+       u32 val;
+
+       if (AR_SREV_9271(ah)) {
+               /*
+                * Enable spectral scan to solution for issues with stuck
+                * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
+                * AR9271 1.1
+                */
+               if (AR_SREV_9271_10(ah)) {
+                       val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
+                             AR_PHY_SPECTRAL_SCAN_ENABLE;
+                       REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
+               }
+               else if (AR_SREV_9271_11(ah))
+                       /*
+                        * change AR_PHY_RF_CTL3 setting to fix MAC issue
+                        * present on AR9271 1.1
+                        */
+                       REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
+               return;
+       }
+
        /*
         * Set the RX_ABORT and RX_DIS and clear if off only after
         * RXE is set for MAC. This prevents frames with corrupted
@@ -1249,11 +1292,23 @@ static void ath9k_hw_override_ini(struct ath_hw *ah,
         */
        REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 
+       if (AR_SREV_9280_10_OR_LATER(ah)) {
+               val = REG_READ(ah, AR_PCU_MISC_MODE2) &
+                              (~AR_PCU_MISC_MODE2_HWWAR1);
+
+               if (AR_SREV_9287_10_OR_LATER(ah))
+                       val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
+
+               REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
+       }
 
        if (!AR_SREV_5416_20_OR_LATER(ah) ||
            AR_SREV_9280_10_OR_LATER(ah))
                return;
-
+       /*
+        * Disable BB clock gating
+        * Necessary to avoid issues on AR5416 2.0
+        */
        REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
 }
 
@@ -1262,28 +1317,29 @@ static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
                              u32 reg, u32 value)
 {
        struct base_eep_header *pBase = &(pEepData->baseEepHeader);
+       struct ath_common *common = ath9k_hw_common(ah);
 
        switch (ah->hw_version.devid) {
        case AR9280_DEVID_PCI:
                if (reg == 0x7894) {
-                       DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
+                       ath_print(common, ATH_DBG_EEPROM,
                                "ini VAL: %x  EEPROM: %x\n", value,
                                (pBase->version & 0xff));
 
                        if ((pBase->version & 0xff) > 0x0a) {
-                               DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
-                                       "PWDCLKIND: %d\n",
-                                       pBase->pwdclkind);
+                               ath_print(common, ATH_DBG_EEPROM,
+                                         "PWDCLKIND: %d\n",
+                                         pBase->pwdclkind);
                                value &= ~AR_AN_TOP2_PWDCLKIND;
                                value |= AR_AN_TOP2_PWDCLKIND &
                                        (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
                        } else {
-                               DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
-                                       "PWDCLKIND Earlier Rev\n");
+                               ath_print(common, ATH_DBG_EEPROM,
+                                         "PWDCLKIND Earlier Rev\n");
                        }
 
-                       DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
-                               "final ini VAL: %x\n", value);
+                       ath_print(common, ATH_DBG_EEPROM,
+                                 "final ini VAL: %x\n", value);
                }
                break;
        }
@@ -1305,11 +1361,21 @@ static void ath9k_olc_init(struct ath_hw *ah)
 {
        u32 i;
 
-       for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
-               ah->originalGain[i] =
-                       MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
-                                       AR_PHY_TX_GAIN);
-       ah->PDADCdelta = 0;
+       if (OLC_FOR_AR9287_10_LATER) {
+               REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
+                               AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
+               ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
+                               AR9287_AN_TXPC0_TXPCMODE,
+                               AR9287_AN_TXPC0_TXPCMODE_S,
+                               AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
+               udelay(100);
+       } else {
+               for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
+                       ah->originalGain[i] =
+                               MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
+                                               AR_PHY_TX_GAIN);
+               ah->PDADCdelta = 0;
+       }
 }
 
 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
@@ -1328,9 +1394,9 @@ static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
 }
 
 static int ath9k_hw_process_ini(struct ath_hw *ah,
-                               struct ath9k_channel *chan,
-                               enum ath9k_ht_macmode macmode)
+                               struct ath9k_channel *chan)
 {
+       struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
        int i, regWrites = 0;
        struct ieee80211_channel *channel = chan->chan;
        u32 modesIndex, freqIndex;
@@ -1422,7 +1488,11 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
                DO_DELAY(regWrites);
        }
 
-       ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
+       ath9k_hw_write_regs(ah, freqIndex, regWrites);
+
+       if (AR_SREV_9271_10(ah))
+               REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
+                               modesIndex, regWrites);
 
        if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
                REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
@@ -1430,22 +1500,22 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
        }
 
        ath9k_hw_override_ini(ah, chan);
-       ath9k_hw_set_regs(ah, chan, macmode);
+       ath9k_hw_set_regs(ah, chan);
        ath9k_hw_init_chain_masks(ah);
 
        if (OLC_FOR_AR9280_20_LATER)
                ath9k_olc_init(ah);
 
        ah->eep_ops->set_txpower(ah, chan,
-                                ath9k_regd_get_ctl(&ah->regulatory, chan),
+                                ath9k_regd_get_ctl(regulatory, chan),
                                 channel->max_antenna_gain * 2,
                                 channel->max_power * 2,
                                 min((u32) MAX_RATE_POWER,
-                                (u32) ah->regulatory.power_limit));
+                                (u32) regulatory->power_limit));
 
        if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
-               DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
-                       "ar5416SetRfRegs failed\n");
+               ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
+                         "ar5416SetRfRegs failed\n");
                return -EIO;
        }
 
@@ -1485,23 +1555,48 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
 {
        u32 regval;
 
+       /*
+        * set AHB_MODE not to do cacheline prefetches
+       */
        regval = REG_READ(ah, AR_AHB_MODE);
        REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
 
+       /*
+        * let mac dma reads be in 128 byte chunks
+        */
        regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
        REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
 
+       /*
+        * Restore TX Trigger Level to its pre-reset value.
+        * The initial value depends on whether aggregation is enabled, and is
+        * adjusted whenever underruns are detected.
+        */
        REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
 
+       /*
+        * let mac dma writes be in 128 byte chunks
+        */
        regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
        REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
 
+       /*
+        * Setup receive FIFO threshold to hold off TX activities
+        */
        REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
 
+       /*
+        * reduce the number of usable entries in PCU TXBUF to avoid
+        * wrap around issues.
+        */
        if (AR_SREV_9285(ah)) {
+               /* For AR9285 the number of Fifos are reduced to half.
+                * So set the usable tx buf size also to half to
+                * avoid data/delimiter underruns
+                */
                REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
                          AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
-       } else {
+       } else if (!AR_SREV_9271(ah)) {
                REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
                          AR_PCU_TXBUF_CTRL_USABLE_SIZE);
        }
@@ -1625,16 +1720,14 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
 
        REG_WRITE(ah, AR_RTC_RC, 0);
        if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
-               DPRINTF(ah->ah_sc, ATH_DBG_RESET,
-                       "RTC stuck in MAC reset\n");
+               ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
+                         "RTC stuck in MAC reset\n");
                return false;
        }
 
        if (!AR_SREV_9100(ah))
                REG_WRITE(ah, AR_RC, 0);
 
-       ath9k_hw_init_pll(ah, NULL);
-
        if (AR_SREV_9100(ah))
                udelay(50);
 
@@ -1646,8 +1739,15 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
        REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
                  AR_RTC_FORCE_WAKE_ON_INT);
 
+       if (!AR_SREV_9100(ah))
+               REG_WRITE(ah, AR_RC, AR_RC_AHB);
+
        REG_WRITE(ah, AR_RTC_RESET, 0);
        udelay(2);
+
+       if (!AR_SREV_9100(ah))
+               REG_WRITE(ah, AR_RC, 0);
+
        REG_WRITE(ah, AR_RTC_RESET, 1);
 
        if (!ath9k_hw_wait(ah,
@@ -1655,7 +1755,8 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
                           AR_RTC_STATUS_M,
                           AR_RTC_STATUS_ON,
                           AH_WAIT_TIMEOUT)) {
-               DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
+               ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
+                         "RTC not waking up\n");
                return false;
        }
 
@@ -1680,8 +1781,7 @@ static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
        }
 }
 
-static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
-                             enum ath9k_ht_macmode macmode)
+static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
 {
        u32 phymode;
        u32 enableDacFifo = 0;
@@ -1700,12 +1800,10 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
                    (chan->chanmode == CHANNEL_G_HT40PLUS))
                        phymode |= AR_PHY_FC_DYN2040_PRI_CH;
 
-               if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
-                       phymode |= AR_PHY_FC_DYN2040_EXT_CH;
        }
        REG_WRITE(ah, AR_PHY_TURBO, phymode);
 
-       ath9k_hw_set11nmac2040(ah, macmode);
+       ath9k_hw_set11nmac2040(ah);
 
        REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
        REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
@@ -1714,7 +1812,7 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
                                struct ath9k_channel *chan)
 {
-       if (OLC_FOR_AR9280_20_LATER) {
+       if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
                if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
                        return false;
        } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
@@ -1731,16 +1829,19 @@ static bool ath9k_hw_chip_reset(struct ath_hw *ah,
 }
 
 static bool ath9k_hw_channel_change(struct ath_hw *ah,
-                                   struct ath9k_channel *chan,
-                                   enum ath9k_ht_macmode macmode)
+                                   struct ath9k_channel *chan)
 {
+       struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
+       struct ath_common *common = ath9k_hw_common(ah);
        struct ieee80211_channel *channel = chan->chan;
        u32 synthDelay, qnum;
+       int r;
 
        for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
                if (ath9k_hw_numtxpending(ah, qnum)) {
-                       DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
-                               "Transmit frames pending on queue %d\n", qnum);
+                       ath_print(common, ATH_DBG_QUEUE,
+                                 "Transmit frames pending on "
+                                 "queue %d\n", qnum);
                        return false;
                }
        }
@@ -1748,29 +1849,26 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
        REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
        if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
                           AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
-               DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
-                       "Could not kill baseband RX\n");
+               ath_print(common, ATH_DBG_FATAL,
+                         "Could not kill baseband RX\n");
                return false;
        }
 
-       ath9k_hw_set_regs(ah, chan, macmode);
+       ath9k_hw_set_regs(ah, chan);
 
-       if (AR_SREV_9280_10_OR_LATER(ah)) {
-               ath9k_hw_ar9280_set_channel(ah, chan);
-       } else {
-               if (!(ath9k_hw_set_channel(ah, chan))) {
-                       DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
-                               "Failed to set channel\n");
-                       return false;
-               }
+       r = ah->ath9k_hw_rf_set_freq(ah, chan);
+       if (r) {
+               ath_print(common, ATH_DBG_FATAL,
+                         "Failed to set channel\n");
+               return false;
        }
 
        ah->eep_ops->set_txpower(ah, chan,
-                            ath9k_regd_get_ctl(&ah->regulatory, chan),
+                            ath9k_regd_get_ctl(regulatory, chan),
                             channel->max_antenna_gain * 2,
                             channel->max_power * 2,
                             min((u32) MAX_RATE_POWER,
-                            (u32) ah->regulatory.power_limit));
+                            (u32) regulatory->power_limit));
 
        synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
        if (IS_CHAN_B(chan))
@@ -1785,10 +1883,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
        if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
                ath9k_hw_set_delta_slope(ah, chan);
 
-       if (AR_SREV_9280_10_OR_LATER(ah))
-               ath9k_hw_9280_spur_mitigate(ah, chan);
-       else
-               ath9k_hw_spur_mitigate(ah, chan);
+       ah->ath9k_hw_spur_mitigate_freq(ah, chan);
 
        if (!chan->oneTimeCalsDone)
                chan->oneTimeCalsDone = true;
@@ -1796,457 +1891,6 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
        return true;
 }
 
-static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
-{
-       int bb_spur = AR_NO_SPUR;
-       int freq;
-       int bin, cur_bin;
-       int bb_spur_off, spur_subchannel_sd;
-       int spur_freq_sd;
-       int spur_delta_phase;
-       int denominator;
-       int upper, lower, cur_vit_mask;
-       int tmp, newVal;
-       int i;
-       int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
-                         AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
-       };
-       int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
-                        AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
-       };
-       int inc[4] = { 0, 100, 0, 0 };
-       struct chan_centers centers;
-
-       int8_t mask_m[123];
-       int8_t mask_p[123];
-       int8_t mask_amt;
-       int tmp_mask;
-       int cur_bb_spur;
-       bool is2GHz = IS_CHAN_2GHZ(chan);
-
-       memset(&mask_m, 0, sizeof(int8_t) * 123);
-       memset(&mask_p, 0, sizeof(int8_t) * 123);
-
-       ath9k_hw_get_channel_centers(ah, chan, &centers);
-       freq = centers.synth_center;
-
-       ah->config.spurmode = SPUR_ENABLE_EEPROM;
-       for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
-               cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
-
-               if (is2GHz)
-                       cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
-               else
-                       cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
-
-               if (AR_NO_SPUR == cur_bb_spur)
-                       break;
-               cur_bb_spur = cur_bb_spur - freq;
-
-               if (IS_CHAN_HT40(chan)) {
-                       if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
-                           (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
-                               bb_spur = cur_bb_spur;
-                               break;
-                       }
-               } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
-                          (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
-                       bb_spur = cur_bb_spur;
-                       break;
-               }
-       }
-
-       if (AR_NO_SPUR == bb_spur) {
-               REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
-                           AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
-               return;
-       } else {
-               REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
-                           AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
-       }
-
-       bin = bb_spur * 320;
-
-       tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
-
-       newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
-                       AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
-                       AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
-                       AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
-       REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
-
-       newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
-                 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
-                 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
-                 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
-                 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
-       REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
-
-       if (IS_CHAN_HT40(chan)) {
-               if (bb_spur < 0) {
-                       spur_subchannel_sd = 1;
-                       bb_spur_off = bb_spur + 10;
-               } else {
-                       spur_subchannel_sd = 0;
-                       bb_spur_off = bb_spur - 10;
-               }
-       } else {
-               spur_subchannel_sd = 0;
-               bb_spur_off = bb_spur;
-       }
-
-       if (IS_CHAN_HT40(chan))
-               spur_delta_phase =
-                       ((bb_spur * 262144) /
-                        10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
-       else
-               spur_delta_phase =
-                       ((bb_spur * 524288) /
-                        10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
-
-       denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
-       spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
-
-       newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
-                 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
-                 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
-       REG_WRITE(ah, AR_PHY_TIMING11, newVal);
-
-       newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
-       REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
-
-       cur_bin = -6000;
-       upper = bin + 100;
-       lower = bin - 100;
-
-       for (i = 0; i < 4; i++) {
-               int pilot_mask = 0;
-               int chan_mask = 0;
-               int bp = 0;
-               for (bp = 0; bp < 30; bp++) {
-                       if ((cur_bin > lower) && (cur_bin < upper)) {
-                               pilot_mask = pilot_mask | 0x1 << bp;
-                               chan_mask = chan_mask | 0x1 << bp;
-                       }
-                       cur_bin += 100;
-               }
-               cur_bin += inc[i];
-               REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
-               REG_WRITE(ah, chan_mask_reg[i], chan_mask);
-       }
-
-       cur_vit_mask = 6100;
-       upper = bin + 120;
-       lower = bin - 120;
-
-       for (i = 0; i < 123; i++) {
-               if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
-
-                       /* workaround for gcc bug #37014 */
-                       volatile int tmp_v = abs(cur_vit_mask - bin);
-
-                       if (tmp_v < 75)
-                               mask_amt = 1;
-                       else
-                               mask_amt = 0;
-                       if (cur_vit_mask < 0)
-                               mask_m[abs(cur_vit_mask / 100)] = mask_amt;
-                       else
-                               mask_p[cur_vit_mask / 100] = mask_amt;
-               }
-               cur_vit_mask -= 100;
-       }
-
-       tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
-               | (mask_m[48] << 26) | (mask_m[49] << 24)
-               | (mask_m[50] << 22) | (mask_m[51] << 20)
-               | (mask_m[52] << 18) | (mask_m[53] << 16)
-               | (mask_m[54] << 14) | (mask_m[55] << 12)
-               | (mask_m[56] << 10) | (mask_m[57] << 8)
-               | (mask_m[58] << 6) | (mask_m[59] << 4)
-               | (mask_m[60] << 2) | (mask_m[61] << 0);
-       REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
-       REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
-
-       tmp_mask = (mask_m[31] << 28)
-               | (mask_m[32] << 26) | (mask_m[33] << 24)
-               | (mask_m[34] << 22) | (mask_m[35] << 20)
-               | (mask_m[36] << 18) | (mask_m[37] << 16)
-               | (mask_m[48] << 14) | (mask_m[39] << 12)
-               | (mask_m[40] << 10) | (mask_m[41] << 8)
-               | (mask_m[42] << 6) | (mask_m[43] << 4)
-               | (mask_m[44] << 2) | (mask_m[45] << 0);
-       REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
-       REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
-
-       tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
-               | (mask_m[18] << 26) | (mask_m[18] << 24)
-               | (mask_m[20] << 22) | (mask_m[20] << 20)
-               | (mask_m[22] << 18) | (mask_m[22] << 16)
-               | (mask_m[24] << 14) | (mask_m[24] << 12)
-               | (mask_m[25] << 10) | (mask_m[26] << 8)
-               | (mask_m[27] << 6) | (mask_m[28] << 4)
-               | (mask_m[29] << 2) | (mask_m[30] << 0);
-       REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
-       REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
-
-       tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
-               | (mask_m[2] << 26) | (mask_m[3] << 24)
-               | (mask_m[4] << 22) | (mask_m[5] << 20)
-               | (mask_m[6] << 18) | (mask_m[7] << 16)
-               | (mask_m[8] << 14) | (mask_m[9] << 12)
-               | (mask_m[10] << 10) | (mask_m[11] << 8)
-               | (mask_m[12] << 6) | (mask_m[13] << 4)
-               | (mask_m[14] << 2) | (mask_m[15] << 0);
-       REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
-       REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
-
-       tmp_mask = (mask_p[15] << 28)
-               | (mask_p[14] << 26) | (mask_p[13] << 24)
-               | (mask_p[12] << 22) | (mask_p[11] << 20)
-               | (mask_p[10] << 18) | (mask_p[9] << 16)
-               | (mask_p[8] << 14) | (mask_p[7] << 12)
-               | (mask_p[6] << 10) | (mask_p[5] << 8)
-               | (mask_p[4] << 6) | (mask_p[3] << 4)
-               | (mask_p[2] << 2) | (mask_p[1] << 0);
-       REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
-       REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
-
-       tmp_mask = (mask_p[30] << 28)
-               | (mask_p[29] << 26) | (mask_p[28] << 24)
-               | (mask_p[27] << 22) | (mask_p[26] << 20)
-               | (mask_p[25] << 18) | (mask_p[24] << 16)
-               | (mask_p[23] << 14) | (mask_p[22] << 12)
-               | (mask_p[21] << 10) | (mask_p[20] << 8)
-               | (mask_p[19] << 6) | (mask_p[18] << 4)
-               | (mask_p[17] << 2) | (mask_p[16] << 0);
-       REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
-       REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
-
-       tmp_mask = (mask_p[45] << 28)
-               | (mask_p[44] << 26) | (mask_p[43] << 24)
-               | (mask_p[42] << 22) | (mask_p[41] << 20)
-               | (mask_p[40] << 18) | (mask_p[39] << 16)
-               | (mask_p[38] << 14) | (mask_p[37] << 12)
-               | (mask_p[36] << 10) | (mask_p[35] << 8)
-               | (mask_p[34] << 6) | (mask_p[33] << 4)
-               | (mask_p[32] << 2) | (mask_p[31] << 0);
-       REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
-       REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
-
-       tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
-               | (mask_p[59] << 26) | (mask_p[58] << 24)
-               | (mask_p[57] << 22) | (mask_p[56] << 20)
-               | (mask_p[55] << 18) | (mask_p[54] << 16)
-               | (mask_p[53] << 14) | (mask_p[52] << 12)
-               | (mask_p[51] << 10) | (mask_p[50] << 8)
-               | (mask_p[49] << 6) | (mask_p[48] << 4)
-               | (mask_p[47] << 2) | (mask_p[46] << 0);
-       REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
-       REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
-}
-
-static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
-{
-       int bb_spur = AR_NO_SPUR;
-       int bin, cur_bin;
-       int spur_freq_sd;
-       int spur_delta_phase;
-       int denominator;
-       int upper, lower, cur_vit_mask;
-       int tmp, new;
-       int i;
-       int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
-                         AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
-       };
-       int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
-                        AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
-       };
-       int inc[4] = { 0, 100, 0, 0 };
-
-       int8_t mask_m[123];
-       int8_t mask_p[123];
-       int8_t mask_amt;
-       int tmp_mask;
-       int cur_bb_spur;
-       bool is2GHz = IS_CHAN_2GHZ(chan);
-
-       memset(&mask_m, 0, sizeof(int8_t) * 123);
-       memset(&mask_p, 0, sizeof(int8_t) * 123);
-
-       for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
-               cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
-               if (AR_NO_SPUR == cur_bb_spur)
-                       break;
-               cur_bb_spur = cur_bb_spur - (chan->channel * 10);
-               if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
-                       bb_spur = cur_bb_spur;
-                       break;
-               }
-       }
-
-       if (AR_NO_SPUR == bb_spur)
-               return;
-
-       bin = bb_spur * 32;
-
-       tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
-       new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
-                    AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
-                    AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
-                    AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
-
-       REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
-
-       new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
-              AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
-              AR_PHY_SPUR_REG_MASK_RATE_SELECT |
-              AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
-              SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
-       REG_WRITE(ah, AR_PHY_SPUR_REG, new);
-
-       spur_delta_phase = ((bb_spur * 524288) / 100) &
-               AR_PHY_TIMING11_SPUR_DELTA_PHASE;
-
-       denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
-       spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
-
-       new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
-              SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
-              SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
-       REG_WRITE(ah, AR_PHY_TIMING11, new);
-
-       cur_bin = -6000;
-       upper = bin + 100;
-       lower = bin - 100;
-
-       for (i = 0; i < 4; i++) {
-               int pilot_mask = 0;
-               int chan_mask = 0;
-               int bp = 0;
-               for (bp = 0; bp < 30; bp++) {
-                       if ((cur_bin > lower) && (cur_bin < upper)) {
-                               pilot_mask = pilot_mask | 0x1 << bp;
-                               chan_mask = chan_mask | 0x1 << bp;
-                       }
-                       cur_bin += 100;
-               }
-               cur_bin += inc[i];
-               REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
-               REG_WRITE(ah, chan_mask_reg[i], chan_mask);
-       }
-
-       cur_vit_mask = 6100;
-       upper = bin + 120;
-       lower = bin - 120;
-
-       for (i = 0; i < 123; i++) {
-               if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
-
-                       /* workaround for gcc bug #37014 */
-                       volatile int tmp_v = abs(cur_vit_mask - bin);
-
-                       if (tmp_v < 75)
-                               mask_amt = 1;
-                       else
-                               mask_amt = 0;
-                       if (cur_vit_mask < 0)
-                               mask_m[abs(cur_vit_mask / 100)] = mask_amt;
-                       else
-                               mask_p[cur_vit_mask / 100] = mask_amt;
-               }
-               cur_vit_mask -= 100;
-       }
-
-       tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
-               | (mask_m[48] << 26) | (mask_m[49] << 24)
-               | (mask_m[50] << 22) | (mask_m[51] << 20)
-               | (mask_m[52] << 18) | (mask_m[53] << 16)
-               | (mask_m[54] << 14) | (mask_m[55] << 12)
-               | (mask_m[56] << 10) | (mask_m[57] << 8)
-               | (mask_m[58] << 6) | (mask_m[59] << 4)
-               | (mask_m[60] << 2) | (mask_m[61] << 0);
-       REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
-       REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
-
-       tmp_mask = (mask_m[31] << 28)
-               | (mask_m[32] << 26) | (mask_m[33] << 24)
-               | (mask_m[34] << 22) | (mask_m[35] << 20)
-               | (mask_m[36] << 18) | (mask_m[37] << 16)
-               | (mask_m[48] << 14) | (mask_m[39] << 12)
-               | (mask_m[40] << 10) | (mask_m[41] << 8)
-               | (mask_m[42] << 6) | (mask_m[43] << 4)
-               | (mask_m[44] << 2) | (mask_m[45] << 0);
-       REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
-       REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
-
-       tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
-               | (mask_m[18] << 26) | (mask_m[18] << 24)
-               | (mask_m[20] << 22) | (mask_m[20] << 20)
-               | (mask_m[22] << 18) | (mask_m[22] << 16)
-               | (mask_m[24] << 14) | (mask_m[24] << 12)
-               | (mask_m[25] << 10) | (mask_m[26] << 8)
-               | (mask_m[27] << 6) | (mask_m[28] << 4)
-               | (mask_m[29] << 2) | (mask_m[30] << 0);
-       REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
-       REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
-
-       tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
-               | (mask_m[2] << 26) | (mask_m[3] << 24)
-               | (mask_m[4] << 22) | (mask_m[5] << 20)
-               | (mask_m[6] << 18) | (mask_m[7] << 16)
-               | (mask_m[8] << 14) | (mask_m[9] << 12)
-               | (mask_m[10] << 10) | (mask_m[11] << 8)
-               | (mask_m[12] << 6) | (mask_m[13] << 4)
-               | (mask_m[14] << 2) | (mask_m[15] << 0);
-       REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
-       REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
-
-       tmp_mask = (mask_p[15] << 28)
-               | (mask_p[14] << 26) | (mask_p[13] << 24)
-               | (mask_p[12] << 22) | (mask_p[11] << 20)
-               | (mask_p[10] << 18) | (mask_p[9] << 16)
-               | (mask_p[8] << 14) | (mask_p[7] << 12)
-               | (mask_p[6] << 10) | (mask_p[5] << 8)
-               | (mask_p[4] << 6) | (mask_p[3] << 4)
-               | (mask_p[2] << 2) | (mask_p[1] << 0);
-       REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
-       REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
-
-       tmp_mask = (mask_p[30] << 28)
-               | (mask_p[29] << 26) | (mask_p[28] << 24)
-               | (mask_p[27] << 22) | (mask_p[26] << 20)
-               | (mask_p[25] << 18) | (mask_p[24] << 16)
-               | (mask_p[23] << 14) | (mask_p[22] << 12)
-               | (mask_p[21] << 10) | (mask_p[20] << 8)
-               | (mask_p[19] << 6) | (mask_p[18] << 4)
-               | (mask_p[17] << 2) | (mask_p[16] << 0);
-       REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
-       REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
-
-       tmp_mask = (mask_p[45] << 28)
-               | (mask_p[44] << 26) | (mask_p[43] << 24)
-               | (mask_p[42] << 22) | (mask_p[41] << 20)
-               | (mask_p[40] << 18) | (mask_p[39] << 16)
-               | (mask_p[38] << 14) | (mask_p[37] << 12)
-               | (mask_p[36] << 10) | (mask_p[35] << 8)
-               | (mask_p[34] << 6) | (mask_p[33] << 4)
-               | (mask_p[32] << 2) | (mask_p[31] << 0);
-       REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
-       REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
-
-       tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
-               | (mask_p[59] << 26) | (mask_p[58] << 24)
-               | (mask_p[57] << 22) | (mask_p[56] << 20)
-               | (mask_p[55] << 18) | (mask_p[54] << 16)
-               | (mask_p[53] << 14) | (mask_p[52] << 12)
-               | (mask_p[51] << 10) | (mask_p[50] << 8)
-               | (mask_p[49] << 6) | (mask_p[48] << 4)
-               | (mask_p[47] << 2) | (mask_p[46] << 0);
-       REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
-       REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
-}
-
 static void ath9k_enable_rfkill(struct ath_hw *ah)
 {
        REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
@@ -2262,21 +1906,21 @@ static void ath9k_enable_rfkill(struct ath_hw *ah)
 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
                    bool bChannelChange)
 {
+       struct ath_common *common = ath9k_hw_common(ah);
        u32 saveLedState;
-       struct ath_softc *sc = ah->ah_sc;
        struct ath9k_channel *curchan = ah->curchan;
        u32 saveDefAntenna;
        u32 macStaId1;
+       u64 tsf = 0;
        int i, rx_chainmask, r;
 
-       ah->extprotspacing = sc->ht_extprotspacing;
-       ah->txchainmask = sc->tx_chainmask;
-       ah->rxchainmask = sc->rx_chainmask;
+       ah->txchainmask = common->tx_chainmask;
+       ah->rxchainmask = common->rx_chainmask;
 
        if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
                return -EIO;
 
-       if (curchan)
+       if (curchan && !ah->chip_fullsleep)
                ath9k_hw_getnf(ah, curchan);
 
        if (bChannelChange &&
@@ -2285,10 +1929,10 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
            (chan->channel != ah->curchan->channel) &&
            ((chan->channelFlags & CHANNEL_ALL) ==
             (ah->curchan->channelFlags & CHANNEL_ALL)) &&
-           (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
-                                  !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
+            !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
+            IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
 
-               if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
+               if (ath9k_hw_channel_change(ah, chan)) {
                        ath9k_hw_loadnf(ah, ah->curchan);
                        ath9k_hw_start_nfcal(ah);
                        return 0;
@@ -2301,21 +1945,44 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
 
        macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
 
+       /* For chips on which RTC reset is done, save TSF before it gets cleared */
+       if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
+               tsf = ath9k_hw_gettsf64(ah);
+
        saveLedState = REG_READ(ah, AR_CFG_LED) &
                (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
                 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
 
        ath9k_hw_mark_phy_inactive(ah);
 
+       if (AR_SREV_9271(ah) && ah->htc_reset_init) {
+               REG_WRITE(ah,
+                         AR9271_RESET_POWER_DOWN_CONTROL,
+                         AR9271_RADIO_RF_RST);
+               udelay(50);
+       }
+
        if (!ath9k_hw_chip_reset(ah, chan)) {
-               DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
+               ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
                return -EINVAL;
        }
 
+       if (AR_SREV_9271(ah) && ah->htc_reset_init) {
+               ah->htc_reset_init = false;
+               REG_WRITE(ah,
+                         AR9271_RESET_POWER_DOWN_CONTROL,
+                         AR9271_GATE_MAC_CTL);
+               udelay(50);
+       }
+
+       /* Restore TSF */
+       if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
+               ath9k_hw_settsf64(ah, tsf);
+
        if (AR_SREV_9280_10_OR_LATER(ah))
                REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
 
-       if (AR_SREV_9287_10_OR_LATER(ah)) {
+       if (AR_SREV_9287_12_OR_LATER(ah)) {
                /* Enable ASYNC FIFO */
                REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
                                AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
@@ -2325,7 +1992,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
                REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
                                AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
        }
-       r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
+       r = ath9k_hw_process_ini(ah, chan);
        if (r)
                return r;
 
@@ -2349,17 +2016,11 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
        if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
                ath9k_hw_set_delta_slope(ah, chan);
 
-       if (AR_SREV_9280_10_OR_LATER(ah))
-               ath9k_hw_9280_spur_mitigate(ah, chan);
-       else
-               ath9k_hw_spur_mitigate(ah, chan);
-
+       ah->ath9k_hw_spur_mitigate_freq(ah, chan);
        ah->eep_ops->set_board_values(ah, chan);
 
-       ath9k_hw_decrease_chain_power(ah, chan);
-
-       REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
-       REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
+       REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
+       REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
                  | macStaId1
                  | AR_STA_ID1_RTS_USE_DEF
                  | (ah->config.
@@ -2367,24 +2028,19 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
                  | ah->sta_id1_defaults);
        ath9k_hw_set_operating_mode(ah, ah->opmode);
 
-       REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
-       REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
+       ath_hw_setbssidmask(common);
 
        REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
 
-       REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
-       REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
-                 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
+       ath9k_hw_write_associd(ah);
 
        REG_WRITE(ah, AR_ISR, ~0);
 
        REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
 
-       if (AR_SREV_9280_10_OR_LATER(ah))
-               ath9k_hw_ar9280_set_channel(ah, chan);
-       else
-               if (!(ath9k_hw_set_channel(ah, chan)))
-                       return -EIO;
+       r = ah->ath9k_hw_rf_set_freq(ah, chan);
+       if (r)
+               return r;
 
        for (i = 0; i < AR_NUM_DCU; i++)
                REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
@@ -2399,9 +2055,9 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
        if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
                ath9k_enable_rfkill(ah);
 
-       ath9k_hw_init_user_settings(ah);
+       ath9k_hw_init_global_settings(ah);
 
-       if (AR_SREV_9287_10_OR_LATER(ah)) {
+       if (AR_SREV_9287_12_OR_LATER(ah)) {
                REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
                          AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
                REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
@@ -2417,7 +2073,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
                REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
                              AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
        }
-       if (AR_SREV_9287_10_OR_LATER(ah)) {
+       if (AR_SREV_9287_12_OR_LATER(ah)) {
                REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
                                AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
        }
@@ -2429,7 +2085,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
 
        REG_WRITE(ah, AR_OBS, 8);
 
-       if (ah->config.intr_mitigation) {
+       if (ah->config.rx_intr_mitigation) {
                REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
                REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
        }
@@ -2447,27 +2103,38 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
 
        REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
 
+       /*
+        * For big endian systems turn on swapping for descriptors
+        */
        if (AR_SREV_9100(ah)) {
                u32 mask;
                mask = REG_READ(ah, AR_CFG);
                if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
-                       DPRINTF(ah->ah_sc, ATH_DBG_RESET,
+                       ath_print(common, ATH_DBG_RESET,
                                "CFG Byte Swap Set 0x%x\n", mask);
                } else {
                        mask =
                                INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
                        REG_WRITE(ah, AR_CFG, mask);
-                       DPRINTF(ah->ah_sc, ATH_DBG_RESET,
+                       ath_print(common, ATH_DBG_RESET,
                                "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
                }
        } else {
+               /* Configure AR9271 target WLAN */
+                if (AR_SREV_9271(ah))
+                       REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
 #ifdef __BIG_ENDIAN
-               REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
+                else
+                       REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
 #endif
        }
 
+       if (ah->btcoex_hw.enabled)
+               ath9k_hw_btcoex_enable(ah);
+
        return 0;
 }
+EXPORT_SYMBOL(ath9k_hw_reset);
 
 /************************/
 /* Key Cache Management */
@@ -2478,8 +2145,8 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
        u32 keyType;
 
        if (entry >= ah->caps.keycache_size) {
-               DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
-                       "keychache entry %u out of range\n", entry);
+               ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
+                         "keychache entry %u out of range\n", entry);
                return false;
        }
 
@@ -2504,19 +2171,17 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
 
        }
 
-       if (ah->curchan == NULL)
-               return true;
-
        return true;
 }
+EXPORT_SYMBOL(ath9k_hw_keyreset);
 
 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
 {
        u32 macHi, macLo;
 
        if (entry >= ah->caps.keycache_size) {
-               DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
-                       "keychache entry %u out of range\n", entry);
+               ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
+                         "keychache entry %u out of range\n", entry);
                return false;
        }
 
@@ -2537,18 +2202,20 @@ bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
 
        return true;
 }
+EXPORT_SYMBOL(ath9k_hw_keysetmac);
 
 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
                                 const struct ath9k_keyval *k,
                                 const u8 *mac)
 {
        const struct ath9k_hw_capabilities *pCap = &ah->caps;
+       struct ath_common *common = ath9k_hw_common(ah);
        u32 key0, key1, key2, key3, key4;
        u32 keyType;
 
        if (entry >= pCap->keycache_size) {
-               DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
-                       "keycache entry %u out of range\n", entry);
+               ath_print(common, ATH_DBG_FATAL,
+                         "keycache entry %u out of range\n", entry);
                return false;
        }
 
@@ -2558,9 +2225,9 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
                break;
        case ATH9K_CIPHER_AES_CCM:
                if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
-                       DPRINTF(ah->ah_sc, ATH_DBG_ANY,
-                               "AES-CCM not supported by mac rev 0x%x\n",
-                               ah->hw_version.macRev);
+                       ath_print(common, ATH_DBG_ANY,
+                                 "AES-CCM not supported by mac rev 0x%x\n",
+                                 ah->hw_version.macRev);
                        return false;
                }
                keyType = AR_KEYTABLE_TYPE_CCM;
@@ -2569,15 +2236,15 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
                keyType = AR_KEYTABLE_TYPE_TKIP;
                if (ATH9K_IS_MIC_ENABLED(ah)
                    && entry + 64 >= pCap->keycache_size) {
-                       DPRINTF(ah->ah_sc, ATH_DBG_ANY,
-                               "entry %u inappropriate for TKIP\n", entry);
+                       ath_print(common, ATH_DBG_ANY,
+                                 "entry %u inappropriate for TKIP\n", entry);
                        return false;
                }
                break;
        case ATH9K_CIPHER_WEP:
                if (k->kv_len < WLAN_KEY_LEN_WEP40) {
-                       DPRINTF(ah->ah_sc, ATH_DBG_ANY,
-                               "WEP key length %u too small\n", k->kv_len);
+                       ath_print(common, ATH_DBG_ANY,
+                                 "WEP key length %u too small\n", k->kv_len);
                        return false;
                }
                if (k->kv_len <= WLAN_KEY_LEN_WEP40)
@@ -2591,8 +2258,8 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
                keyType = AR_KEYTABLE_TYPE_CLR;
                break;
        default:
-               DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
-                       "cipher %u not supported\n", k->kv_type);
+               ath_print(common, ATH_DBG_FATAL,
+                         "cipher %u not supported\n", k->kv_type);
                return false;
        }
 
@@ -2734,6 +2401,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
 
        return true;
 }
+EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
 
 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
 {
@@ -2744,6 +2412,7 @@ bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
        }
        return false;
 }
+EXPORT_SYMBOL(ath9k_hw_keyisvalid);
 
 /******************************/
 /* Power Management (Chipset) */
@@ -2758,8 +2427,9 @@ static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
                if (!AR_SREV_9100(ah))
                        REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
 
-               REG_CLR_BIT(ah, (AR_RTC_RESET),
-                           AR_RTC_RESET_EN);
+               if(!AR_SREV_5416(ah))
+                       REG_CLR_BIT(ah, (AR_RTC_RESET),
+                                   AR_RTC_RESET_EN);
        }
 }
 
@@ -2791,6 +2461,7 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
                                           ATH9K_RESET_POWER_ON) != true) {
                                return false;
                        }
+                       ath9k_hw_init_pll(ah, NULL);
                }
                if (AR_SREV_9100(ah))
                        REG_SET_BIT(ah, AR_RTC_RESET,
@@ -2809,8 +2480,9 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
                                    AR_RTC_FORCE_WAKE_EN);
                }
                if (i == 0) {
-                       DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
-                               "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
+                       ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
+                                 "Failed to wakeup in %uus\n",
+                                 POWER_UP_TIME / 20);
                        return false;
                }
        }
@@ -2820,9 +2492,9 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
        return true;
 }
 
-static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
-                                    enum ath9k_power_mode mode)
+bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
 {
+       struct ath_common *common = ath9k_hw_common(ah);
        int status = true, setChip = true;
        static const char *modes[] = {
                "AWAKE",
@@ -2834,8 +2506,8 @@ static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
        if (ah->power_mode == mode)
                return status;
 
-       DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
-               modes[ah->power_mode], modes[mode]);
+       ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
+                 modes[ah->power_mode], modes[mode]);
 
        switch (mode) {
        case ATH9K_PM_AWAKE:
@@ -2849,59 +2521,15 @@ static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
                ath9k_set_power_network_sleep(ah, setChip);
                break;
        default:
-               DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
-                       "Unknown power mode %u\n", mode);
+               ath_print(common, ATH_DBG_FATAL,
+                         "Unknown power mode %u\n", mode);
                return false;
        }
        ah->power_mode = mode;
 
        return status;
 }
-
-bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
-{
-       unsigned long flags;
-       bool ret;
-
-       spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
-       ret = ath9k_hw_setpower_nolock(ah, mode);
-       spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
-
-       return ret;
-}
-
-void ath9k_ps_wakeup(struct ath_softc *sc)
-{
-       unsigned long flags;
-
-       spin_lock_irqsave(&sc->sc_pm_lock, flags);
-       if (++sc->ps_usecount != 1)
-               goto unlock;
-
-       ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
-
- unlock:
-       spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
-}
-
-void ath9k_ps_restore(struct ath_softc *sc)
-{
-       unsigned long flags;
-
-       spin_lock_irqsave(&sc->sc_pm_lock, flags);
-       if (--sc->ps_usecount != 0)
-               goto unlock;
-
-       if (sc->ps_enabled &&
-           !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
-                             SC_OP_WAIT_FOR_CAB |
-                             SC_OP_WAIT_FOR_PSPOLL_DATA |
-                             SC_OP_WAIT_FOR_TX_ACK)))
-               ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
-
- unlock:
-       spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
-}
+EXPORT_SYMBOL(ath9k_hw_setpower);
 
 /*
  * Helper for ASPM support.
@@ -2912,9 +2540,10 @@ void ath9k_ps_restore(struct ath_softc *sc)
  * Programming the SerDes must go through the same 288 bit serial shift
  * register as the other analog registers.  Hence the 9 writes.
  */
-void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
+void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
 {
        u8 i;
+       u32 val;
 
        if (ah->is_pciexpress != true)
                return;
@@ -2924,86 +2553,116 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
                return;
 
        /* Nothing to do on restore for 11N */
-       if (restore)
-               return;
-
-       if (AR_SREV_9280_20_OR_LATER(ah)) {
-               /*
-                * AR9280 2.0 or later chips use SerDes values from the
-                * initvals.h initialized depending on chipset during
-                * ath9k_hw_init()
-                */
-               for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
-                       REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
-                                 INI_RA(&ah->iniPcieSerdes, i, 1));
-               }
-       } else if (AR_SREV_9280(ah) &&
-                  (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
-               REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
-               REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
+       if (!restore) {
+               if (AR_SREV_9280_20_OR_LATER(ah)) {
+                       /*
+                        * AR9280 2.0 or later chips use SerDes values from the
+                        * initvals.h initialized depending on chipset during
+                        * ath9k_hw_init()
+                        */
+                       for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
+                               REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
+                                         INI_RA(&ah->iniPcieSerdes, i, 1));
+                       }
+               } else if (AR_SREV_9280(ah) &&
+                          (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
+                       REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
+                       REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
+
+                       /* RX shut off when elecidle is asserted */
+                       REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
+                       REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
+                       REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
+
+                       /* Shut off CLKREQ active in L1 */
+                       if (ah->config.pcie_clock_req)
+                               REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
+                       else
+                               REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
 
-               /* RX shut off when elecidle is asserted */
-               REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
-               REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
-               REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
+                       REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
+                       REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
+                       REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
 
-               /* Shut off CLKREQ active in L1 */
-               if (ah->config.pcie_clock_req)
-                       REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
-               else
-                       REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
+                       /* Load the new settings */
+                       REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 
-               REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
-               REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
-               REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
+               } else {
+                       REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
+                       REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 
-               /* Load the new settings */
-               REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
+                       /* RX shut off when elecidle is asserted */
+                       REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
+                       REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
+                       REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
 
-       } else {
-               REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
-               REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
+                       /*
+                        * Ignore ah->ah_config.pcie_clock_req setting for
+                        * pre-AR9280 11n
+                        */
+                       REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
 
-               /* RX shut off when elecidle is asserted */
-               REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
-               REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
-               REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
+                       REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
+                       REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
+                       REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
 
-               /*
-                * Ignore ah->ah_config.pcie_clock_req setting for
-                * pre-AR9280 11n
-                */
-               REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
+                       /* Load the new settings */
+                       REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
+               }
 
-               REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
-               REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
-               REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
+               udelay(1000);
 
-               /* Load the new settings */
-               REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
-       }
+               /* set bit 19 to allow forcing of pcie core into L1 state */
+               REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 
-       udelay(1000);
+               /* Several PCIe massages to ensure proper behaviour */
+               if (ah->config.pcie_waen) {
+                       val = ah->config.pcie_waen;
+                       if (!power_off)
+                               val &= (~AR_WA_D3_L1_DISABLE);
+               } else {
+                       if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
+                           AR_SREV_9287(ah)) {
+                               val = AR9285_WA_DEFAULT;
+                               if (!power_off)
+                                       val &= (~AR_WA_D3_L1_DISABLE);
+                       } else if (AR_SREV_9280(ah)) {
+                               /*
+                                * On AR9280 chips bit 22 of 0x4004 needs to be
+                                * set otherwise card may disappear.
+                                */
+                               val = AR9280_WA_DEFAULT;
+                               if (!power_off)
+                                       val &= (~AR_WA_D3_L1_DISABLE);
+                       } else
+                               val = AR_WA_DEFAULT;
+               }
 
-       /* set bit 19 to allow forcing of pcie core into L1 state */
-       REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
+               REG_WRITE(ah, AR_WA, val);
+       }
 
-       /* Several PCIe massages to ensure proper behaviour */
-       if (ah->config.pcie_waen) {
-               REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
-       } else {
-               if (AR_SREV_9285(ah))
-                       REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
+       if (power_off) {
                /*
-                * On AR9280 chips bit 22 of 0x4004 needs to be set to
-                * otherwise card may disappear.
+                * Set PCIe workaround bits
+                * bit 14 in WA register (disable L1) should only
+                * be set when device enters D3 and be cleared
+                * when device comes back to D0.
                 */
-               else if (AR_SREV_9280(ah))
-                       REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
-               else
-                       REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
+               if (ah->config.pcie_waen) {
+                       if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
+                               REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
+               } else {
+                       if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
+                             AR_SREV_9287(ah)) &&
+                            (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
+                           (AR_SREV_9280(ah) &&
+                            (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
+                               REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
+                       }
+               }
        }
 }
+EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
 
 /**********************/
 /* Interrupt Handling */
@@ -3027,6 +2686,7 @@ bool ath9k_hw_intrpend(struct ath_hw *ah)
 
        return false;
 }
+EXPORT_SYMBOL(ath9k_hw_intrpend);
 
 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
 {
@@ -3035,6 +2695,7 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
        struct ath9k_hw_capabilities *pCap = &ah->caps;
        u32 sync_cause = 0;
        bool fatal_int = false;
+       struct ath_common *common = ath9k_hw_common(ah);
 
        if (!AR_SREV_9100(ah)) {
                if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
@@ -3084,7 +2745,7 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
 
                *masked = isr & ATH9K_INT_COMMON;
 
-               if (ah->config.intr_mitigation) {
+               if (ah->config.rx_intr_mitigation) {
                        if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
                                *masked |= ATH9K_INT_RX;
                }
@@ -3108,8 +2769,8 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
                }
 
                if (isr & AR_ISR_RXORN) {
-                       DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
-                               "receive FIFO overrun interrupt\n");
+                       ath_print(common, ATH_DBG_INTERRUPT,
+                                 "receive FIFO overrun interrupt\n");
                }
 
                if (!AR_SREV_9100(ah)) {
@@ -3126,6 +2787,23 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
        if (AR_SREV_9100(ah))
                return true;
 
+       if (isr & AR_ISR_GENTMR) {
+               u32 s5_s;
+
+               s5_s = REG_READ(ah, AR_ISR_S5_S);
+               if (isr & AR_ISR_GENTMR) {
+                       ah->intr_gen_timer_trigger =
+                               MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
+
+                       ah->intr_gen_timer_thresh =
+                               MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
+
+                       if (ah->intr_gen_timer_trigger)
+                               *masked |= ATH9K_INT_GENTIMER;
+
+               }
+       }
+
        if (sync_cause) {
                fatal_int =
                        (sync_cause &
@@ -3134,25 +2812,25 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
 
                if (fatal_int) {
                        if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
-                               DPRINTF(ah->ah_sc, ATH_DBG_ANY,
-                                       "received PCI FATAL interrupt\n");
+                               ath_print(common, ATH_DBG_ANY,
+                                         "received PCI FATAL interrupt\n");
                        }
                        if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
-                               DPRINTF(ah->ah_sc, ATH_DBG_ANY,
-                                       "received PCI PERR interrupt\n");
+                               ath_print(common, ATH_DBG_ANY,
+                                         "received PCI PERR interrupt\n");
                        }
                        *masked |= ATH9K_INT_FATAL;
                }
                if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
-                       DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
-                               "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
+                       ath_print(common, ATH_DBG_INTERRUPT,
+                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
                        REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
                        REG_WRITE(ah, AR_RC, 0);
                        *masked |= ATH9K_INT_FATAL;
                }
                if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
-                       DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
-                               "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
+                       ath_print(common, ATH_DBG_INTERRUPT,
+                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
                }
 
                REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
@@ -3161,17 +2839,19 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
 
        return true;
 }
+EXPORT_SYMBOL(ath9k_hw_getisr);
 
 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
 {
        u32 omask = ah->mask_reg;
        u32 mask, mask2;
        struct ath9k_hw_capabilities *pCap = &ah->caps;
+       struct ath_common *common = ath9k_hw_common(ah);
 
-       DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
+       ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
 
        if (omask & ATH9K_INT_GLOBAL) {
-               DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
+               ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
                REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
                (void) REG_READ(ah, AR_IER);
                if (!AR_SREV_9100(ah)) {
@@ -3198,7 +2878,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
        }
        if (ints & ATH9K_INT_RX) {
                mask |= AR_IMR_RXERR;
-               if (ah->config.intr_mitigation)
+               if (ah->config.rx_intr_mitigation)
                        mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
                else
                        mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
@@ -3228,7 +2908,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
                        mask2 |= AR_IMR_S2_CST;
        }
 
-       DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
+       ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
        REG_WRITE(ah, AR_IMR, mask);
        mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
                                           AR_IMR_S2_DTIM |
@@ -3248,7 +2928,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
        }
 
        if (ints & ATH9K_INT_GLOBAL) {
-               DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
+               ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
                REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
                if (!AR_SREV_9100(ah)) {
                        REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
@@ -3261,12 +2941,13 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
                        REG_WRITE(ah, AR_INTR_SYNC_MASK,
                                  AR_INTR_SYNC_DEFAULT);
                }
-               DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
-                        REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
+               ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
+                         REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
        }
 
        return omask;
 }
+EXPORT_SYMBOL(ath9k_hw_set_interrupts);
 
 /*******************/
 /* Beacon Handling */
@@ -3309,9 +2990,9 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
                        AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
                break;
        default:
-               DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
-                       "%s: unsupported opmode: %d\n",
-                       __func__, ah->opmode);
+               ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
+                         "%s: unsupported opmode: %d\n",
+                         __func__, ah->opmode);
                return;
                break;
        }
@@ -3323,18 +3004,19 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
 
        beacon_period &= ~ATH9K_BEACON_ENA;
        if (beacon_period & ATH9K_BEACON_RESET_TSF) {
-               beacon_period &= ~ATH9K_BEACON_RESET_TSF;
                ath9k_hw_reset_tsf(ah);
        }
 
        REG_SET_BIT(ah, AR_TIMER_MODE, flags);
 }
+EXPORT_SYMBOL(ath9k_hw_beaconinit);
 
 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
                                    const struct ath9k_beacon_state *bs)
 {
        u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
        struct ath9k_hw_capabilities *pCap = &ah->caps;
+       struct ath_common *common = ath9k_hw_common(ah);
 
        REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
 
@@ -3360,10 +3042,10 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
        else
                nextTbtt = bs->bs_nexttbtt;
 
-       DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
-       DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
-       DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
-       DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
+       ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
+       ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
+       ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
+       ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
 
        REG_WRITE(ah, AR_NEXT_DTIM,
                  TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
@@ -3391,38 +3073,49 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
        /* TSF Out of Range Threshold */
        REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
 }
+EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
 
 /*******************/
 /* HW Capabilities */
 /*******************/
 
-void ath9k_hw_fill_cap_info(struct ath_hw *ah)
+int ath9k_hw_fill_cap_info(struct ath_hw *ah)
 {
        struct ath9k_hw_capabilities *pCap = &ah->caps;
+       struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
+       struct ath_common *common = ath9k_hw_common(ah);
+       struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
+
        u16 capField = 0, eeval;
 
        eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
-       ah->regulatory.current_rd = eeval;
+       regulatory->current_rd = eeval;
 
        eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
        if (AR_SREV_9285_10_OR_LATER(ah))
                eeval |= AR9285_RDEXT_DEFAULT;
-       ah->regulatory.current_rd_ext = eeval;
+       regulatory->current_rd_ext = eeval;
 
        capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
 
        if (ah->opmode != NL80211_IFTYPE_AP &&
            ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
-               if (ah->regulatory.current_rd == 0x64 ||
-                   ah->regulatory.current_rd == 0x65)
-                       ah->regulatory.current_rd += 5;
-               else if (ah->regulatory.current_rd == 0x41)
-                       ah->regulatory.current_rd = 0x43;
-               DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
-                       "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
+               if (regulatory->current_rd == 0x64 ||
+                   regulatory->current_rd == 0x65)
+                       regulatory->current_rd += 5;
+               else if (regulatory->current_rd == 0x41)
+                       regulatory->current_rd = 0x43;
+               ath_print(common, ATH_DBG_REGULATORY,
+                         "regdomain mapped to 0x%x\n", regulatory->current_rd);
        }
 
        eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
+       if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
+               ath_print(common, ATH_DBG_FATAL,
+                         "no band has been marked as supported in EEPROM.\n");
+               return -EINVAL;
+       }
+
        bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
 
        if (eeval & AR5416_OPFLAGS_11A) {
@@ -3456,10 +3149,17 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
        }
 
        pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
+       /*
+        * For AR9271 we will temporarilly uses the rx chainmax as read from
+        * the EEPROM.
+        */
        if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
-           !(eeval & AR5416_OPFLAGS_11A))
+           !(eeval & AR5416_OPFLAGS_11A) &&
+           !(AR_SREV_9271(ah)))
+               /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
                pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
        else
+               /* Use rx_chainmask from EEPROM. */
                pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
 
        if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
@@ -3502,7 +3202,11 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
                pCap->keycache_size = AR_KEYTABLE_SIZE;
 
        pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
-       pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
+
+       if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
+               pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
+       else
+               pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
 
        if (AR_SREV_9285_10_OR_LATER(ah))
                pCap->num_gpio_pins = AR9285_NUM_GPIO;
@@ -3532,22 +3236,14 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
        }
 #endif
 
-       if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
-           (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
-           (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
-           (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
-           (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
-           (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
-               pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
-       else
-               pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
+       pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
 
        if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
                pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
        else
                pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
 
-       if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
+       if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
                pCap->reg_cap =
                        AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
                        AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
@@ -3559,23 +3255,38 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
                        AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
        }
 
-       pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
+       /* Advertise midband for AR5416 with FCC midband set in eeprom */
+       if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
+           AR_SREV_5416(ah))
+               pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
 
        pCap->num_antcfg_5ghz =
                ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
        pCap->num_antcfg_2ghz =
                ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
 
-       if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
-               pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
-               ah->btactive_gpio = 6;
-               ah->wlanactive_gpio = 5;
+       if (AR_SREV_9280_10_OR_LATER(ah) &&
+           ath9k_hw_btcoex_supported(ah)) {
+               btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
+               btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
+
+               if (AR_SREV_9285(ah)) {
+                       btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
+                       btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
+               } else {
+                       btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
+               }
+       } else {
+               btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
        }
+
+       return 0;
 }
 
 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
                            u32 capability, u32 *result)
 {
+       struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
        switch (type) {
        case ATH9K_CAP_CIPHER:
                switch (capability) {
@@ -3624,13 +3335,13 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
                case 0:
                        return 0;
                case 1:
-                       *result = ah->regulatory.power_limit;
+                       *result = regulatory->power_limit;
                        return 0;
                case 2:
-                       *result = ah->regulatory.max_power_level;
+                       *result = regulatory->max_power_level;
                        return 0;
                case 3:
-                       *result = ah->regulatory.tp_scale;
+                       *result = regulatory->tp_scale;
                        return 0;
                }
                return false;
@@ -3642,6 +3353,7 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
                return false;
        }
 }
+EXPORT_SYMBOL(ath9k_hw_getcapability);
 
 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
                            u32 capability, u32 setting, int *status)
@@ -3675,6 +3387,7 @@ bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
                return false;
        }
 }
+EXPORT_SYMBOL(ath9k_hw_setcapability);
 
 /****************************/
 /* GPIO / RFKILL / Antennae */
@@ -3712,7 +3425,7 @@ void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
 {
        u32 gpio_shift;
 
-       ASSERT(gpio < ah->caps.num_gpio_pins);
+       BUG_ON(gpio >= ah->caps.num_gpio_pins);
 
        gpio_shift = gpio << 1;
 
@@ -3721,6 +3434,7 @@ void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
                (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
                (AR_GPIO_OE_OUT_DRV << gpio_shift));
 }
+EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
 
 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
 {
@@ -3739,6 +3453,7 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
        else
                return MS_REG_READ(AR, gpio) != 0;
 }
+EXPORT_SYMBOL(ath9k_hw_gpio_get);
 
 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
                         u32 ah_signal_type)
@@ -3754,67 +3469,26 @@ void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
                (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
                (AR_GPIO_OE_OUT_DRV << gpio_shift));
 }
+EXPORT_SYMBOL(ath9k_hw_cfg_output);
 
 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
 {
        REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
                AR_GPIO_BIT(gpio));
 }
+EXPORT_SYMBOL(ath9k_hw_set_gpio);
 
 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
 {
        return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
 }
+EXPORT_SYMBOL(ath9k_hw_getdefantenna);
 
 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
 {
        REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
 }
-
-bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
-                              enum ath9k_ant_setting settings,
-                              struct ath9k_channel *chan,
-                              u8 *tx_chainmask,
-                              u8 *rx_chainmask,
-                              u8 *antenna_cfgd)
-{
-       static u8 tx_chainmask_cfg, rx_chainmask_cfg;
-
-       if (AR_SREV_9280(ah)) {
-               if (!tx_chainmask_cfg) {
-
-                       tx_chainmask_cfg = *tx_chainmask;
-                       rx_chainmask_cfg = *rx_chainmask;
-               }
-
-               switch (settings) {
-               case ATH9K_ANT_FIXED_A:
-                       *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
-                       *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
-                       *antenna_cfgd = true;
-                       break;
-               case ATH9K_ANT_FIXED_B:
-                       if (ah->caps.tx_chainmask >
-                           ATH9K_ANTENNA1_CHAINMASK) {
-                               *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
-                       }
-                       *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
-                       *antenna_cfgd = true;
-                       break;
-               case ATH9K_ANT_VARIABLE:
-                       *tx_chainmask = tx_chainmask_cfg;
-                       *rx_chainmask = rx_chainmask_cfg;
-                       *antenna_cfgd = true;
-                       break;
-               default:
-                       break;
-               }
-       } else {
-               ah->diversity_control = settings;
-       }
-
-       return true;
-}
+EXPORT_SYMBOL(ath9k_hw_setantenna);
 
 /*********************/
 /* General Operation */
@@ -3832,12 +3506,14 @@ u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
 
        return bits;
 }
+EXPORT_SYMBOL(ath9k_hw_getrxfilter);
 
 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
 {
        u32 phybits;
 
-       REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
+       REG_WRITE(ah, AR_RX_FILTER, bits);
+
        phybits = 0;
        if (bits & ATH9K_RX_FILTER_PHYRADAR)
                phybits |= AR_PHY_ERR_RADAR;
@@ -3852,63 +3528,76 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
                REG_WRITE(ah, AR_RXCFG,
                          REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
 }
+EXPORT_SYMBOL(ath9k_hw_setrxfilter);
 
 bool ath9k_hw_phy_disable(struct ath_hw *ah)
 {
-       return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
+       if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
+               return false;
+
+       ath9k_hw_init_pll(ah, NULL);
+       return true;
 }
+EXPORT_SYMBOL(ath9k_hw_phy_disable);
 
 bool ath9k_hw_disable(struct ath_hw *ah)
 {
        if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
                return false;
 
-       return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
+       if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
+               return false;
+
+       ath9k_hw_init_pll(ah, NULL);
+       return true;
 }
+EXPORT_SYMBOL(ath9k_hw_disable);
 
 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
 {
+       struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
        struct ath9k_channel *chan = ah->curchan;
        struct ieee80211_channel *channel = chan->chan;
 
-       ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
+       regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
 
        ah->eep_ops->set_txpower(ah, chan,
-                                ath9k_regd_get_ctl(&ah->regulatory, chan),
+                                ath9k_regd_get_ctl(regulatory, chan),
                                 channel->max_antenna_gain * 2,
                                 channel->max_power * 2,
                                 min((u32) MAX_RATE_POWER,
-                                (u32) ah->regulatory.power_limit));
+                                (u32) regulatory->power_limit));
 }
+EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
 
 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
 {
-       memcpy(ah->macaddr, mac, ETH_ALEN);
+       memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
 }
+EXPORT_SYMBOL(ath9k_hw_setmac);
 
 void ath9k_hw_setopmode(struct ath_hw *ah)
 {
        ath9k_hw_set_operating_mode(ah, ah->opmode);
 }
+EXPORT_SYMBOL(ath9k_hw_setopmode);
 
 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
 {
        REG_WRITE(ah, AR_MCAST_FIL0, filter0);
        REG_WRITE(ah, AR_MCAST_FIL1, filter1);
 }
+EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
 
-void ath9k_hw_setbssidmask(struct ath_softc *sc)
+void ath9k_hw_write_associd(struct ath_hw *ah)
 {
-       REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
-       REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
-}
+       struct ath_common *common = ath9k_hw_common(ah);
 
-void ath9k_hw_write_associd(struct ath_softc *sc)
-{
-       REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
-       REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
-                 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
+       REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
+       REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
+                 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
 }
+EXPORT_SYMBOL(ath9k_hw_write_associd);
 
 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
 {
@@ -3919,54 +3608,56 @@ u64 ath9k_hw_gettsf64(struct ath_hw *ah)
 
        return tsf;
 }
+EXPORT_SYMBOL(ath9k_hw_gettsf64);
 
 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
 {
        REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
        REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
 }
+EXPORT_SYMBOL(ath9k_hw_settsf64);
 
 void ath9k_hw_reset_tsf(struct ath_hw *ah)
 {
-       ath9k_ps_wakeup(ah->ah_sc);
        if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
                           AH_TSF_WRITE_TIMEOUT))
-               DPRINTF(ah->ah_sc, ATH_DBG_RESET,
-                       "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
+               ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
+                         "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
 
        REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
-       ath9k_ps_restore(ah->ah_sc);
 }
+EXPORT_SYMBOL(ath9k_hw_reset_tsf);
 
-bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
+void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
 {
        if (setting)
                ah->misc_mode |= AR_PCU_TX_ADD_TSF;
        else
                ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
-
-       return true;
 }
+EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
 
-bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
+/*
+ *  Extend 15-bit time stamp from rx descriptor to
+ *  a full 64-bit TSF using the current h/w TSF.
+*/
+u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
 {
-       if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
-               DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
-               ah->slottime = (u32) -1;
-               return false;
-       } else {
-               REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
-               ah->slottime = us;
-               return true;
-       }
+       u64 tsf;
+
+       tsf = ath9k_hw_gettsf64(ah);
+       if ((tsf & 0x7fff) < rstamp)
+               tsf -= 0x8000;
+       return (tsf & ~0x7fff) | rstamp;
 }
+EXPORT_SYMBOL(ath9k_hw_extend_tsf);
 
-void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
+void ath9k_hw_set11nmac2040(struct ath_hw *ah)
 {
+       struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
        u32 macmode;
 
-       if (mode == ATH9K_HT_MACMODE_2040 &&
-           !ah->config.cwm_ignore_extcca)
+       if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
                macmode = AR_2040_JOINED_RX_CLEAR;
        else
                macmode = 0;
@@ -3974,29 +3665,280 @@ void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
        REG_WRITE(ah, AR_2040_MODE, macmode);
 }
 
-/***************************/
-/*  Bluetooth Coexistence  */
-/***************************/
+/* HW Generic timers configuration */
 
-void ath9k_hw_btcoex_enable(struct ath_hw *ah)
+static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
 {
-       /* connect bt_active to baseband */
-       REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
-                       (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
-                        AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
+       {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
+       {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
+       {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
+       {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
+       {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
+       {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
+       {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
+       {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
+       {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
+       {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
+                               AR_NDP2_TIMER_MODE, 0x0002},
+       {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
+                               AR_NDP2_TIMER_MODE, 0x0004},
+       {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
+                               AR_NDP2_TIMER_MODE, 0x0008},
+       {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
+                               AR_NDP2_TIMER_MODE, 0x0010},
+       {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
+                               AR_NDP2_TIMER_MODE, 0x0020},
+       {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
+                               AR_NDP2_TIMER_MODE, 0x0040},
+       {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
+                               AR_NDP2_TIMER_MODE, 0x0080}
+};
 
-       REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
-                       AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
+/* HW generic timer primitives */
 
-       /* Set input mux for bt_active to gpio pin */
-       REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
-                       AR_GPIO_INPUT_MUX1_BT_ACTIVE,
-                       ah->btactive_gpio);
+/* compute and clear index of rightmost 1 */
+static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
+{
+       u32 b;
+
+       b = *mask;
+       b &= (0-b);
+       *mask &= ~b;
+       b *= debruijn32;
+       b >>= 27;
+
+       return timer_table->gen_timer_index[b];
+}
+
+u32 ath9k_hw_gettsf32(struct ath_hw *ah)
+{
+       return REG_READ(ah, AR_TSF_L32);
+}
+EXPORT_SYMBOL(ath9k_hw_gettsf32);
 
-       /* Configure the desired gpio port for input */
-       ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
+struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
+                                         void (*trigger)(void *),
+                                         void (*overflow)(void *),
+                                         void *arg,
+                                         u8 timer_index)
+{
+       struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
+       struct ath_gen_timer *timer;
+
+       timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
+
+       if (timer == NULL) {
+               ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
+                         "Failed to allocate memory"
+                         "for hw timer[%d]\n", timer_index);
+               return NULL;
+       }
+
+       /* allocate a hardware generic timer slot */
+       timer_table->timers[timer_index] = timer;
+       timer->index = timer_index;
+       timer->trigger = trigger;
+       timer->overflow = overflow;
+       timer->arg = arg;
+
+       return timer;
+}
+EXPORT_SYMBOL(ath_gen_timer_alloc);
+
+void ath9k_hw_gen_timer_start(struct ath_hw *ah,
+                             struct ath_gen_timer *timer,
+                             u32 timer_next,
+                             u32 timer_period)
+{
+       struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
+       u32 tsf;
+
+       BUG_ON(!timer_period);
+
+       set_bit(timer->index, &timer_table->timer_mask.timer_bits);
+
+       tsf = ath9k_hw_gettsf32(ah);
+
+       ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
+                 "curent tsf %x period %x"
+                 "timer_next %x\n", tsf, timer_period, timer_next);
+
+       /*
+        * Pull timer_next forward if the current TSF already passed it
+        * because of software latency
+        */
+       if (timer_next < tsf)
+               timer_next = tsf + timer_period;
+
+       /*
+        * Program generic timer registers
+        */
+       REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
+                timer_next);
+       REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
+                 timer_period);
+       REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
+                   gen_tmr_configuration[timer->index].mode_mask);
+
+       /* Enable both trigger and thresh interrupt masks */
+       REG_SET_BIT(ah, AR_IMR_S5,
+               (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
+               SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
+}
+EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
+
+void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
+{
+       struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
+
+       if ((timer->index < AR_FIRST_NDP_TIMER) ||
+               (timer->index >= ATH_MAX_GEN_TIMER)) {
+               return;
+       }
+
+       /* Clear generic timer enable bits. */
+       REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
+                       gen_tmr_configuration[timer->index].mode_mask);
+
+       /* Disable both trigger and thresh interrupt masks */
+       REG_CLR_BIT(ah, AR_IMR_S5,
+               (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
+               SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
+
+       clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
+}
+EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
+
+void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
+{
+       struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
+
+       /* free the hardware generic timer slot */
+       timer_table->timers[timer->index] = NULL;
+       kfree(timer);
+}
+EXPORT_SYMBOL(ath_gen_timer_free);
+
+/*
+ * Generic Timer Interrupts handling
+ */
+void ath_gen_timer_isr(struct ath_hw *ah)
+{
+       struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
+       struct ath_gen_timer *timer;
+       struct ath_common *common = ath9k_hw_common(ah);
+       u32 trigger_mask, thresh_mask, index;
+
+       /* get hardware generic timer interrupt status */
+       trigger_mask = ah->intr_gen_timer_trigger;
+       thresh_mask = ah->intr_gen_timer_thresh;
+       trigger_mask &= timer_table->timer_mask.val;
+       thresh_mask &= timer_table->timer_mask.val;
+
+       trigger_mask &= ~thresh_mask;
+
+       while (thresh_mask) {
+               index = rightmost_index(timer_table, &thresh_mask);
+               timer = timer_table->timers[index];
+               BUG_ON(!timer);
+               ath_print(common, ATH_DBG_HWTIMER,
+                         "TSF overflow for Gen timer %d\n", index);
+               timer->overflow(timer->arg);
+       }
+
+       while (trigger_mask) {
+               index = rightmost_index(timer_table, &trigger_mask);
+               timer = timer_table->timers[index];
+               BUG_ON(!timer);
+               ath_print(common, ATH_DBG_HWTIMER,
+                         "Gen timer[%d] trigger\n", index);
+               timer->trigger(timer->arg);
+       }
+}
+EXPORT_SYMBOL(ath_gen_timer_isr);
+
+static struct {
+       u32 version;
+       const char * name;
+} ath_mac_bb_names[] = {
+       /* Devices with external radios */
+       { AR_SREV_VERSION_5416_PCI,     "5416" },
+       { AR_SREV_VERSION_5416_PCIE,    "5418" },
+       { AR_SREV_VERSION_9100,         "9100" },
+       { AR_SREV_VERSION_9160,         "9160" },
+       /* Single-chip solutions */
+       { AR_SREV_VERSION_9280,         "9280" },
+       { AR_SREV_VERSION_9285,         "9285" },
+       { AR_SREV_VERSION_9287,         "9287" },
+       { AR_SREV_VERSION_9271,         "9271" },
+};
+
+/* For devices with external radios */
+static struct {
+       u16 version;
+       const char * name;
+} ath_rf_names[] = {
+       { 0,                            "5133" },
+       { AR_RAD5133_SREV_MAJOR,        "5133" },
+       { AR_RAD5122_SREV_MAJOR,        "5122" },
+       { AR_RAD2133_SREV_MAJOR,        "2133" },
+       { AR_RAD2122_SREV_MAJOR,        "2122" }
+};
+
+/*
+ * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
+ */
+static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
+{
+       int i;
+
+       for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
+               if (ath_mac_bb_names[i].version == mac_bb_version) {
+                       return ath_mac_bb_names[i].name;
+               }
+       }
+
+       return "????";
+}
+
+/*
+ * Return the RF name. "????" is returned if the RF is unknown.
+ * Used for devices with external radios.
+ */
+static const char *ath9k_hw_rf_name(u16 rf_version)
+{
+       int i;
+
+       for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
+               if (ath_rf_names[i].version == rf_version) {
+                       return ath_rf_names[i].name;
+               }
+       }
+
+       return "????";
+}
+
+void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
+{
+       int used;
+
+       /* chipsets >= AR9280 are single-chip */
+       if (AR_SREV_9280_10_OR_LATER(ah)) {
+               used = snprintf(hw_name, len,
+                              "Atheros AR%s Rev:%x",
+                              ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
+                              ah->hw_version.macRev);
+       }
+       else {
+               used = snprintf(hw_name, len,
+                              "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
+                              ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
+                              ah->hw_version.macRev,
+                              ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
+                                               AR_RADIO_SREV_MAJOR)),
+                              ah->hw_version.phyRev);
+       }
 
-       /* Configure the desired GPIO port for TX_FRAME output */
-       ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
-                           AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
+       hw_name[used] = '\0';
 }
+EXPORT_SYMBOL(ath9k_hw_name);