Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
index 67b3b65..1baca8e 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010 Atheros Communications Inc.
+ * Copyright (c) 2010-2011 Atheros Communications Inc.
  *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
 #include "hw.h"
 #include "ar9003_phy.h"
 
+static const int firstep_table[] =
+/* level:  0   1   2   3   4   5   6   7   8  */
+       { -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
+
+static const int cycpwrThr1_table[] =
+/* level:  0   1   2   3   4   5   6   7   8  */
+       { -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
+
+/*
+ * register values to turn OFDM weak signal detection OFF
+ */
+static const int m1ThreshLow_off = 127;
+static const int m2ThreshLow_off = 127;
+static const int m1Thresh_off = 127;
+static const int m2Thresh_off = 127;
+static const int m2CountThr_off =  31;
+static const int m2CountThrLow_off =  63;
+static const int m1ThreshLowExt_off = 127;
+static const int m2ThreshLowExt_off = 127;
+static const int m1ThreshExt_off = 127;
+static const int m2ThreshExt_off = 127;
+
 /**
  * ar9003_hw_set_channel - set channel on single-chip device
  * @ah: atheros hardware structure
@@ -53,13 +75,54 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
        freq = centers.synth_center;
 
        if (freq < 4800) {     /* 2 GHz, fractional mode */
-               channelSel = CHANSEL_2G(freq);
+               if (AR_SREV_9330(ah)) {
+                       u32 chan_frac;
+                       u32 div;
+
+                       if (ah->is_clk_25mhz)
+                               div = 75;
+                       else
+                               div = 120;
+
+                       channelSel = (freq * 4) / div;
+                       chan_frac = (((freq * 4) % div) * 0x20000) / div;
+                       channelSel = (channelSel << 17) | chan_frac;
+               } else if (AR_SREV_9485(ah)) {
+                       u32 chan_frac;
+
+                       /*
+                        * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
+                        * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
+                        * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
+                        */
+                       channelSel = (freq * 4) / 120;
+                       chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
+                       channelSel = (channelSel << 17) | chan_frac;
+               } else if (AR_SREV_9340(ah)) {
+                       if (ah->is_clk_25mhz) {
+                               u32 chan_frac;
+
+                               channelSel = (freq * 2) / 75;
+                               chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
+                               channelSel = (channelSel << 17) | chan_frac;
+                       } else
+                               channelSel = CHANSEL_2G(freq) >> 1;
+               } else
+                       channelSel = CHANSEL_2G(freq);
                /* Set to 2G mode */
                bMode = 1;
        } else {
-               channelSel = CHANSEL_5G(freq);
-               /* Doubler is ON, so, divide channelSel by 2. */
-               channelSel >>= 1;
+               if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
+                       u32 chan_frac;
+
+                       channelSel = (freq * 2) / 75;
+                       chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
+                       channelSel = (channelSel << 17) | chan_frac;
+               } else {
+                       channelSel = CHANSEL_5G(freq);
+                       /* Doubler is ON, so, divide channelSel by 2. */
+                       channelSel >>= 1;
+               }
                /* Set to 5G mode */
                bMode = 0;
        }
@@ -94,7 +157,7 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
 }
 
 /**
- * ar9003_hw_spur_mitigate - convert baseband spur frequency
+ * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
  * @ah: atheros hardware structure
  * @chan:
  *
@@ -103,27 +166,56 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  *
  * Spur mitigation for MRC CCK
  */
-static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
-                                   struct ath9k_channel *chan)
+static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
+                                           struct ath9k_channel *chan)
 {
-       u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
+       static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
        int cur_bb_spur, negative = 0, cck_spur_freq;
        int i;
+       int range, max_spur_cnts, synth_freq;
+       u8 *spur_fbin_ptr = NULL;
 
        /*
         * Need to verify range +/- 10 MHz in control channel, otherwise spur
         * is out-of-band and can be ignored.
         */
 
-       for (i = 0; i < 4; i++) {
+       if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) {
+               spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
+                                                        IS_CHAN_2GHZ(chan));
+               if (spur_fbin_ptr[0] == 0) /* No spur */
+                       return;
+               max_spur_cnts = 5;
+               if (IS_CHAN_HT40(chan)) {
+                       range = 19;
+                       if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
+                                          AR_PHY_GC_DYN2040_PRI_CH) == 0)
+                               synth_freq = chan->channel + 10;
+                       else
+                               synth_freq = chan->channel - 10;
+               } else {
+                       range = 10;
+                       synth_freq = chan->channel;
+               }
+       } else {
+               range = 10;
+               max_spur_cnts = 4;
+               synth_freq = chan->channel;
+       }
+
+       for (i = 0; i < max_spur_cnts; i++) {
                negative = 0;
-               cur_bb_spur = spur_freq[i] - chan->channel;
+               if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
+                       cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
+                                       IS_CHAN_2GHZ(chan)) - synth_freq;
+               else
+                       cur_bb_spur = spur_freq[i] - synth_freq;
 
                if (cur_bb_spur < 0) {
                        negative = 1;
                        cur_bb_spur = -cur_bb_spur;
                }
-               if (cur_bb_spur < 10) {
+               if (cur_bb_spur < range) {
                        cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
 
                        if (negative == 1)
@@ -157,6 +249,212 @@ static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
                      AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
 }
 
+/* Clean all spur register fields */
+static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
+{
+       REG_RMW_FIELD(ah, AR_PHY_TIMING4,
+                     AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
+       REG_RMW_FIELD(ah, AR_PHY_TIMING11,
+                     AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
+       REG_RMW_FIELD(ah, AR_PHY_TIMING11,
+                     AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
+       REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+                     AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
+       REG_RMW_FIELD(ah, AR_PHY_TIMING11,
+                     AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
+       REG_RMW_FIELD(ah, AR_PHY_TIMING11,
+                     AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
+       REG_RMW_FIELD(ah, AR_PHY_TIMING4,
+                     AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
+       REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
+                     AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
+       REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
+                     AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
+
+       REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
+                     AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
+       REG_RMW_FIELD(ah, AR_PHY_TIMING4,
+                     AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
+       REG_RMW_FIELD(ah, AR_PHY_TIMING4,
+                     AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
+       REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
+                     AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
+       REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
+                     AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
+       REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
+                     AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
+       REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
+                     AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
+       REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
+                     AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
+       REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
+                     AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
+       REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
+                     AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
+}
+
+static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
+                               int freq_offset,
+                               int spur_freq_sd,
+                               int spur_delta_phase,
+                               int spur_subchannel_sd)
+{
+       int mask_index = 0;
+
+       /* OFDM Spur mitigation */
+       REG_RMW_FIELD(ah, AR_PHY_TIMING4,
+                AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
+       REG_RMW_FIELD(ah, AR_PHY_TIMING11,
+                     AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
+       REG_RMW_FIELD(ah, AR_PHY_TIMING11,
+                     AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
+       REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+                     AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
+       REG_RMW_FIELD(ah, AR_PHY_TIMING11,
+                     AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
+       REG_RMW_FIELD(ah, AR_PHY_TIMING11,
+                     AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
+       REG_RMW_FIELD(ah, AR_PHY_TIMING4,
+                     AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
+       REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
+                     AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
+       REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
+                     AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
+
+       if (REG_READ_FIELD(ah, AR_PHY_MODE,
+                          AR_PHY_MODE_DYNAMIC) == 0x1)
+               REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
+                             AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
+
+       mask_index = (freq_offset << 4) / 5;
+       if (mask_index < 0)
+               mask_index = mask_index - 1;
+
+       mask_index = mask_index & 0x7f;
+
+       REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
+                     AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
+       REG_RMW_FIELD(ah, AR_PHY_TIMING4,
+                     AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
+       REG_RMW_FIELD(ah, AR_PHY_TIMING4,
+                     AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
+       REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
+                     AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
+       REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
+                     AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
+       REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
+                     AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
+       REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
+                     AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
+       REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
+                     AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
+       REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
+                     AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
+       REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
+                     AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
+}
+
+static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
+                                    struct ath9k_channel *chan,
+                                    int freq_offset)
+{
+       int spur_freq_sd = 0;
+       int spur_subchannel_sd = 0;
+       int spur_delta_phase = 0;
+
+       if (IS_CHAN_HT40(chan)) {
+               if (freq_offset < 0) {
+                       if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
+                                          AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
+                               spur_subchannel_sd = 1;
+                       else
+                               spur_subchannel_sd = 0;
+
+                       spur_freq_sd = ((freq_offset + 10) << 9) / 11;
+
+               } else {
+                       if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
+                           AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
+                               spur_subchannel_sd = 0;
+                       else
+                               spur_subchannel_sd = 1;
+
+                       spur_freq_sd = ((freq_offset - 10) << 9) / 11;
+
+               }
+
+               spur_delta_phase = (freq_offset << 17) / 5;
+
+       } else {
+               spur_subchannel_sd = 0;
+               spur_freq_sd = (freq_offset << 9) /11;
+               spur_delta_phase = (freq_offset << 18) / 5;
+       }
+
+       spur_freq_sd = spur_freq_sd & 0x3ff;
+       spur_delta_phase = spur_delta_phase & 0xfffff;
+
+       ar9003_hw_spur_ofdm(ah,
+                           freq_offset,
+                           spur_freq_sd,
+                           spur_delta_phase,
+                           spur_subchannel_sd);
+}
+
+/* Spur mitigation for OFDM */
+static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
+                                        struct ath9k_channel *chan)
+{
+       int synth_freq;
+       int range = 10;
+       int freq_offset = 0;
+       int mode;
+       u8* spurChansPtr;
+       unsigned int i;
+       struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+
+       if (IS_CHAN_5GHZ(chan)) {
+               spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
+               mode = 0;
+       }
+       else {
+               spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
+               mode = 1;
+       }
+
+       if (spurChansPtr[0] == 0)
+               return; /* No spur in the mode */
+
+       if (IS_CHAN_HT40(chan)) {
+               range = 19;
+               if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
+                                  AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
+                       synth_freq = chan->channel - 10;
+               else
+                       synth_freq = chan->channel + 10;
+       } else {
+               range = 10;
+               synth_freq = chan->channel;
+       }
+
+       ar9003_hw_spur_ofdm_clear(ah);
+
+       for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
+               freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
+               if (abs(freq_offset) < range) {
+                       ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
+                       break;
+               }
+       }
+}
+
+static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
+                                   struct ath9k_channel *chan)
+{
+       ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
+       ar9003_hw_spur_mitigate_ofdm(ah, chan);
+}
+
 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
                                         struct ath9k_channel *chan)
 {
@@ -169,16 +467,7 @@ static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
        else if (chan && IS_CHAN_QUARTER_RATE(chan))
                pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
 
-       if (chan && IS_CHAN_5GHZ(chan)) {
-               pll |= SM(0x28, AR_RTC_9300_PLL_DIV);
-
-               /*
-                * When doing fast clock, set PLL to 0x142c
-                */
-               if (IS_CHAN_A_5MHZ_SPACED(chan))
-                       pll = 0x142c;
-       } else
-               pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
+       pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
 
        return pll;
 }
@@ -268,7 +557,11 @@ void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
                break;
        }
 
-       REG_WRITE(ah, AR_SELFGEN_MASK, tx);
+       if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
+               REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
+       else
+               REG_WRITE(ah, AR_SELFGEN_MASK, tx);
+
        if (tx == 0x5) {
                REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
                            AR_PHY_SWAP_ALT_CHAIN);
@@ -325,14 +618,6 @@ static void ar9003_hw_prog_ini(struct ath_hw *ah,
 
                REG_WRITE(ah, reg, val);
 
-               /*
-                * Determine if this is a shift register value, and insert the
-                * configured delay if so.
-                */
-               if (reg >= 0x16000 && reg < 0x17000
-                   && ah->config.analog_shiftreg)
-                       udelay(100);
-
                DO_DELAY(regWrites);
        }
 }
@@ -343,29 +628,25 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
        struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
        unsigned int regWrites = 0, i;
        struct ieee80211_channel *channel = chan->chan;
-       u32 modesIndex, freqIndex;
+       u32 modesIndex;
 
        switch (chan->chanmode) {
        case CHANNEL_A:
        case CHANNEL_A_HT20:
                modesIndex = 1;
-               freqIndex = 1;
                break;
        case CHANNEL_A_HT40PLUS:
        case CHANNEL_A_HT40MINUS:
                modesIndex = 2;
-               freqIndex = 1;
                break;
        case CHANNEL_G:
        case CHANNEL_G_HT20:
        case CHANNEL_B:
                modesIndex = 4;
-               freqIndex = 2;
                break;
        case CHANNEL_G_HT40PLUS:
        case CHANNEL_G_HT40MINUS:
                modesIndex = 3;
-               freqIndex = 2;
                break;
 
        default:
@@ -386,10 +667,16 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
         * For 5GHz channels requiring Fast Clock, apply
         * different modal values.
         */
-       if (IS_CHAN_A_5MHZ_SPACED(chan))
+       if (IS_CHAN_A_FAST_CLOCK(ah, chan))
                REG_WRITE_ARRAY(&ah->iniModesAdditional,
                                modesIndex, regWrites);
 
+       if (AR_SREV_9300(ah))
+               REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites);
+
+       if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
+               REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
+
        ar9003_hw_override_ini(ah);
        ar9003_hw_set_channel_regs(ah, chan);
        ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
@@ -400,7 +687,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
                                 channel->max_antenna_gain * 2,
                                 channel->max_power * 2,
                                 min((u32) MAX_RATE_POWER,
-                                (u32) regulatory->power_limit));
+                                (u32) regulatory->power_limit), false);
 
        return 0;
 }
@@ -416,7 +703,7 @@ static void ar9003_hw_set_rfmode(struct ath_hw *ah,
        rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
                ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
 
-       if (IS_CHAN_A_5MHZ_SPACED(chan))
+       if (IS_CHAN_A_FAST_CLOCK(ah, chan))
                rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
 
        REG_WRITE(ah, AR_PHY_MODE, rfMode);
@@ -498,28 +785,6 @@ static void ar9003_hw_rfbus_done(struct ath_hw *ah)
        REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 }
 
-/*
- * Set the interrupt and GPIO values so the ISR can disable RF
- * on a switch signal.  Assumes GPIO port and interrupt polarity
- * are set prior to call.
- */
-static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
-{
-       /* Connect rfsilent_bb_l to baseband */
-       REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
-                   AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
-       /* Set input mux for rfsilent_bb_l to GPIO #0 */
-       REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
-                   AR_GPIO_INPUT_MUX2_RFSILENT);
-
-       /*
-        * Configure the desired GPIO port for input and
-        * enable baseband rf silence.
-        */
-       ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
-       REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
-}
-
 static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
 {
        u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
@@ -533,73 +798,70 @@ static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
 static bool ar9003_hw_ani_control(struct ath_hw *ah,
                                  enum ath9k_ani_cmd cmd, int param)
 {
-       struct ar5416AniState *aniState = ah->curani;
        struct ath_common *common = ath9k_hw_common(ah);
+       struct ath9k_channel *chan = ah->curchan;
+       struct ar5416AniState *aniState = &chan->ani;
+       s32 value, value2;
 
        switch (cmd & ah->ani_function) {
-       case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
-               u32 level = param;
-
-               if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
-                       ath_print(common, ATH_DBG_ANI,
-                                 "level out of range (%u > %u)\n",
-                                 level,
-                                 (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
-                       return false;
-               }
-
-               REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
-                             AR_PHY_DESIRED_SZ_TOT_DES,
-                             ah->totalSizeDesired[level]);
-               REG_RMW_FIELD(ah, AR_PHY_AGC,
-                             AR_PHY_AGC_COARSE_LOW,
-                             ah->coarse_low[level]);
-               REG_RMW_FIELD(ah, AR_PHY_AGC,
-                             AR_PHY_AGC_COARSE_HIGH,
-                             ah->coarse_high[level]);
-               REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
-                             AR_PHY_FIND_SIG_FIRPWR, ah->firpwr[level]);
-
-               if (level > aniState->noiseImmunityLevel)
-                       ah->stats.ast_ani_niup++;
-               else if (level < aniState->noiseImmunityLevel)
-                       ah->stats.ast_ani_nidown++;
-               aniState->noiseImmunityLevel = level;
-               break;
-       }
        case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
-               const int m1ThreshLow[] = { 127, 50 };
-               const int m2ThreshLow[] = { 127, 40 };
-               const int m1Thresh[] = { 127, 0x4d };
-               const int m2Thresh[] = { 127, 0x40 };
-               const int m2CountThr[] = { 31, 16 };
-               const int m2CountThrLow[] = { 63, 48 };
+               /*
+                * on == 1 means ofdm weak signal detection is ON
+                * on == 1 is the default, for less noise immunity
+                *
+                * on == 0 means ofdm weak signal detection is OFF
+                * on == 0 means more noise imm
+                */
                u32 on = param ? 1 : 0;
+               /*
+                * make register setting for default
+                * (weak sig detect ON) come from INI file
+                */
+               int m1ThreshLow = on ?
+                       aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
+               int m2ThreshLow = on ?
+                       aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
+               int m1Thresh = on ?
+                       aniState->iniDef.m1Thresh : m1Thresh_off;
+               int m2Thresh = on ?
+                       aniState->iniDef.m2Thresh : m2Thresh_off;
+               int m2CountThr = on ?
+                       aniState->iniDef.m2CountThr : m2CountThr_off;
+               int m2CountThrLow = on ?
+                       aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
+               int m1ThreshLowExt = on ?
+                       aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
+               int m2ThreshLowExt = on ?
+                       aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
+               int m1ThreshExt = on ?
+                       aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
+               int m2ThreshExt = on ?
+                       aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
 
                REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
                              AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
-                             m1ThreshLow[on]);
+                             m1ThreshLow);
                REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
                              AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
-                             m2ThreshLow[on]);
+                             m2ThreshLow);
                REG_RMW_FIELD(ah, AR_PHY_SFCORR,
-                             AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]);
+                             AR_PHY_SFCORR_M1_THRESH, m1Thresh);
                REG_RMW_FIELD(ah, AR_PHY_SFCORR,
-                             AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]);
+                             AR_PHY_SFCORR_M2_THRESH, m2Thresh);
                REG_RMW_FIELD(ah, AR_PHY_SFCORR,
-                             AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]);
+                             AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
                REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
                              AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
-                             m2CountThrLow[on]);
+                             m2CountThrLow);
 
                REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
-                             AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLow[on]);
+                             AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
                REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
-                             AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLow[on]);
+                             AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
                REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
-                             AR_PHY_SFCORR_EXT_M1_THRESH, m1Thresh[on]);
+                             AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
                REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
-                             AR_PHY_SFCORR_EXT_M2_THRESH, m2Thresh[on]);
+                             AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
 
                if (on)
                        REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
@@ -609,6 +871,12 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                                    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 
                if (!on != aniState->ofdmWeakSigDetectOff) {
+                       ath_dbg(common, ATH_DBG_ANI,
+                               "** ch %d: ofdm weak signal: %s=>%s\n",
+                               chan->channel,
+                               !aniState->ofdmWeakSigDetectOff ?
+                               "on" : "off",
+                               on ? "on" : "off");
                        if (on)
                                ah->stats.ast_ani_ofdmon++;
                        else
@@ -617,206 +885,386 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                }
                break;
        }
-       case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
-               const int weakSigThrCck[] = { 8, 6 };
-               u32 high = param ? 1 : 0;
-
-               REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
-                             AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
-                             weakSigThrCck[high]);
-               if (high != aniState->cckWeakSigThreshold) {
-                       if (high)
-                               ah->stats.ast_ani_cckhigh++;
-                       else
-                               ah->stats.ast_ani_ccklow++;
-                       aniState->cckWeakSigThreshold = high;
-               }
-               break;
-       }
        case ATH9K_ANI_FIRSTEP_LEVEL:{
-               const int firstep[] = { 0, 4, 8 };
                u32 level = param;
 
-               if (level >= ARRAY_SIZE(firstep)) {
-                       ath_print(common, ATH_DBG_ANI,
-                                 "level out of range (%u > %u)\n",
-                                 level,
-                                 (unsigned) ARRAY_SIZE(firstep));
+               if (level >= ARRAY_SIZE(firstep_table)) {
+                       ath_dbg(common, ATH_DBG_ANI,
+                               "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
+                               level, ARRAY_SIZE(firstep_table));
                        return false;
                }
+
+               /*
+                * make register setting relative to default
+                * from INI file & cap value
+                */
+               value = firstep_table[level] -
+                       firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
+                       aniState->iniDef.firstep;
+               if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
+                       value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
+               if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
+                       value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
                REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
                              AR_PHY_FIND_SIG_FIRSTEP,
-                             firstep[level]);
-               if (level > aniState->firstepLevel)
-                       ah->stats.ast_ani_stepup++;
-               else if (level < aniState->firstepLevel)
-                       ah->stats.ast_ani_stepdown++;
-               aniState->firstepLevel = level;
+                             value);
+               /*
+                * we need to set first step low register too
+                * make register setting relative to default
+                * from INI file & cap value
+                */
+               value2 = firstep_table[level] -
+                        firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
+                        aniState->iniDef.firstepLow;
+               if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
+                       value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
+               if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
+                       value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
+
+               REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
+                             AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
+
+               if (level != aniState->firstepLevel) {
+                       ath_dbg(common, ATH_DBG_ANI,
+                               "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
+                               chan->channel,
+                               aniState->firstepLevel,
+                               level,
+                               ATH9K_ANI_FIRSTEP_LVL_NEW,
+                               value,
+                               aniState->iniDef.firstep);
+                       ath_dbg(common, ATH_DBG_ANI,
+                               "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
+                               chan->channel,
+                               aniState->firstepLevel,
+                               level,
+                               ATH9K_ANI_FIRSTEP_LVL_NEW,
+                               value2,
+                               aniState->iniDef.firstepLow);
+                       if (level > aniState->firstepLevel)
+                               ah->stats.ast_ani_stepup++;
+                       else if (level < aniState->firstepLevel)
+                               ah->stats.ast_ani_stepdown++;
+                       aniState->firstepLevel = level;
+               }
                break;
        }
        case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
-               const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
                u32 level = param;
 
-               if (level >= ARRAY_SIZE(cycpwrThr1)) {
-                       ath_print(common, ATH_DBG_ANI,
-                                 "level out of range (%u > %u)\n",
-                                 level,
-                                 (unsigned) ARRAY_SIZE(cycpwrThr1));
+               if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
+                       ath_dbg(common, ATH_DBG_ANI,
+                               "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
+                               level, ARRAY_SIZE(cycpwrThr1_table));
                        return false;
                }
+               /*
+                * make register setting relative to default
+                * from INI file & cap value
+                */
+               value = cycpwrThr1_table[level] -
+                       cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
+                       aniState->iniDef.cycpwrThr1;
+               if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
+                       value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
+               if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
+                       value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
                REG_RMW_FIELD(ah, AR_PHY_TIMING5,
                              AR_PHY_TIMING5_CYCPWR_THR1,
-                             cycpwrThr1[level]);
-               if (level > aniState->spurImmunityLevel)
-                       ah->stats.ast_ani_spurup++;
-               else if (level < aniState->spurImmunityLevel)
-                       ah->stats.ast_ani_spurdown++;
-               aniState->spurImmunityLevel = level;
+                             value);
+
+               /*
+                * set AR_PHY_EXT_CCA for extension channel
+                * make register setting relative to default
+                * from INI file & cap value
+                */
+               value2 = cycpwrThr1_table[level] -
+                        cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
+                        aniState->iniDef.cycpwrThr1Ext;
+               if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
+                       value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
+               if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
+                       value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
+               REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
+                             AR_PHY_EXT_CYCPWR_THR1, value2);
+
+               if (level != aniState->spurImmunityLevel) {
+                       ath_dbg(common, ATH_DBG_ANI,
+                               "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
+                               chan->channel,
+                               aniState->spurImmunityLevel,
+                               level,
+                               ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
+                               value,
+                               aniState->iniDef.cycpwrThr1);
+                       ath_dbg(common, ATH_DBG_ANI,
+                               "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
+                               chan->channel,
+                               aniState->spurImmunityLevel,
+                               level,
+                               ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
+                               value2,
+                               aniState->iniDef.cycpwrThr1Ext);
+                       if (level > aniState->spurImmunityLevel)
+                               ah->stats.ast_ani_spurup++;
+                       else if (level < aniState->spurImmunityLevel)
+                               ah->stats.ast_ani_spurdown++;
+                       aniState->spurImmunityLevel = level;
+               }
                break;
        }
+       case ATH9K_ANI_MRC_CCK:{
+               /*
+                * is_on == 1 means MRC CCK ON (default, less noise imm)
+                * is_on == 0 means MRC CCK is OFF (more noise imm)
+                */
+               bool is_on = param ? 1 : 0;
+               REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
+                             AR_PHY_MRC_CCK_ENABLE, is_on);
+               REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
+                             AR_PHY_MRC_CCK_MUX_REG, is_on);
+               if (!is_on != aniState->mrcCCKOff) {
+                       ath_dbg(common, ATH_DBG_ANI,
+                               "** ch %d: MRC CCK: %s=>%s\n",
+                               chan->channel,
+                               !aniState->mrcCCKOff ? "on" : "off",
+                               is_on ? "on" : "off");
+               if (is_on)
+                       ah->stats.ast_ani_ccklow++;
+               else
+                       ah->stats.ast_ani_cckhigh++;
+               aniState->mrcCCKOff = !is_on;
+               }
+       break;
+       }
        case ATH9K_ANI_PRESENT:
                break;
        default:
-               ath_print(common, ATH_DBG_ANI,
-                         "invalid cmd %u\n", cmd);
+               ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
                return false;
        }
 
-       ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
-       ath_print(common, ATH_DBG_ANI,
-                 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
-                 "ofdmWeakSigDetectOff=%d\n",
-                 aniState->noiseImmunityLevel,
-                 aniState->spurImmunityLevel,
-                 !aniState->ofdmWeakSigDetectOff);
-       ath_print(common, ATH_DBG_ANI,
-                 "cckWeakSigThreshold=%d, "
-                 "firstepLevel=%d, listenTime=%d\n",
-                 aniState->cckWeakSigThreshold,
-                 aniState->firstepLevel,
-                 aniState->listenTime);
-       ath_print(common, ATH_DBG_ANI,
-               "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
-               aniState->cycleCount,
+       ath_dbg(common, ATH_DBG_ANI,
+               "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
+               aniState->spurImmunityLevel,
+               !aniState->ofdmWeakSigDetectOff ? "on" : "off",
+               aniState->firstepLevel,
+               !aniState->mrcCCKOff ? "on" : "off",
+               aniState->listenTime,
                aniState->ofdmPhyErrCount,
                aniState->cckPhyErrCount);
-
        return true;
 }
 
-static void ar9003_hw_nf_sanitize_2g(struct ath_hw *ah, s16 *nf)
+static void ar9003_hw_do_getnf(struct ath_hw *ah,
+                             int16_t nfarray[NUM_NF_READINGS])
 {
-       struct ath_common *common = ath9k_hw_common(ah);
+#define AR_PHY_CH_MINCCA_PWR   0x1FF00000
+#define AR_PHY_CH_MINCCA_PWR_S 20
+#define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
+#define AR_PHY_CH_EXT_MINCCA_PWR_S 16
 
-       if (*nf > ah->nf_2g_max) {
-               ath_print(common, ATH_DBG_CALIBRATE,
-                         "2 GHz NF (%d) > MAX (%d), "
-                         "correcting to MAX",
-                         *nf, ah->nf_2g_max);
-               *nf = ah->nf_2g_max;
-       } else if (*nf < ah->nf_2g_min) {
-               ath_print(common, ATH_DBG_CALIBRATE,
-                         "2 GHz NF (%d) < MIN (%d), "
-                         "correcting to MIN",
-                         *nf, ah->nf_2g_min);
-               *nf = ah->nf_2g_min;
+       int16_t nf;
+       int i;
+
+       for (i = 0; i < AR9300_MAX_CHAINS; i++) {
+               if (ah->rxchainmask & BIT(i)) {
+                       nf = MS(REG_READ(ah, ah->nf_regs[i]),
+                                        AR_PHY_CH_MINCCA_PWR);
+                       nfarray[i] = sign_extend32(nf, 8);
+
+                       if (IS_CHAN_HT40(ah->curchan)) {
+                               u8 ext_idx = AR9300_MAX_CHAINS + i;
+
+                               nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
+                                                AR_PHY_CH_EXT_MINCCA_PWR);
+                               nfarray[ext_idx] = sign_extend32(nf, 8);
+                       }
+               }
        }
 }
 
-static void ar9003_hw_nf_sanitize_5g(struct ath_hw *ah, s16 *nf)
+static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
+{
+       ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
+       ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
+       if (AR_SREV_9330(ah))
+               ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
+       else
+               ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
+       ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
+       ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
+       ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
+}
+
+/*
+ * Initialize the ANI register values with default (ini) values.
+ * This routine is called during a (full) hardware reset after
+ * all the registers are initialised from the INI.
+ */
+static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
 {
+       struct ar5416AniState *aniState;
        struct ath_common *common = ath9k_hw_common(ah);
+       struct ath9k_channel *chan = ah->curchan;
+       struct ath9k_ani_default *iniDef;
+       u32 val;
 
-       if (*nf > ah->nf_5g_max) {
-               ath_print(common, ATH_DBG_CALIBRATE,
-                         "5 GHz NF (%d) > MAX (%d), "
-                         "correcting to MAX",
-                         *nf, ah->nf_5g_max);
-               *nf = ah->nf_5g_max;
-       } else if (*nf < ah->nf_5g_min) {
-               ath_print(common, ATH_DBG_CALIBRATE,
-                         "5 GHz NF (%d) < MIN (%d), "
-                         "correcting to MIN",
-                         *nf, ah->nf_5g_min);
-               *nf = ah->nf_5g_min;
-       }
+       aniState = &ah->curchan->ani;
+       iniDef = &aniState->iniDef;
+
+       ath_dbg(common, ATH_DBG_ANI,
+               "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
+               ah->hw_version.macVersion,
+               ah->hw_version.macRev,
+               ah->opmode,
+               chan->channel,
+               chan->channelFlags);
+
+       val = REG_READ(ah, AR_PHY_SFCORR);
+       iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
+       iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
+       iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
+
+       val = REG_READ(ah, AR_PHY_SFCORR_LOW);
+       iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
+       iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
+       iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
+
+       val = REG_READ(ah, AR_PHY_SFCORR_EXT);
+       iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
+       iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
+       iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
+       iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
+       iniDef->firstep = REG_READ_FIELD(ah,
+                                        AR_PHY_FIND_SIG,
+                                        AR_PHY_FIND_SIG_FIRSTEP);
+       iniDef->firstepLow = REG_READ_FIELD(ah,
+                                           AR_PHY_FIND_SIG_LOW,
+                                           AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
+       iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
+                                           AR_PHY_TIMING5,
+                                           AR_PHY_TIMING5_CYCPWR_THR1);
+       iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
+                                              AR_PHY_EXT_CCA,
+                                              AR_PHY_EXT_CYCPWR_THR1);
+
+       /* these levels just got reset to defaults by the INI */
+       aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
+       aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
+       aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
+       aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
 }
 
-static void ar9003_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
+static void ar9003_hw_set_radar_params(struct ath_hw *ah,
+                                      struct ath_hw_radar_conf *conf)
 {
-       if (IS_CHAN_2GHZ(ah->curchan))
-               ar9003_hw_nf_sanitize_2g(ah, nf);
+       u32 radar_0 = 0, radar_1 = 0;
+
+       if (!conf) {
+               REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
+               return;
+       }
+
+       radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
+       radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
+       radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
+       radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
+       radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
+       radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
+
+       radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
+       radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
+       radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
+       radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
+       radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
+
+       REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
+       REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
+       if (conf->ext_channel)
+               REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
        else
-               ar9003_hw_nf_sanitize_5g(ah, nf);
+               REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
 }
 
-static void ar9003_hw_do_getnf(struct ath_hw *ah,
-                             int16_t nfarray[NUM_NF_READINGS])
+static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
 {
-       struct ath_common *common = ath9k_hw_common(ah);
-       int16_t nf;
+       struct ath_hw_radar_conf *conf = &ah->radar_conf;
+
+       conf->fir_power = -28;
+       conf->radar_rssi = 0;
+       conf->pulse_height = 10;
+       conf->pulse_rssi = 24;
+       conf->pulse_inband = 8;
+       conf->pulse_maxlen = 255;
+       conf->pulse_inband_step = 12;
+       conf->radar_inband = 8;
+}
 
-       nf = MS(REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR);
-       if (nf & 0x100)
-               nf = 0 - ((nf ^ 0x1ff) + 1);
-       ar9003_hw_nf_sanitize(ah, &nf);
-       ath_print(common, ATH_DBG_CALIBRATE,
-                 "NF calibrated [ctl] [chain 0] is %d\n", nf);
-       nfarray[0] = nf;
-
-       nf = MS(REG_READ(ah, AR_PHY_CCA_1), AR_PHY_CH1_MINCCA_PWR);
-       if (nf & 0x100)
-               nf = 0 - ((nf ^ 0x1ff) + 1);
-       ar9003_hw_nf_sanitize(ah, &nf);
-       ath_print(common, ATH_DBG_CALIBRATE,
-                 "NF calibrated [ctl] [chain 1] is %d\n", nf);
-       nfarray[1] = nf;
-
-       nf = MS(REG_READ(ah, AR_PHY_CCA_2), AR_PHY_CH2_MINCCA_PWR);
-       if (nf & 0x100)
-               nf = 0 - ((nf ^ 0x1ff) + 1);
-       ar9003_hw_nf_sanitize(ah, &nf);
-       ath_print(common, ATH_DBG_CALIBRATE,
-                 "NF calibrated [ctl] [chain 2] is %d\n", nf);
-       nfarray[2] = nf;
-
-       nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
-       if (nf & 0x100)
-               nf = 0 - ((nf ^ 0x1ff) + 1);
-       ar9003_hw_nf_sanitize(ah, &nf);
-       ath_print(common, ATH_DBG_CALIBRATE,
-                 "NF calibrated [ext] [chain 0] is %d\n", nf);
-       nfarray[3] = nf;
-
-       nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_1), AR_PHY_CH1_EXT_MINCCA_PWR);
-       if (nf & 0x100)
-               nf = 0 - ((nf ^ 0x1ff) + 1);
-       ar9003_hw_nf_sanitize(ah, &nf);
-       ath_print(common, ATH_DBG_CALIBRATE,
-                 "NF calibrated [ext] [chain 1] is %d\n", nf);
-       nfarray[4] = nf;
-
-       nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_2), AR_PHY_CH2_EXT_MINCCA_PWR);
-       if (nf & 0x100)
-               nf = 0 - ((nf ^ 0x1ff) + 1);
-       ar9003_hw_nf_sanitize(ah, &nf);
-       ath_print(common, ATH_DBG_CALIBRATE,
-                 "NF calibrated [ext] [chain 2] is %d\n", nf);
-       nfarray[5] = nf;
-}
-
-void ar9003_hw_set_nf_limits(struct ath_hw *ah)
-{
-       ah->nf_2g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
-       ah->nf_2g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
-       ah->nf_5g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
-       ah->nf_5g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
+static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
+                                  struct ath_hw_antcomb_conf *antconf)
+{
+       u32 regval;
+
+       regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
+       antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>
+                                 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;
+       antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>
+                                AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
+       antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
+                                 AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
+
+       if (AR_SREV_9330_11(ah)) {
+               antconf->lna1_lna2_delta = -9;
+               antconf->div_group = 1;
+       } else if (AR_SREV_9485(ah)) {
+               antconf->lna1_lna2_delta = -9;
+               antconf->div_group = 2;
+       } else {
+               antconf->lna1_lna2_delta = -3;
+               antconf->div_group = 0;
+       }
+}
+
+static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
+                                  struct ath_hw_antcomb_conf *antconf)
+{
+       u32 regval;
+
+       regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
+       regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
+                   AR_PHY_9485_ANT_DIV_ALT_LNACONF |
+                   AR_PHY_9485_ANT_FAST_DIV_BIAS |
+                   AR_PHY_9485_ANT_DIV_MAIN_GAINTB |
+                   AR_PHY_9485_ANT_DIV_ALT_GAINTB);
+       regval |= ((antconf->main_lna_conf <<
+                                       AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)
+                  & AR_PHY_9485_ANT_DIV_MAIN_LNACONF);
+       regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)
+                  & AR_PHY_9485_ANT_DIV_ALT_LNACONF);
+       regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)
+                  & AR_PHY_9485_ANT_FAST_DIV_BIAS);
+       regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)
+                  & AR_PHY_9485_ANT_DIV_MAIN_GAINTB);
+       regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)
+                  & AR_PHY_9485_ANT_DIV_ALT_GAINTB);
+
+       REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
 }
 
 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
 {
        struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
+       struct ath_hw_ops *ops = ath9k_hw_ops(ah);
+       static const u32 ar9300_cca_regs[6] = {
+               AR_PHY_CCA_0,
+               AR_PHY_CCA_1,
+               AR_PHY_CCA_2,
+               AR_PHY_EXT_CCA,
+               AR_PHY_EXT_CCA_1,
+               AR_PHY_EXT_CCA_2,
+       };
 
        priv_ops->rf_set_freq = ar9003_hw_set_channel;
        priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
@@ -829,8 +1277,156 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
        priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
        priv_ops->rfbus_req = ar9003_hw_rfbus_req;
        priv_ops->rfbus_done = ar9003_hw_rfbus_done;
-       priv_ops->enable_rfkill = ar9003_hw_enable_rfkill;
        priv_ops->set_diversity = ar9003_hw_set_diversity;
        priv_ops->ani_control = ar9003_hw_ani_control;
        priv_ops->do_getnf = ar9003_hw_do_getnf;
+       priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
+       priv_ops->set_radar_params = ar9003_hw_set_radar_params;
+
+       ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
+       ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
+
+       ar9003_hw_set_nf_limits(ah);
+       ar9003_hw_set_radar_conf(ah);
+       memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
+}
+
+void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
+{
+       struct ath_common *common = ath9k_hw_common(ah);
+       u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
+       u32 val, idle_count;
+
+       if (!idle_tmo_ms) {
+               /* disable IRQ, disable chip-reset for BB panic */
+               REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
+                         REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
+                         ~(AR_PHY_WATCHDOG_RST_ENABLE |
+                           AR_PHY_WATCHDOG_IRQ_ENABLE));
+
+               /* disable watchdog in non-IDLE mode, disable in IDLE mode */
+               REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
+                         REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
+                         ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
+                           AR_PHY_WATCHDOG_IDLE_ENABLE));
+
+               ath_dbg(common, ATH_DBG_RESET, "Disabled BB Watchdog\n");
+               return;
+       }
+
+       /* enable IRQ, disable chip-reset for BB watchdog */
+       val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
+       REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
+                 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
+                 ~AR_PHY_WATCHDOG_RST_ENABLE);
+
+       /* bound limit to 10 secs */
+       if (idle_tmo_ms > 10000)
+               idle_tmo_ms = 10000;
+
+       /*
+        * The time unit for watchdog event is 2^15 44/88MHz cycles.
+        *
+        * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
+        * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
+        *
+        * Given we use fast clock now in 5 GHz, these time units should
+        * be common for both 2 GHz and 5 GHz.
+        */
+       idle_count = (100 * idle_tmo_ms) / 74;
+       if (ah->curchan && IS_CHAN_HT40(ah->curchan))
+               idle_count = (100 * idle_tmo_ms) / 37;
+
+       /*
+        * enable watchdog in non-IDLE mode, disable in IDLE mode,
+        * set idle time-out.
+        */
+       REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
+                 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
+                 AR_PHY_WATCHDOG_IDLE_MASK |
+                 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
+
+       ath_dbg(common, ATH_DBG_RESET,
+               "Enabled BB Watchdog timeout (%u ms)\n",
+               idle_tmo_ms);
+}
+
+void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
+{
+       /*
+        * we want to avoid printing in ISR context so we save the
+        * watchdog status to be printed later in bottom half context.
+        */
+       ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
+
+       /*
+        * the watchdog timer should reset on status read but to be sure
+        * sure we write 0 to the watchdog status bit.
+        */
+       REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
+                 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
+}
+
+void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
+{
+       struct ath_common *common = ath9k_hw_common(ah);
+       u32 status;
+
+       if (likely(!(common->debug_mask & ATH_DBG_RESET)))
+               return;
+
+       status = ah->bb_watchdog_last_status;
+       ath_dbg(common, ATH_DBG_RESET,
+               "\n==== BB update: BB status=0x%08x ====\n", status);
+       ath_dbg(common, ATH_DBG_RESET,
+               "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
+               MS(status, AR_PHY_WATCHDOG_INFO),
+               MS(status, AR_PHY_WATCHDOG_DET_HANG),
+               MS(status, AR_PHY_WATCHDOG_RADAR_SM),
+               MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
+               MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
+               MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
+               MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
+               MS(status, AR_PHY_WATCHDOG_AGC_SM),
+               MS(status, AR_PHY_WATCHDOG_SRCH_SM));
+
+       ath_dbg(common, ATH_DBG_RESET,
+               "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
+               REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
+               REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
+       ath_dbg(common, ATH_DBG_RESET,
+               "** BB mode: BB_gen_controls=0x%08x **\n",
+               REG_READ(ah, AR_PHY_GEN_CTRL));
+
+#define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
+       if (common->cc_survey.cycles)
+               ath_dbg(common, ATH_DBG_RESET,
+                       "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
+                       PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
+
+       ath_dbg(common, ATH_DBG_RESET,
+               "==== BB update: done ====\n\n");
+}
+EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
+
+void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
+{
+       u32 val;
+
+       /* While receiving unsupported rate frame rx state machine
+        * gets into a state 0xb and if phy_restart happens in that
+        * state, BB would go hang. If RXSM is in 0xb state after
+        * first bb panic, ensure to disable the phy_restart.
+        */
+       if (!((MS(ah->bb_watchdog_last_status,
+                 AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
+           ah->bb_hang_rx_ofdm))
+               return;
+
+       ah->bb_hang_rx_ofdm = true;
+       val = REG_READ(ah, AR_PHY_RESTART);
+       val &= ~AR_PHY_RESTART_ENA;
+
+       REG_WRITE(ah, AR_PHY_RESTART, val);
 }
+EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);