ath5k: don't reset mcast filter when configuring the mode
[linux-2.6.git] / drivers / net / wireless / ath / ath5k / base.c
index 1a6e72f..95a8e23 100644 (file)
@@ -59,7 +59,7 @@
 #include "reg.h"
 #include "debug.h"
 
-static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
+static u8 ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
 static int modparam_nohwcrypt;
 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
@@ -84,24 +84,24 @@ MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
 
 /* Known PCI ids */
 static const struct pci_device_id ath5k_pci_id_table[] = {
-       { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
-       { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
-       { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
-       { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
-       { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
-       { PCI_VDEVICE(3COM_2,  0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
-       { PCI_VDEVICE(3COM,    0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
-       { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
-       { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
-       { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
-       { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
-       { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
-       { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
-       { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
-       { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
-       { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
-       { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
-       { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
+       { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
+       { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
+       { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
+       { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
+       { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
+       { PCI_VDEVICE(3COM_2,  0x0013) }, /* 3com 5212 */
+       { PCI_VDEVICE(3COM,    0x0013) }, /* 3com 3CRDAG675 5212 */
+       { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
+       { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
+       { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
+       { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
+       { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
+       { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
+       { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
+       { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
+       { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
+       { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
+       { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
        { 0 }
 };
 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
@@ -218,7 +218,9 @@ static struct pci_driver ath5k_pci_driver = {
  * Prototypes - MAC 802.11 stack related functions
  */
 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
-static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
+static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
+               struct ath5k_txq *txq);
+static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
 static int ath5k_reset_wake(struct ath5k_softc *sc);
 static int ath5k_start(struct ieee80211_hw *hw);
 static void ath5k_stop(struct ieee80211_hw *hw);
@@ -227,13 +229,12 @@ static int ath5k_add_interface(struct ieee80211_hw *hw,
 static void ath5k_remove_interface(struct ieee80211_hw *hw,
                struct ieee80211_if_init_conf *conf);
 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
-static int ath5k_config_interface(struct ieee80211_hw *hw,
-               struct ieee80211_vif *vif,
-               struct ieee80211_if_conf *conf);
+static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
+                                  int mc_count, struct dev_addr_list *mc_list);
 static void ath5k_configure_filter(struct ieee80211_hw *hw,
                unsigned int changed_flags,
                unsigned int *new_flags,
-               int mc_count, struct dev_mc_list *mclist);
+               u64 multicast);
 static int ath5k_set_key(struct ieee80211_hw *hw,
                enum set_key_cmd cmd,
                struct ieee80211_vif *vif, struct ieee80211_sta *sta,
@@ -245,12 +246,14 @@ static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
-static int ath5k_beacon_update(struct ath5k_softc *sc,
-               struct sk_buff *skb);
+static int ath5k_beacon_update(struct ieee80211_hw *hw,
+               struct ieee80211_vif *vif);
 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
                struct ieee80211_vif *vif,
                struct ieee80211_bss_conf *bss_conf,
                u32 changes);
+static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
+static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
 
 static const struct ieee80211_ops ath5k_hw_ops = {
        .tx             = ath5k_tx,
@@ -259,7 +262,7 @@ static const struct ieee80211_ops ath5k_hw_ops = {
        .add_interface  = ath5k_add_interface,
        .remove_interface = ath5k_remove_interface,
        .config         = ath5k_config,
-       .config_interface = ath5k_config_interface,
+       .prepare_multicast = ath5k_prepare_multicast,
        .configure_filter = ath5k_configure_filter,
        .set_key        = ath5k_set_key,
        .get_stats      = ath5k_get_stats,
@@ -269,6 +272,8 @@ static const struct ieee80211_ops ath5k_hw_ops = {
        .set_tsf        = ath5k_set_tsf,
        .reset_tsf      = ath5k_reset_tsf,
        .bss_info_changed = ath5k_bss_info_changed,
+       .sw_scan_start  = ath5k_sw_scan_start,
+       .sw_scan_complete = ath5k_sw_scan_complete,
 };
 
 /*
@@ -301,7 +306,8 @@ static void ath5k_desc_free(struct ath5k_softc *sc,
 static int     ath5k_rxbuf_setup(struct ath5k_softc *sc,
                                struct ath5k_buf *bf);
 static int     ath5k_txbuf_setup(struct ath5k_softc *sc,
-                               struct ath5k_buf *bf);
+                               struct ath5k_buf *bf,
+                               struct ath5k_txq *txq);
 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
                                struct ath5k_buf *bf)
 {
@@ -373,7 +379,7 @@ static int  ath5k_stop_hw(struct ath5k_softc *sc);
 static irqreturn_t ath5k_intr(int irq, void *dev_id);
 static void    ath5k_tasklet_reset(unsigned long data);
 
-static void    ath5k_calibrate(unsigned long data);
+static void    ath5k_tasklet_calibrate(unsigned long data);
 
 /*
  * Module init/exit functions
@@ -468,7 +474,7 @@ ath5k_pci_probe(struct pci_dev *pdev,
                 * DMA to work so force a reasonable value here if it
                 * comes up zero.
                 */
-               csz = L1_CACHE_BYTES / sizeof(u32);
+               csz = L1_CACHE_BYTES >> 2;
                pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
        }
        /*
@@ -516,10 +522,12 @@ ath5k_pci_probe(struct pci_dev *pdev,
        /* Initialize driver private data */
        SET_IEEE80211_DEV(hw, &pdev->dev);
        hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
+                   IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
                    IEEE80211_HW_SIGNAL_DBM |
                    IEEE80211_HW_NOISE_DBM;
 
        hw->wiphy->interface_modes =
+               BIT(NL80211_IFTYPE_AP) |
                BIT(NL80211_IFTYPE_STATION) |
                BIT(NL80211_IFTYPE_ADHOC) |
                BIT(NL80211_IFTYPE_MESH_POINT);
@@ -539,8 +547,9 @@ ath5k_pci_probe(struct pci_dev *pdev,
        __set_bit(ATH_STAT_INVALID, sc->status);
 
        sc->iobase = mem; /* So we can unmap it on detach */
-       sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
+       sc->common.cachelsz = csz << 2; /* convert to bytes */
        sc->opmode = NL80211_IFTYPE_STATION;
+       sc->bintval = 1000;
        mutex_init(&sc->lock);
        spin_lock_init(&sc->rxbuflock);
        spin_lock_init(&sc->txbuflock);
@@ -557,7 +566,7 @@ ath5k_pci_probe(struct pci_dev *pdev,
        }
 
        /* Initialize device */
-       sc->ah = ath5k_hw_attach(sc, id->driver_data);
+       sc->ah = ath5k_hw_attach(sc);
        if (IS_ERR(sc->ah)) {
                ret = PTR_ERR(sc->ah);
                goto err_irq;
@@ -668,7 +677,6 @@ ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 
        ath5k_led_off(sc);
 
-       free_irq(pdev->irq, sc);
        pci_save_state(pdev);
        pci_disable_device(pdev);
        pci_set_power_state(pdev, PCI_D3hot);
@@ -689,18 +697,15 @@ ath5k_pci_resume(struct pci_dev *pdev)
        if (err)
                return err;
 
-       err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
-       if (err) {
-               ATH5K_ERR(sc, "request_irq failed\n");
-               goto err_no_irq;
-       }
+       /*
+        * Suspend/Resume resets the PCI configuration space, so we have to
+        * re-disable the RETRY_TIMEOUT register (0x41) to keep
+        * PCI Tx retries from interfering with C3 CPU state
+        */
+       pci_write_config_byte(pdev, 0x41, 0);
 
        ath5k_led_enable(sc);
        return 0;
-
-err_no_irq:
-       pci_disable_device(pdev);
-       return err;
 }
 #endif /* CONFIG_PM */
 
@@ -713,9 +718,9 @@ static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *re
 {
        struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
        struct ath5k_softc *sc = hw->priv;
-       struct ath_regulatory *reg = &sc->ah->ah_regulatory;
+       struct ath_regulatory *regulatory = &sc->common.regulatory;
 
-       return ath_reg_notifier_apply(wiphy, request, reg);
+       return ath_reg_notifier_apply(wiphy, request, regulatory);
 }
 
 static int
@@ -723,6 +728,7 @@ ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
 {
        struct ath5k_softc *sc = hw->priv;
        struct ath5k_hw *ah = sc->ah;
+       struct ath_regulatory *regulatory = &sc->common.regulatory;
        u8 mac[ETH_ALEN] = {};
        int ret;
 
@@ -780,19 +786,25 @@ ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
                goto err_desc;
        }
        sc->bhalq = ret;
+       sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
+       if (IS_ERR(sc->cabq)) {
+               ATH5K_ERR(sc, "can't setup cab queue\n");
+               ret = PTR_ERR(sc->cabq);
+               goto err_bhal;
+       }
 
        sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
        if (IS_ERR(sc->txq)) {
                ATH5K_ERR(sc, "can't setup xmit queue\n");
                ret = PTR_ERR(sc->txq);
-               goto err_bhal;
+               goto err_queues;
        }
 
        tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
        tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
        tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
+       tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
        tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
-       setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
 
        ret = ath5k_eeprom_read_mac(ah, mac);
        if (ret) {
@@ -806,9 +818,8 @@ ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
        memset(sc->bssidmask, 0xff, ETH_ALEN);
        ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
 
-       ah->ah_regulatory.current_rd =
-               ah->ah_capabilities.cap_eeprom.ee_regdomain;
-       ret = ath_regd_init(&ah->ah_regulatory, hw->wiphy, ath5k_reg_notifier);
+       regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
+       ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
        if (ret) {
                ATH5K_ERR(sc, "can't initialize regulatory system\n");
                goto err_queues;
@@ -820,8 +831,8 @@ ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
                goto err_queues;
        }
 
-       if (!ath_is_world_regd(&sc->ah->ah_regulatory))
-               regulatory_hint(hw->wiphy, sc->ah->ah_regulatory.alpha2);
+       if (!ath_is_world_regd(regulatory))
+               regulatory_hint(hw->wiphy, regulatory->alpha2);
 
        ath5k_init_leds(sc);
 
@@ -1063,10 +1074,9 @@ ath5k_setup_bands(struct ieee80211_hw *hw)
 }
 
 /*
- * Set/change channels.  If the channel is really being changed,
- * it's done by reseting the chip.  To accomplish this we must
- * first cleanup any pending DMA, then restart stuff after a la
- * ath5k_init.
+ * Set/change channels. We always reset the chip.
+ * To accomplish this we must first cleanup any pending DMA,
+ * then restart stuff after a la  ath5k_init.
  *
  * Called with sc->lock.
  */
@@ -1076,22 +1086,13 @@ ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
        ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
                sc->curchan->center_freq, chan->center_freq);
 
-       if (chan->center_freq != sc->curchan->center_freq ||
-               chan->hw_value != sc->curchan->hw_value) {
-
-               sc->curchan = chan;
-               sc->curband = &sc->sbands[chan->band];
-
-               /*
-                * To switch channels clear any pending DMA operations;
-                * wait long enough for the RX fifo to drain, reset the
-                * hardware at the new frequency, and then re-enable
-                * the relevant bits of the h/w.
-                */
-               return ath5k_reset(sc, true, true);
-       }
-
-       return 0;
+       /*
+        * To switch channels clear any pending DMA operations;
+        * wait long enough for the RX fifo to drain, reset the
+        * hardware at the new frequency, and then re-enable
+        * the relevant bits of the h/w.
+        */
+       return ath5k_reset(sc, chan);
 }
 
 static void
@@ -1112,6 +1113,8 @@ ath5k_mode_setup(struct ath5k_softc *sc)
        struct ath5k_hw *ah = sc->ah;
        u32 rfilt;
 
+       ah->ah_op_mode = sc->opmode;
+
        /* configure rx filter */
        rfilt = sc->filter_flags;
        ath5k_hw_set_rx_filter(ah, rfilt);
@@ -1122,7 +1125,6 @@ ath5k_mode_setup(struct ath5k_softc *sc)
        /* configure operational mode */
        ath5k_hw_set_opmode(ah);
 
-       ath5k_hw_set_mcast_filter(ah, 0, 0);
        ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
 }
 
@@ -1151,27 +1153,20 @@ static
 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
 {
        struct sk_buff *skb;
-       unsigned int off;
 
        /*
         * Allocate buffer with headroom_needed space for the
         * fake physical layer header at the start.
         */
-       skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
+       skb = ath_rxbuf_alloc(&sc->common,
+                             sc->rxbufsize + sc->common.cachelsz - 1,
+                             GFP_ATOMIC);
 
        if (!skb) {
                ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
-                               sc->rxbufsize + sc->cachelsz - 1);
+                               sc->rxbufsize + sc->common.cachelsz - 1);
                return NULL;
        }
-       /*
-        * Cache-line-align.  This is important (for the
-        * 5210 at least) as not doing so causes bogus data
-        * in rx'd frames.
-        */
-       off = ((unsigned long)skb->data) % sc->cachelsz;
-       if (off != 0)
-               skb_reserve(skb, sc->cachelsz - off);
 
        *skb_addr = pci_map_single(sc->pdev,
                skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
@@ -1226,10 +1221,10 @@ ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
 }
 
 static int
-ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
+ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
+                 struct ath5k_txq *txq)
 {
        struct ath5k_hw *ah = sc->ah;
-       struct ath5k_txq *txq = sc->txq;
        struct ath5k_desc *ds = bf->desc;
        struct sk_buff *skb = bf->skb;
        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
@@ -1282,7 +1277,7 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
                ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
                (sc->power_level * 2),
                hw_rate,
-               info->control.rates[0].count, keyidx, 0, flags,
+               info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
                cts_rate, duration);
        if (ret)
                goto err_unmap;
@@ -1613,14 +1608,13 @@ ath5k_rx_start(struct ath5k_softc *sc)
        struct ath5k_buf *bf;
        int ret;
 
-       sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
+       sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->common.cachelsz);
 
        ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
-               sc->cachelsz, sc->rxbufsize);
-
-       sc->rxlink = NULL;
+               sc->common.cachelsz, sc->rxbufsize);
 
        spin_lock_bh(&sc->rxbuflock);
+       sc->rxlink = NULL;
        list_for_each_entry(bf, &sc->rxbuf, list) {
                ret = ath5k_rxbuf_setup(sc, bf);
                if (ret != 0) {
@@ -1629,9 +1623,9 @@ ath5k_rx_start(struct ath5k_softc *sc)
                }
        }
        bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
+       ath5k_hw_set_rxdp(ah, bf->daddr);
        spin_unlock_bh(&sc->rxbuflock);
 
-       ath5k_hw_set_rxdp(ah, bf->daddr);
        ath5k_hw_start_rx_dma(ah);      /* enable recv descriptors */
        ath5k_mode_setup(sc);           /* set filters, etc. */
        ath5k_hw_start_rx_pcu(ah);      /* re-enable PCU/DMA engine */
@@ -1743,39 +1737,10 @@ ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
        }
 }
 
-static void ath5k_tasklet_beacon(unsigned long data)
-{
-       struct ath5k_softc *sc = (struct ath5k_softc *) data;
-
-       /*
-        * Software beacon alert--time to send a beacon.
-        *
-        * In IBSS mode we use this interrupt just to
-        * keep track of the next TBTT (target beacon
-        * transmission time) in order to detect wether
-        * automatic TSF updates happened.
-        */
-       if (sc->opmode == NL80211_IFTYPE_ADHOC) {
-               /* XXX: only if VEOL suppported */
-               u64 tsf = ath5k_hw_get_tsf64(sc->ah);
-               sc->nexttbtt += sc->bintval;
-               ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
-                               "SWBA nexttbtt: %x hw_tu: %x "
-                               "TSF: %llx\n",
-                               sc->nexttbtt,
-                               TSF_TO_TU(tsf),
-                               (unsigned long long) tsf);
-       } else {
-               spin_lock(&sc->block);
-               ath5k_beacon_send(sc);
-               spin_unlock(&sc->block);
-       }
-}
-
 static void
 ath5k_tasklet_rx(unsigned long data)
 {
-       struct ieee80211_rx_status rxs = {};
+       struct ieee80211_rx_status *rxs;
        struct ath5k_rx_status rs = {};
        struct sk_buff *skb, *next_skb;
        dma_addr_t next_skb_addr;
@@ -1785,6 +1750,7 @@ ath5k_tasklet_rx(unsigned long data)
        int ret;
        int hdrlen;
        int padsize;
+       int rx_flag;
 
        spin_lock(&sc->rxbuflock);
        if (list_empty(&sc->rxbuf)) {
@@ -1792,7 +1758,7 @@ ath5k_tasklet_rx(unsigned long data)
                goto unlock;
        }
        do {
-               rxs.flag = 0;
+               rx_flag = 0;
 
                bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
                BUG_ON(bf->skb == NULL);
@@ -1836,7 +1802,7 @@ ath5k_tasklet_rx(unsigned long data)
                                        goto accept;
                        }
                        if (rs.rs_status & AR5K_RXERR_MIC) {
-                               rxs.flag |= RX_FLAG_MMIC_ERROR;
+                               rx_flag |= RX_FLAG_MMIC_ERROR;
                                goto accept;
                        }
 
@@ -1874,6 +1840,7 @@ accept:
                        memmove(skb->data + padsize, skb->data, hdrlen);
                        skb_pull(skb, padsize);
                }
+               rxs = IEEE80211_SKB_RXCB(skb);
 
                /*
                 * always extend the mac timestamp, since this information is
@@ -1895,41 +1862,41 @@ accept:
                 * impossible to comply to that. This affects IBSS merge only
                 * right now, so it's not too bad...
                 */
-               rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
-               rxs.flag |= RX_FLAG_TSFT;
+               rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
+               rxs->flag = rx_flag | RX_FLAG_TSFT;
 
-               rxs.freq = sc->curchan->center_freq;
-               rxs.band = sc->curband->band;
+               rxs->freq = sc->curchan->center_freq;
+               rxs->band = sc->curband->band;
 
-               rxs.noise = sc->ah->ah_noise_floor;
-               rxs.signal = rxs.noise + rs.rs_rssi;
+               rxs->noise = sc->ah->ah_noise_floor;
+               rxs->signal = rxs->noise + rs.rs_rssi;
 
                /* An rssi of 35 indicates you should be able use
                 * 54 Mbps reliably. A more elaborate scheme can be used
                 * here but it requires a map of SNR/throughput for each
                 * possible mode used */
-               rxs.qual = rs.rs_rssi * 100 / 35;
+               rxs->qual = rs.rs_rssi * 100 / 35;
 
                /* rssi can be more than 35 though, anything above that
                 * should be considered at 100% */
-               if (rxs.qual > 100)
-                       rxs.qual = 100;
+               if (rxs->qual > 100)
+                       rxs->qual = 100;
 
-               rxs.antenna = rs.rs_antenna;
-               rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
-               rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
+               rxs->antenna = rs.rs_antenna;
+               rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
+               rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
 
-               if (rxs.rate_idx >= 0 && rs.rs_rate ==
-                   sc->curband->bitrates[rxs.rate_idx].hw_value_short)
-                       rxs.flag |= RX_FLAG_SHORTPRE;
+               if (rxs->rate_idx >= 0 && rs.rs_rate ==
+                   sc->curband->bitrates[rxs->rate_idx].hw_value_short)
+                       rxs->flag |= RX_FLAG_SHORTPRE;
 
                ath5k_debug_dump_skb(sc, skb, "RX  ", 0);
 
                /* check beacons in IBSS mode */
                if (sc->opmode == NL80211_IFTYPE_ADHOC)
-                       ath5k_check_ibss_tsf(sc, skb, &rxs);
+                       ath5k_check_ibss_tsf(sc, skb, rxs);
 
-               __ieee80211_rx(sc->hw, skb, &rxs);
+               ieee80211_rx(sc->hw, skb);
 
                bf->skb = next_skb;
                bf->skbaddr = next_skb_addr;
@@ -2022,9 +1989,12 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
 static void
 ath5k_tasklet_tx(unsigned long data)
 {
+       int i;
        struct ath5k_softc *sc = (void *)data;
 
-       ath5k_tx_processq(sc, sc->txq);
+       for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
+               if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
+                       ath5k_tx_processq(sc, &sc->txqs[i]);
 }
 
 
@@ -2042,7 +2012,8 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
        struct  ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
        struct ath5k_hw *ah = sc->ah;
        struct ath5k_desc *ds;
-       int ret, antenna = 0;
+       int ret = 0;
+       u8 antenna;
        u32 flags;
 
        bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
@@ -2056,23 +2027,35 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
        }
 
        ds = bf->desc;
+       antenna = ah->ah_tx_ant;
 
        flags = AR5K_TXDESC_NOACK;
        if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
                ds->ds_link = bf->daddr;        /* self-linked */
                flags |= AR5K_TXDESC_VEOL;
-               /*
-                * Let hardware handle antenna switching if txantenna is not set
-                */
-       } else {
+       } else
                ds->ds_link = 0;
-               /*
-                * Switch antenna every 4 beacons if txantenna is not set
-                * XXX assumes two antennas
-                */
-               if (antenna == 0)
-                       antenna = sc->bsent & 4 ? 2 : 1;
-       }
+
+       /*
+        * If we use multiple antennas on AP and use
+        * the Sectored AP scenario, switch antenna every
+        * 4 beacons to make sure everybody hears our AP.
+        * When a client tries to associate, hw will keep
+        * track of the tx antenna to be used for this client
+        * automaticaly, based on ACKed packets.
+        *
+        * Note: AP still listens and transmits RTS on the
+        * default antenna which is supposed to be an omni.
+        *
+        * Note2: On sectored scenarios it's possible to have
+        * multiple antennas (1omni -the default- and 14 sectors)
+        * so if we choose to actually support this mode we need
+        * to allow user to set how many antennas we have and tweak
+        * the code below to send beacons on all of them.
+        */
+       if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
+               antenna = sc->bsent & 4 ? 2 : 1;
+
 
        /* FIXME: If we are in g mode and rate is a CCK rate
         * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
@@ -2106,6 +2089,7 @@ ath5k_beacon_send(struct ath5k_softc *sc)
 {
        struct ath5k_buf *bf = sc->bbuf;
        struct ath5k_hw *ah = sc->ah;
+       struct sk_buff *skb;
 
        ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
 
@@ -2125,7 +2109,7 @@ ath5k_beacon_send(struct ath5k_softc *sc)
                sc->bmisscount++;
                ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
                        "missed %u consecutive beacons\n", sc->bmisscount);
-               if (sc->bmisscount > 3) {               /* NB: 3 is a guess */
+               if (sc->bmisscount > 10) {      /* NB: 10 is a guess */
                        ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
                                "stuck beacon time (%u missed)\n",
                                sc->bmisscount);
@@ -2146,15 +2130,25 @@ ath5k_beacon_send(struct ath5k_softc *sc)
         * are still pending on the queue.
         */
        if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
-               ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
+               ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
                /* NB: hw still stops DMA, so proceed */
        }
 
+       /* refresh the beacon for AP mode */
+       if (sc->opmode == NL80211_IFTYPE_AP)
+               ath5k_beacon_update(sc->hw, sc->vif);
+
        ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
        ath5k_hw_start_tx_dma(ah, sc->bhalq);
        ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
                sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
 
+       skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
+       while (skb) {
+               ath5k_tx_queue(sc->hw, skb, sc->cabq);
+               skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
+       }
+
        sc->bsent++;
 }
 
@@ -2275,13 +2269,11 @@ ath5k_beacon_config(struct ath5k_softc *sc)
        struct ath5k_hw *ah = sc->ah;
        unsigned long flags;
 
-       ath5k_hw_set_imr(ah, 0);
+       spin_lock_irqsave(&sc->block, flags);
        sc->bmisscount = 0;
        sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
 
-       if (sc->opmode == NL80211_IFTYPE_ADHOC ||
-                       sc->opmode == NL80211_IFTYPE_MESH_POINT ||
-                       sc->opmode == NL80211_IFTYPE_AP) {
+       if (sc->enable_beacon) {
                /*
                 * In IBSS mode we use a self-linked tx descriptor and let the
                 * hardware send the beacons automatically. We have to load it
@@ -2294,16 +2286,46 @@ ath5k_beacon_config(struct ath5k_softc *sc)
                sc->imask |= AR5K_INT_SWBA;
 
                if (sc->opmode == NL80211_IFTYPE_ADHOC) {
-                       if (ath5k_hw_hasveol(ah)) {
-                               spin_lock_irqsave(&sc->block, flags);
+                       if (ath5k_hw_hasveol(ah))
                                ath5k_beacon_send(sc);
-                               spin_unlock_irqrestore(&sc->block, flags);
-                       }
                } else
                        ath5k_beacon_update_timers(sc, -1);
+       } else {
+               ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
        }
 
        ath5k_hw_set_imr(ah, sc->imask);
+       mmiowb();
+       spin_unlock_irqrestore(&sc->block, flags);
+}
+
+static void ath5k_tasklet_beacon(unsigned long data)
+{
+       struct ath5k_softc *sc = (struct ath5k_softc *) data;
+
+       /*
+        * Software beacon alert--time to send a beacon.
+        *
+        * In IBSS mode we use this interrupt just to
+        * keep track of the next TBTT (target beacon
+        * transmission time) in order to detect wether
+        * automatic TSF updates happened.
+        */
+       if (sc->opmode == NL80211_IFTYPE_ADHOC) {
+               /* XXX: only if VEOL suppported */
+               u64 tsf = ath5k_hw_get_tsf64(sc->ah);
+               sc->nexttbtt += sc->bintval;
+               ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
+                               "SWBA nexttbtt: %x hw_tu: %x "
+                               "TSF: %llx\n",
+                               sc->nexttbtt,
+                               TSF_TO_TU(tsf),
+                               (unsigned long long) tsf);
+       } else {
+               spin_lock(&sc->block);
+               ath5k_beacon_send(sc);
+               spin_unlock(&sc->block);
+       }
 }
 
 
@@ -2338,11 +2360,13 @@ ath5k_init(struct ath5k_softc *sc)
        sc->curband = &sc->sbands[sc->curchan->band];
        sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
                AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
-               AR5K_INT_FATAL | AR5K_INT_GLOBAL;
-       ret = ath5k_reset(sc, false, false);
+               AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI;
+       ret = ath5k_reset(sc, NULL);
        if (ret)
                goto done;
 
+       ath5k_rfkill_hw_start(ah);
+
        /*
         * Reset the key cache since some parts do not reset the
         * contents on initial power up or resume from suspend.
@@ -2353,8 +2377,8 @@ ath5k_init(struct ath5k_softc *sc)
        /* Set ack to be sent at low bit-rates */
        ath5k_hw_set_ack_bitrate_high(ah, false);
 
-       mod_timer(&sc->calib_tim, round_jiffies(jiffies +
-                       msecs_to_jiffies(ath5k_calinterval * 1000)));
+       /* Set PHY calibration inteval */
+       ah->ah_cal_intval = ath5k_calinterval;
 
        ret = 0;
 done:
@@ -2418,39 +2442,43 @@ ath5k_stop_hw(struct ath5k_softc *sc)
        ret = ath5k_stop_locked(sc);
        if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
                /*
-                * Set the chip in full sleep mode.  Note that we are
-                * careful to do this only when bringing the interface
-                * completely to a stop.  When the chip is in this state
-                * it must be carefully woken up or references to
-                * registers in the PCI clock domain may freeze the bus
-                * (and system).  This varies by chip and is mostly an
-                * issue with newer parts that go to sleep more quickly.
-                */
-               if (sc->ah->ah_mac_srev >= 0x78) {
-                       /*
-                        * XXX
-                        * don't put newer MAC revisions > 7.8 to sleep because
-                        * of the above mentioned problems
-                        */
-                       ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
-                               "not putting device to sleep\n");
-               } else {
-                       ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
-                               "putting device to full sleep\n");
-                       ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
-               }
+                * Don't set the card in full sleep mode!
+                *
+                * a) When the device is in this state it must be carefully
+                * woken up or references to registers in the PCI clock
+                * domain may freeze the bus (and system).  This varies
+                * by chip and is mostly an issue with newer parts
+                * (madwifi sources mentioned srev >= 0x78) that go to
+                * sleep more quickly.
+                *
+                * b) On older chips full sleep results a weird behaviour
+                * during wakeup. I tested various cards with srev < 0x78
+                * and they don't wake up after module reload, a second
+                * module reload is needed to bring the card up again.
+                *
+                * Until we figure out what's going on don't enable
+                * full chip reset on any chip (this is what Legacy HAL
+                * and Sam's HAL do anyway). Instead Perform a full reset
+                * on the device (same as initial state after attach) and
+                * leave it idle (keep MAC/BB on warm reset) */
+               ret = ath5k_hw_on_hold(sc->ah);
+
+               ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
+                               "putting device to sleep\n");
        }
        ath5k_txbuf_free(sc, sc->bbuf);
 
        mmiowb();
        mutex_unlock(&sc->lock);
 
-       del_timer_sync(&sc->calib_tim);
        tasklet_kill(&sc->rxtq);
        tasklet_kill(&sc->txtq);
        tasklet_kill(&sc->restq);
+       tasklet_kill(&sc->calib);
        tasklet_kill(&sc->beacontq);
 
+       ath5k_rfkill_hw_stop(sc->ah);
+
        return ret;
 }
 
@@ -2502,6 +2530,9 @@ ath5k_intr(int irq, void *dev_id)
                        if (status & AR5K_INT_BMISS) {
                                /* TODO */
                        }
+                       if (status & AR5K_INT_SWI) {
+                               tasklet_schedule(&sc->calib);
+                       }
                        if (status & AR5K_INT_MIB) {
                                /*
                                 * These stats are also used for ANI i think
@@ -2509,12 +2540,17 @@ ath5k_intr(int irq, void *dev_id)
                                 */
                                ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
                        }
+                       if (status & AR5K_INT_GPIO)
+                               tasklet_schedule(&sc->rf_kill.toggleq);
+
                }
-       } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
+       } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
 
        if (unlikely(!counter))
                ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
 
+       ath5k_hw_calibration_poll(ah);
+
        return IRQ_HANDLED;
 }
 
@@ -2531,11 +2567,19 @@ ath5k_tasklet_reset(unsigned long data)
  * for temperature/environment changes.
  */
 static void
-ath5k_calibrate(unsigned long data)
+ath5k_tasklet_calibrate(unsigned long data)
 {
        struct ath5k_softc *sc = (void *)data;
        struct ath5k_hw *ah = sc->ah;
 
+       /* Only full calibration for now */
+       if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION)
+               return;
+
+       /* Stop queues so that calibration
+        * doesn't interfere with tx */
+       ieee80211_stop_queues(sc->hw);
+
        ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
                ieee80211_frequency_to_channel(sc->curchan->center_freq),
                sc->curchan->hw_value);
@@ -2553,8 +2597,11 @@ ath5k_calibrate(unsigned long data)
                        ieee80211_frequency_to_channel(
                                sc->curchan->center_freq));
 
-       mod_timer(&sc->calib_tim, round_jiffies(jiffies +
-                       msecs_to_jiffies(ath5k_calinterval * 1000)));
+       ah->ah_swi_mask = 0;
+
+       /* Wake queues */
+       ieee80211_wake_queues(sc->hw);
+
 }
 
 
@@ -2566,6 +2613,14 @@ static int
 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
 {
        struct ath5k_softc *sc = hw->priv;
+
+       return ath5k_tx_queue(hw, skb, sc->txq);
+}
+
+static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
+                         struct ath5k_txq *txq)
+{
+       struct ath5k_softc *sc = hw->priv;
        struct ath5k_buf *bf;
        unsigned long flags;
        int hdrlen;
@@ -2609,7 +2664,7 @@ ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
 
        bf->skb = skb;
 
-       if (ath5k_txbuf_setup(sc, bf)) {
+       if (ath5k_txbuf_setup(sc, bf, txq)) {
                bf->skb = NULL;
                spin_lock_irqsave(&sc->txbuflock, flags);
                list_add_tail(&bf->list, &sc->txbuf);
@@ -2624,20 +2679,27 @@ drop_packet:
        return NETDEV_TX_OK;
 }
 
+/*
+ * Reset the hardware.  If chan is not NULL, then also pause rx/tx
+ * and change to the given channel.
+ */
 static int
-ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
+ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
 {
        struct ath5k_hw *ah = sc->ah;
        int ret;
 
        ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
 
-       if (stop) {
+       if (chan) {
                ath5k_hw_set_imr(ah, 0);
                ath5k_txq_cleanup(sc);
                ath5k_rx_stop(sc);
+
+               sc->curchan = chan;
+               sc->curband = &sc->sbands[chan->band];
        }
-       ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
+       ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
        if (ret) {
                ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
                goto err;
@@ -2673,7 +2735,7 @@ ath5k_reset_wake(struct ath5k_softc *sc)
 {
        int ret;
 
-       ret = ath5k_reset(sc, true, true);
+       ret = ath5k_reset(sc, sc->curchan);
        if (!ret)
                ieee80211_wake_queues(sc->hw);
 
@@ -2717,10 +2779,8 @@ static int ath5k_add_interface(struct ieee80211_hw *hw,
                goto end;
        }
 
-       /* Set to a reasonable value. Note that this will
-        * be set to mac80211's value at ath5k_config(). */
-       sc->bintval = 1000;
        ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
+       ath5k_mode_setup(sc);
 
        ret = 0;
 end:
@@ -2752,56 +2812,79 @@ static int
 ath5k_config(struct ieee80211_hw *hw, u32 changed)
 {
        struct ath5k_softc *sc = hw->priv;
+       struct ath5k_hw *ah = sc->ah;
        struct ieee80211_conf *conf = &hw->conf;
-       int ret;
+       int ret = 0;
 
        mutex_lock(&sc->lock);
 
-       sc->bintval = conf->beacon_int;
-       sc->power_level = conf->power_level;
+       if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
+               ret = ath5k_chan_set(sc, conf->channel);
+               if (ret < 0)
+                       goto unlock;
+       }
+
+       if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
+       (sc->power_level != conf->power_level)) {
+               sc->power_level = conf->power_level;
+
+               /* Half dB steps */
+               ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
+       }
 
-       ret = ath5k_chan_set(sc, conf->channel);
+       /* TODO:
+        * 1) Move this on config_interface and handle each case
+        * separately eg. when we have only one STA vif, use
+        * AR5K_ANTMODE_SINGLE_AP
+        *
+        * 2) Allow the user to change antenna mode eg. when only
+        * one antenna is present
+        *
+        * 3) Allow the user to set default/tx antenna when possible
+        *
+        * 4) Default mode should handle 90% of the cases, together
+        * with fixed a/b and single AP modes we should be able to
+        * handle 99%. Sectored modes are extreme cases and i still
+        * haven't found a usage for them. If we decide to support them,
+        * then we must allow the user to set how many tx antennas we
+        * have available
+        */
+       ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
 
+unlock:
        mutex_unlock(&sc->lock);
        return ret;
 }
 
-static int
-ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
-                       struct ieee80211_if_conf *conf)
+static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
+                                  int mc_count, struct dev_addr_list *mclist)
 {
-       struct ath5k_softc *sc = hw->priv;
-       struct ath5k_hw *ah = sc->ah;
-       int ret = 0;
+       u32 mfilt[2], val;
+       int i;
+       u8 pos;
 
-       mutex_lock(&sc->lock);
-       if (sc->vif != vif) {
-               ret = -EIO;
-               goto unlock;
-       }
-       if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
-               /* Cache for later use during resets */
-               memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
-               /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
-                * a clean way of letting us retrieve this yet. */
-               ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
-               mmiowb();
-       }
-       if (conf->changed & IEEE80211_IFCC_BEACON &&
-                       (vif->type == NL80211_IFTYPE_ADHOC ||
-                        vif->type == NL80211_IFTYPE_MESH_POINT ||
-                        vif->type == NL80211_IFTYPE_AP)) {
-               struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
-               if (!beacon) {
-                       ret = -ENOMEM;
-                       goto unlock;
-               }
-               ath5k_beacon_update(sc, beacon);
+       mfilt[0] = 0;
+       mfilt[1] = 1;
+
+       for (i = 0; i < mc_count; i++) {
+               if (!mclist)
+                       break;
+               /* calculate XOR of eight 6-bit values */
+               val = get_unaligned_le32(mclist->dmi_addr + 0);
+               pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
+               val = get_unaligned_le32(mclist->dmi_addr + 3);
+               pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
+               pos &= 0x3f;
+               mfilt[pos / 32] |= (1 << (pos % 32));
+               /* XXX: we might be able to just do this instead,
+               * but not sure, needs testing, if we do use this we'd
+               * neet to inform below to not reset the mcast */
+               /* ath5k_hw_set_mcast_filterindex(ah,
+                *      mclist->dmi_addr[5]); */
+               mclist = mclist->next;
        }
 
-unlock:
-       mutex_unlock(&sc->lock);
-       return ret;
+       return ((u64)(mfilt[1]) << 32) | mfilt[0];
 }
 
 #define SUPPORTED_FIF_FLAGS \
@@ -2829,16 +2912,16 @@ unlock:
 static void ath5k_configure_filter(struct ieee80211_hw *hw,
                unsigned int changed_flags,
                unsigned int *new_flags,
-               int mc_count, struct dev_mc_list *mclist)
+               u64 multicast)
 {
        struct ath5k_softc *sc = hw->priv;
        struct ath5k_hw *ah = sc->ah;
-       u32 mfilt[2], val, rfilt;
-       u8 pos;
-       int i;
+       u32 mfilt[2], rfilt;
 
-       mfilt[0] = 0;
-       mfilt[1] = 0;
+       mutex_lock(&sc->lock);
+
+       mfilt[0] = multicast;
+       mfilt[1] = multicast >> 32;
 
        /* Only deal with supported flags */
        changed_flags &= SUPPORTED_FIF_FLAGS;
@@ -2864,24 +2947,6 @@ static void ath5k_configure_filter(struct ieee80211_hw *hw,
        if (*new_flags & FIF_ALLMULTI) {
                mfilt[0] =  ~0;
                mfilt[1] =  ~0;
-       } else {
-               for (i = 0; i < mc_count; i++) {
-                       if (!mclist)
-                               break;
-                       /* calculate XOR of eight 6-bit values */
-                       val = get_unaligned_le32(mclist->dmi_addr + 0);
-                       pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
-                       val = get_unaligned_le32(mclist->dmi_addr + 3);
-                       pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
-                       pos &= 0x3f;
-                       mfilt[pos / 32] |= (1 << (pos % 32));
-                       /* XXX: we might be able to just do this instead,
-                       * but not sure, needs testing, if we do use this we'd
-                       * neet to inform below to not reset the mcast */
-                       /* ath5k_hw_set_mcast_filterindex(ah,
-                        *      mclist->dmi_addr[5]); */
-                       mclist = mclist->next;
-               }
        }
 
        /* This is the best we can do */
@@ -2905,22 +2970,25 @@ static void ath5k_configure_filter(struct ieee80211_hw *hw,
 
        /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
 
-       if (sc->opmode == NL80211_IFTYPE_MONITOR)
-               rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
-                       AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
-       if (sc->opmode != NL80211_IFTYPE_STATION)
-               rfilt |= AR5K_RX_FILTER_PROBEREQ;
-       if (sc->opmode != NL80211_IFTYPE_AP &&
-               sc->opmode != NL80211_IFTYPE_MESH_POINT &&
-               test_bit(ATH_STAT_PROMISC, sc->status))
-               rfilt |= AR5K_RX_FILTER_PROM;
-       if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
-               sc->opmode == NL80211_IFTYPE_ADHOC ||
-               sc->opmode == NL80211_IFTYPE_AP)
-               rfilt |= AR5K_RX_FILTER_BEACON;
-       if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
-               rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
-                       AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
+       switch (sc->opmode) {
+       case NL80211_IFTYPE_MESH_POINT:
+       case NL80211_IFTYPE_MONITOR:
+               rfilt |= AR5K_RX_FILTER_CONTROL |
+                        AR5K_RX_FILTER_BEACON |
+                        AR5K_RX_FILTER_PROBEREQ |
+                        AR5K_RX_FILTER_PROM;
+               break;
+       case NL80211_IFTYPE_AP:
+       case NL80211_IFTYPE_ADHOC:
+               rfilt |= AR5K_RX_FILTER_PROBEREQ |
+                        AR5K_RX_FILTER_BEACON;
+               break;
+       case NL80211_IFTYPE_STATION:
+               if (sc->assoc)
+                       rfilt |= AR5K_RX_FILTER_BEACON;
+       default:
+               break;
+       }
 
        /* Set filters */
        ath5k_hw_set_rx_filter(ah, rfilt);
@@ -2930,6 +2998,8 @@ static void ath5k_configure_filter(struct ieee80211_hw *hw,
        /* Set the cached hw filter flags, this will alter actually
         * be set in HW */
        sc->filter_flags = rfilt;
+
+       mutex_unlock(&sc->lock);
 }
 
 static int
@@ -2943,11 +3013,17 @@ ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
        if (modparam_nohwcrypt)
                return -EOPNOTSUPP;
 
+       if (sc->opmode == NL80211_IFTYPE_AP)
+               return -EOPNOTSUPP;
+
        switch (key->alg) {
        case ALG_WEP:
        case ALG_TKIP:
                break;
        case ALG_CCMP:
+               if (sc->ah->ah_aes_support)
+                       break;
+
                return -EOPNOTSUPP;
        default:
                WARN_ON(1);
@@ -3041,28 +3117,43 @@ ath5k_reset_tsf(struct ieee80211_hw *hw)
                ath5k_hw_reset_tsf(sc->ah);
 }
 
+/*
+ * Updates the beacon that is sent by ath5k_beacon_send.  For adhoc,
+ * this is called only once at config_bss time, for AP we do it every
+ * SWBA interrupt so that the TIM will reflect buffered frames.
+ *
+ * Called with the beacon lock.
+ */
 static int
-ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
+ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
 {
-       unsigned long flags;
        int ret;
+       struct ath5k_softc *sc = hw->priv;
+       struct sk_buff *skb;
+
+       if (WARN_ON(!vif)) {
+               ret = -EINVAL;
+               goto out;
+       }
+
+       skb = ieee80211_beacon_get(hw, vif);
+
+       if (!skb) {
+               ret = -ENOMEM;
+               goto out;
+       }
 
        ath5k_debug_dump_skb(sc, skb, "BC  ", 1);
 
-       spin_lock_irqsave(&sc->block, flags);
        ath5k_txbuf_free(sc, sc->bbuf);
        sc->bbuf->skb = skb;
        ret = ath5k_beacon_setup(sc, sc->bbuf);
        if (ret)
                sc->bbuf->skb = NULL;
-       spin_unlock_irqrestore(&sc->block, flags);
-       if (!ret) {
-               ath5k_beacon_config(sc);
-               mmiowb();
-       }
-
+out:
        return ret;
 }
+
 static void
 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
 {
@@ -3084,11 +3175,60 @@ static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
                                    u32 changes)
 {
        struct ath5k_softc *sc = hw->priv;
+       struct ath5k_hw *ah = sc->ah;
+       unsigned long flags;
+
+       mutex_lock(&sc->lock);
+       if (WARN_ON(sc->vif != vif))
+               goto unlock;
+
+       if (changes & BSS_CHANGED_BSSID) {
+               /* Cache for later use during resets */
+               memcpy(ah->ah_bssid, bss_conf->bssid, ETH_ALEN);
+               /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
+                * a clean way of letting us retrieve this yet. */
+               ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
+               mmiowb();
+       }
+
+       if (changes & BSS_CHANGED_BEACON_INT)
+               sc->bintval = bss_conf->beacon_int;
+
        if (changes & BSS_CHANGED_ASSOC) {
-               mutex_lock(&sc->lock);
                sc->assoc = bss_conf->assoc;
                if (sc->opmode == NL80211_IFTYPE_STATION)
                        set_beacon_filter(hw, sc->assoc);
-               mutex_unlock(&sc->lock);
+               ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
+                       AR5K_LED_ASSOC : AR5K_LED_INIT);
+       }
+
+       if (changes & BSS_CHANGED_BEACON) {
+               spin_lock_irqsave(&sc->block, flags);
+               ath5k_beacon_update(hw, vif);
+               spin_unlock_irqrestore(&sc->block, flags);
        }
+
+       if (changes & BSS_CHANGED_BEACON_ENABLED)
+               sc->enable_beacon = bss_conf->enable_beacon;
+
+       if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
+                      BSS_CHANGED_BEACON_INT))
+               ath5k_beacon_config(sc);
+
+ unlock:
+       mutex_unlock(&sc->lock);
+}
+
+static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
+{
+       struct ath5k_softc *sc = hw->priv;
+       if (!sc->assoc)
+               ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
+}
+
+static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
+{
+       struct ath5k_softc *sc = hw->priv;
+       ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
+               AR5K_LED_ASSOC : AR5K_LED_INIT);
 }