drivers: wireless: bcm4329: set MMC_PM_KEEP_POWER on suspend
[linux-2.6.git] / drivers / net / tg3.h
index e7880d5..2ea456d 100644 (file)
@@ -23,8 +23,6 @@
 #define TG3_BDINFO_NIC_ADDR            0xcUL /* 32-bit */
 #define TG3_BDINFO_SIZE                        0x10UL
 
-#define TG3_RX_INTERNAL_RING_SZ_5906   32
-
 #define TG3_RX_STD_MAX_SIZE_5700       512
 #define TG3_RX_STD_MAX_SIZE_5717       2048
 #define TG3_RX_JMB_MAX_SIZE_5700       256
 #define  CHIPREV_ID_5717_A0             0x05717000
 #define  CHIPREV_ID_57765_A0            0x57785000
 #define  CHIPREV_ID_5719_A0             0x05719000
+#define  CHIPREV_ID_5720_A0             0x05720000
 #define  GET_ASIC_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700                         0x07
 #define   ASIC_REV_5701                         0x00
 #define   CHIPREV_5750_BX               0x41
 #define   CHIPREV_5784_AX               0x57840
 #define   CHIPREV_5761_AX               0x57610
+#define   CHIPREV_57765_AX              0x577650
 #define  GET_METAL_REV(CHIP_REV_ID)    ((CHIP_REV_ID) & 0xff)
 #define   METAL_REV_A0                  0x00
 #define   METAL_REV_A1                  0x01
 #define   METAL_REV_B2                  0x02
 #define TG3PCI_DMA_RW_CTRL             0x0000006c
 #define  DMA_RWCTRL_DIS_CACHE_ALIGNMENT  0x00000001
+#define  DMA_RWCTRL_TAGGED_STAT_WA      0x00000080
 #define  DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380
 #define  DMA_RWCTRL_READ_BNDRY_MASK     0x00000700
 #define  DMA_RWCTRL_READ_BNDRY_DISAB    0x00000000
 #define  RCVLSC_STATUS_ERROR_ATTN       0x00000004
 /* 0x3408 --> 0x3600 unused */
 
+#define TG3_CPMU_DRV_STATUS            0x0000344c
+
 /* CPMU registers */
 #define TG3_CPMU_CTRL                  0x00003600
 #define  CPMU_CTRL_LINK_IDLE_MODE       0x00000200
 #define  TG3_CPMU_EEEMD_EEE_ENABLE      0x00100000
 #define TG3_CPMU_EEE_DBTMR1            0x000036b4
 #define  TG3_CPMU_DBTMR1_PCIEXIT_2047US         0x07ff0000
-#define  TG3_CPMU_DBTMR1_LNKIDLE_2047US         0x000070ff
+#define  TG3_CPMU_DBTMR1_LNKIDLE_2047US         0x000007ff
 #define TG3_CPMU_EEE_DBTMR2            0x000036b8
 #define  TG3_CPMU_DBTMR2_APE_TX_2047US  0x07ff0000
-#define  TG3_CPMU_DBTMR2_TXIDXEQ_2047US         0x000070ff
+#define  TG3_CPMU_DBTMR2_TXIDXEQ_2047US         0x000007ff
 #define TG3_CPMU_EEE_LNKIDL_CTRL       0x000036bc
 #define  TG3_CPMU_EEE_LNKIDL_PCIE_NL0   0x01000000
 #define  TG3_CPMU_EEE_LNKIDL_UART_IDL   0x00000004
 #define HOSTCC_STATS_BLK_NIC_ADDR      0x00003c40
 #define HOSTCC_STATUS_BLK_NIC_ADDR     0x00003c44
 #define HOSTCC_FLOW_ATTN               0x00003c48
+#define HOSTCC_FLOW_ATTN_MBUF_LWM       0x00000040
 /* 0x3c4c --> 0x3c50 unused */
 #define HOSTCC_JUMBO_CON_IDX           0x00003c50
 #define HOSTCC_STD_CON_IDX             0x00003c54
 #define  MSGINT_MODE_ONE_SHOT_DISABLE   0x00000020
 #define  MSGINT_MODE_MULTIVEC_EN        0x00000080
 #define MSGINT_STATUS                  0x00006004
+#define  MSGINT_STATUS_MSI_REQ          0x00000001
 #define MSGINT_FIFO                    0x00006008
 /* 0x600c --> 0x6400 unused */
 
 
 /* Alternate PCIE definitions */
 #define TG3_PCIE_TLDLPL_PORT           0x00007c00
+#define TG3_PCIE_DL_LO_FTSMAX          0x0000000c
+#define TG3_PCIE_DL_LO_FTSMAX_MSK      0x000000ff
+#define TG3_PCIE_DL_LO_FTSMAX_VAL      0x0000002c
 #define TG3_PCIE_PL_LO_PHYCTL1          0x00000004
 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN        0x00001000
 #define TG3_PCIE_PL_LO_PHYCTL5          0x00000014
 #define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ      0x80000000
 
+#define TG3_REG_BLK_SIZE               0x00008000
+
 /* OTP bit definitions */
 #define TG3_OTP_AGCTGT_MASK            0x000000e0
 #define TG3_OTP_AGCTGT_SHIFT           1
 #define TG3_NVM_DIR_END                        0x78
 #define TG3_NVM_DIRENT_SIZE            0xc
 #define TG3_NVM_DIRTYPE_SHIFT          24
+#define TG3_NVM_DIRTYPE_LENMSK         0x003fffff
 #define TG3_NVM_DIRTYPE_ASFINI         1
+#define TG3_NVM_DIRTYPE_EXTVPD         20
 #define TG3_NVM_PTREV_BCVER            0x94
 #define TG3_NVM_BCVER_MAJMSK           0x0000ff00
 #define TG3_NVM_BCVER_MAJSFT           8
 #define  NIC_SRAM_MBUF_POOL_BASE5705   0x00010000
 #define  NIC_SRAM_MBUF_POOL_SIZE5705   0x0000e000
 
+#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700      128
+#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755      64
+#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906      32
+
+#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700      64
+#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717      16
+
 
 /* Currently this is fixed. */
 #define TG3_PHY_MII_ADDR               0x01
 
 
 /*** Tigon3 specific PHY MII registers. ***/
-#define  TG3_BMCR_SPEED1000            0x0040
-
-#define MII_TG3_CTRL                   0x09 /* 1000-baseT control register */
-#define  MII_TG3_CTRL_ADV_1000_HALF    0x0100
-#define  MII_TG3_CTRL_ADV_1000_FULL    0x0200
-#define  MII_TG3_CTRL_AS_MASTER                0x0800
-#define  MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
-
 #define MII_TG3_MMD_CTRL               0x0d /* MMD Access Control register */
 #define MII_TG3_MMD_CTRL_DATA_NOINC    0x4000
 #define MII_TG3_MMD_ADDRESS            0x0e /* MMD Address Data register */
 #define  MII_TG3_DSP_TAP26_OPCSINPT    0x0004
 #define MII_TG3_DSP_AADJ1CH0           0x001f
 #define MII_TG3_DSP_CH34TP2            0x4022
-#define MII_TG3_DSP_CH34TP2_HIBW01     0x0010
+#define MII_TG3_DSP_CH34TP2_HIBW01     0x01ff
 #define MII_TG3_DSP_AADJ1CH3           0x601f
 #define  MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
 #define MII_TG3_DSP_EXP1_INT_STAT      0x0f01
 #define MII_TG3_DSP_EXP96              0x0f96
 #define MII_TG3_DSP_EXP97              0x0f97
 
-#define MII_TG3_AUX_CTRL               0x18 /* auxilliary control register */
+#define MII_TG3_AUX_CTRL               0x18 /* auxiliary control register */
 
+#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL  0x0000
+#define MII_TG3_AUXCTL_ACTL_TX_6DB     0x0400
+#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA  0x0800
+#define MII_TG3_AUXCTL_ACTL_EXTPKTLEN  0x4000
+
+#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL  0x0002
+#define MII_TG3_AUXCTL_PCTL_WOL_EN     0x0008
 #define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010
 #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE        0x0020
+#define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC        0x0040
 #define MII_TG3_AUXCTL_PCTL_VREG_11V   0x0180
-#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL  0x0002
 
-#define MII_TG3_AUXCTL_MISC_WREN       0x8000
-#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX        0x0200
-#define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000
+#define MII_TG3_AUXCTL_SHDWSEL_MISCTEST        0x0004
+
 #define MII_TG3_AUXCTL_SHDWSEL_MISC    0x0007
+#define MII_TG3_AUXCTL_MISC_WIRESPD_EN 0x0010
+#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX        0x0200
+#define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT        12
+#define MII_TG3_AUXCTL_MISC_WREN       0x8000
 
-#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA  0x0800
-#define MII_TG3_AUXCTL_ACTL_TX_6DB     0x0400
-#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL  0x0000
 
-#define MII_TG3_AUX_STAT               0x19 /* auxilliary status register */
+#define MII_TG3_AUX_STAT               0x19 /* auxiliary status register */
 #define MII_TG3_AUX_STAT_LPASS         0x0004
 #define MII_TG3_AUX_STAT_SPDMASK       0x0700
 #define MII_TG3_AUX_STAT_10HALF                0x0100
 
 
 /* APE registers.  Accessible through BAR1 */
+#define TG3_APE_GPIO_MSG               0x0008
+#define TG3_APE_GPIO_MSG_SHIFT         4
 #define TG3_APE_EVENT                  0x000c
 #define  APE_EVENT_1                    0x00000001
 #define TG3_APE_LOCK_REQ               0x002c
 /* APE convenience enumerations. */
 #define TG3_APE_LOCK_GRC                1
 #define TG3_APE_LOCK_MEM                4
+#define TG3_APE_LOCK_GPIO               7
 
 #define TG3_EEPROM_SB_F1R2_MBA_OFF     0x10
 
@@ -2614,7 +2635,12 @@ struct tg3_hw_stats {
        tg3_stat64_t                    nic_avoided_irqs;
        tg3_stat64_t                    nic_tx_threshold_hit;
 
-       u8                              __reserved4[0xb00-0x9c0];
+       /* NOT a part of the hardware statistics block format.
+        * These stats are here as storage for tg3_periodic_fetch_stats().
+        */
+       tg3_stat64_t                    mbuf_lwm_thresh_hit;
+
+       u8                              __reserved4[0xb00-0x9c8];
 };
 
 /* 'mapping' is superfluous as the chip does not write into
@@ -2626,6 +2652,12 @@ struct ring_info {
        DEFINE_DMA_UNMAP_ADDR(mapping);
 };
 
+struct tg3_tx_ring_info {
+       struct sk_buff                  *skb;
+       DEFINE_DMA_UNMAP_ADDR(mapping);
+       bool                            fragmented;
+};
+
 struct tg3_link_config {
        /* Describes what we're trying to get. */
        u32                             advertising;
@@ -2746,6 +2778,8 @@ struct tg3_ethtool_stats {
        u64             nic_irqs;
        u64             nic_avoided_irqs;
        u64             nic_tx_threshold_hit;
+
+       u64             mbuf_lwm_thresh_hit;
 };
 
 struct tg3_rx_prodring_set {
@@ -2769,6 +2803,7 @@ struct tg3_napi {
        struct tg3                      *tp;
        struct tg3_hw_status            *hw_status;
 
+       u32                             chk_msi_cnt;
        u32                             last_tag;
        u32                             last_irq_tag;
        u32                             int_mbox;
@@ -2776,6 +2811,7 @@ struct tg3_napi {
 
        u32                             consmbox ____cacheline_aligned;
        u32                             rx_rcb_ptr;
+       u32                             last_rx_cons;
        u16                             *rx_rcb_prod_idx;
        struct tg3_rx_prodring_set      prodring;
        struct tg3_rx_buffer_desc       *rx_rcb;
@@ -2783,9 +2819,10 @@ struct tg3_napi {
        u32                             tx_prod ____cacheline_aligned;
        u32                             tx_cons;
        u32                             tx_pending;
+       u32                             last_tx_cons;
        u32                             prodmbox;
        struct tg3_tx_buffer_desc       *tx_ring;
-       struct ring_info                *tx_buffers;
+       struct tg3_tx_ring_info         *tx_buffers;
 
        dma_addr_t                      status_mapping;
        dma_addr_t                      rx_rcb_mapping;
@@ -2795,6 +2832,85 @@ struct tg3_napi {
        unsigned int                    irq_vec;
 };
 
+enum TG3_FLAGS {
+       TG3_FLAG_TAGGED_STATUS = 0,
+       TG3_FLAG_TXD_MBOX_HWBUG,
+       TG3_FLAG_USE_LINKCHG_REG,
+       TG3_FLAG_ERROR_PROCESSED,
+       TG3_FLAG_ENABLE_ASF,
+       TG3_FLAG_ASPM_WORKAROUND,
+       TG3_FLAG_POLL_SERDES,
+       TG3_FLAG_MBOX_WRITE_REORDER,
+       TG3_FLAG_PCIX_TARGET_HWBUG,
+       TG3_FLAG_WOL_SPEED_100MB,
+       TG3_FLAG_WOL_ENABLE,
+       TG3_FLAG_EEPROM_WRITE_PROT,
+       TG3_FLAG_NVRAM,
+       TG3_FLAG_NVRAM_BUFFERED,
+       TG3_FLAG_SUPPORT_MSI,
+       TG3_FLAG_SUPPORT_MSIX,
+       TG3_FLAG_PCIX_MODE,
+       TG3_FLAG_PCI_HIGH_SPEED,
+       TG3_FLAG_PCI_32BIT,
+       TG3_FLAG_SRAM_USE_CONFIG,
+       TG3_FLAG_TX_RECOVERY_PENDING,
+       TG3_FLAG_WOL_CAP,
+       TG3_FLAG_JUMBO_RING_ENABLE,
+       TG3_FLAG_PAUSE_AUTONEG,
+       TG3_FLAG_CPMU_PRESENT,
+       TG3_FLAG_40BIT_DMA_BUG,
+       TG3_FLAG_BROKEN_CHECKSUMS,
+       TG3_FLAG_JUMBO_CAPABLE,
+       TG3_FLAG_CHIP_RESETTING,
+       TG3_FLAG_INIT_COMPLETE,
+       TG3_FLAG_RESTART_TIMER,
+       TG3_FLAG_TSO_BUG,
+       TG3_FLAG_IS_5788,
+       TG3_FLAG_MAX_RXPEND_64,
+       TG3_FLAG_TSO_CAPABLE,
+       TG3_FLAG_PCI_EXPRESS, /* BCM5785 + pci_is_pcie() */
+       TG3_FLAG_ASF_NEW_HANDSHAKE,
+       TG3_FLAG_HW_AUTONEG,
+       TG3_FLAG_IS_NIC,
+       TG3_FLAG_FLASH,
+       TG3_FLAG_HW_TSO_1,
+       TG3_FLAG_5705_PLUS,
+       TG3_FLAG_5750_PLUS,
+       TG3_FLAG_HW_TSO_3,
+       TG3_FLAG_USING_MSI,
+       TG3_FLAG_USING_MSIX,
+       TG3_FLAG_ICH_WORKAROUND,
+       TG3_FLAG_5780_CLASS,
+       TG3_FLAG_HW_TSO_2,
+       TG3_FLAG_1SHOT_MSI,
+       TG3_FLAG_NO_FWARE_REPORTED,
+       TG3_FLAG_NO_NVRAM_ADDR_TRANS,
+       TG3_FLAG_ENABLE_APE,
+       TG3_FLAG_PROTECTED_NVRAM,
+       TG3_FLAG_5701_DMA_BUG,
+       TG3_FLAG_USE_PHYLIB,
+       TG3_FLAG_MDIOBUS_INITED,
+       TG3_FLAG_LRG_PROD_RING_CAP,
+       TG3_FLAG_RGMII_INBAND_DISABLE,
+       TG3_FLAG_RGMII_EXT_IBND_RX_EN,
+       TG3_FLAG_RGMII_EXT_IBND_TX_EN,
+       TG3_FLAG_CLKREQ_BUG,
+       TG3_FLAG_5755_PLUS,
+       TG3_FLAG_NO_NVRAM,
+       TG3_FLAG_ENABLE_RSS,
+       TG3_FLAG_ENABLE_TSS,
+       TG3_FLAG_SHORT_DMA_BUG,
+       TG3_FLAG_USE_JUMBO_BDFLAG,
+       TG3_FLAG_L1PLLPD_EN,
+       TG3_FLAG_57765_PLUS,
+       TG3_FLAG_APE_HAS_NCSI,
+       TG3_FLAG_5717_PLUS,
+       TG3_FLAG_4K_FIFO_LIMIT,
+
+       /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
+       TG3_FLAG_NUMBER_OF_FLAGS,       /* Last entry in enum TG3_FLAGS */
+};
+
 struct tg3 {
        /* begin "general, frequently-used members" cacheline section */
 
@@ -2818,7 +2934,7 @@ struct tg3 {
        /* SMP locking strategy:
         *
         * lock: Held during reset, PHY access, timer, and when
-        *       updating tg3_flags and tg3_flags2.
+        *       updating tg3_flags.
         *
         * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
         *                netif_tx_lock when it needs to call
@@ -2875,96 +2991,13 @@ struct tg3 {
        struct tg3_ethtool_stats        estats;
        struct tg3_ethtool_stats        estats_prev;
 
+       DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS);
+
        union {
        unsigned long                   phy_crc_errors;
        unsigned long                   last_event_jiffies;
        };
 
-       u32                             tg3_flags;
-#define TG3_FLAG_TAGGED_STATUS         0x00000001
-#define TG3_FLAG_TXD_MBOX_HWBUG                0x00000002
-#define TG3_FLAG_RX_CHECKSUMS          0x00000004
-#define TG3_FLAG_USE_LINKCHG_REG       0x00000008
-#define TG3_FLAG_ENABLE_ASF            0x00000020
-#define TG3_FLAG_ASPM_WORKAROUND       0x00000040
-#define TG3_FLAG_POLL_SERDES           0x00000080
-#define TG3_FLAG_MBOX_WRITE_REORDER    0x00000100
-#define TG3_FLAG_PCIX_TARGET_HWBUG     0x00000200
-#define TG3_FLAG_WOL_SPEED_100MB       0x00000400
-#define TG3_FLAG_WOL_ENABLE            0x00000800
-#define TG3_FLAG_EEPROM_WRITE_PROT     0x00001000
-#define TG3_FLAG_NVRAM                 0x00002000
-#define TG3_FLAG_NVRAM_BUFFERED                0x00004000
-#define TG3_FLAG_SUPPORT_MSI           0x00008000
-#define TG3_FLAG_SUPPORT_MSIX          0x00010000
-#define TG3_FLAG_SUPPORT_MSI_OR_MSIX   (TG3_FLAG_SUPPORT_MSI | \
-                                        TG3_FLAG_SUPPORT_MSIX)
-#define TG3_FLAG_PCIX_MODE             0x00020000
-#define TG3_FLAG_PCI_HIGH_SPEED                0x00040000
-#define TG3_FLAG_PCI_32BIT             0x00080000
-#define TG3_FLAG_SRAM_USE_CONFIG       0x00100000
-#define TG3_FLAG_TX_RECOVERY_PENDING   0x00200000
-#define TG3_FLAG_WOL_CAP               0x00400000
-#define TG3_FLAG_JUMBO_RING_ENABLE     0x00800000
-#define TG3_FLAG_PAUSE_AUTONEG         0x02000000
-#define TG3_FLAG_CPMU_PRESENT          0x04000000
-#define TG3_FLAG_40BIT_DMA_BUG         0x08000000
-#define TG3_FLAG_BROKEN_CHECKSUMS      0x10000000
-#define TG3_FLAG_JUMBO_CAPABLE         0x20000000
-#define TG3_FLAG_CHIP_RESETTING                0x40000000
-#define TG3_FLAG_INIT_COMPLETE         0x80000000
-       u32                             tg3_flags2;
-#define TG3_FLG2_RESTART_TIMER         0x00000001
-#define TG3_FLG2_TSO_BUG               0x00000002
-#define TG3_FLG2_IS_5788               0x00000008
-#define TG3_FLG2_MAX_RXPEND_64         0x00000010
-#define TG3_FLG2_TSO_CAPABLE           0x00000020
-#define TG3_FLG2_PCI_EXPRESS           0x00000200
-#define TG3_FLG2_ASF_NEW_HANDSHAKE     0x00000400
-#define TG3_FLG2_HW_AUTONEG            0x00000800
-#define TG3_FLG2_IS_NIC                        0x00001000
-#define TG3_FLG2_FLASH                 0x00008000
-#define TG3_FLG2_HW_TSO_1              0x00010000
-#define TG3_FLG2_5705_PLUS             0x00040000
-#define TG3_FLG2_5750_PLUS             0x00080000
-#define TG3_FLG2_HW_TSO_3              0x00100000
-#define TG3_FLG2_USING_MSI             0x00200000
-#define TG3_FLG2_USING_MSIX            0x00400000
-#define TG3_FLG2_USING_MSI_OR_MSIX     (TG3_FLG2_USING_MSI | \
-                                       TG3_FLG2_USING_MSIX)
-#define TG3_FLG2_ICH_WORKAROUND                0x02000000
-#define TG3_FLG2_5780_CLASS            0x04000000
-#define TG3_FLG2_HW_TSO_2              0x08000000
-#define TG3_FLG2_HW_TSO                        (TG3_FLG2_HW_TSO_1 | \
-                                        TG3_FLG2_HW_TSO_2 | \
-                                        TG3_FLG2_HW_TSO_3)
-#define TG3_FLG2_1SHOT_MSI             0x10000000
-#define TG3_FLG2_NO_FWARE_REPORTED     0x40000000
-       u32                             tg3_flags3;
-#define TG3_FLG3_NO_NVRAM_ADDR_TRANS   0x00000001
-#define TG3_FLG3_ENABLE_APE            0x00000002
-#define TG3_FLG3_PROTECTED_NVRAM       0x00000004
-#define TG3_FLG3_5701_DMA_BUG          0x00000008
-#define TG3_FLG3_USE_PHYLIB            0x00000010
-#define TG3_FLG3_MDIOBUS_INITED                0x00000020
-#define TG3_FLG3_LRG_PROD_RING_CAP     0x00000080
-#define TG3_FLG3_RGMII_INBAND_DISABLE  0x00000100
-#define TG3_FLG3_RGMII_EXT_IBND_RX_EN  0x00000200
-#define TG3_FLG3_RGMII_EXT_IBND_TX_EN  0x00000400
-#define TG3_FLG3_CLKREQ_BUG            0x00000800
-#define TG3_FLG3_5755_PLUS             0x00002000
-#define TG3_FLG3_NO_NVRAM              0x00004000
-#define TG3_FLG3_ENABLE_RSS            0x00020000
-#define TG3_FLG3_ENABLE_TSS            0x00040000
-#define TG3_FLG3_4G_DMA_BNDRY_BUG      0x00080000
-#define TG3_FLG3_40BIT_DMA_LIMIT_BUG   0x00100000
-#define TG3_FLG3_SHORT_DMA_BUG         0x00200000
-#define TG3_FLG3_USE_JUMBO_BDFLAG      0x00400000
-#define TG3_FLG3_L1PLLPD_EN            0x00800000
-#define TG3_FLG3_57765_PLUS            0x01000000
-#define TG3_FLG3_APE_HAS_NCSI          0x02000000
-#define TG3_FLG3_5717_PLUS             0x04000000
-
        struct timer_list               timer;
        u16                             timer_counter;
        u16                             timer_multiplier;
@@ -2999,12 +3032,10 @@ struct tg3 {
        u8                              pci_cacheline_sz;
        u8                              pci_lat_timer;
 
+       int                             pci_fn;
        int                             pm_cap;
        int                             msi_cap;
-       union {
        int                             pcix_cap;
-       int                             pcie_cap;
-       };
        int                             pcie_readrq;
 
        struct mii_bus                  *mdio_bus;