drivers: wireless: bcm4329: set MMC_PM_KEEP_POWER on suspend
[linux-2.6.git] / drivers / net / tg3.h
index ce010cd..2ea456d 100644 (file)
 #define   CHIPREV_5750_BX               0x41
 #define   CHIPREV_5784_AX               0x57840
 #define   CHIPREV_5761_AX               0x57610
+#define   CHIPREV_57765_AX              0x577650
 #define  GET_METAL_REV(CHIP_REV_ID)    ((CHIP_REV_ID) & 0xff)
 #define   METAL_REV_A0                  0x00
 #define   METAL_REV_A1                  0x01
 #define  RCVLSC_STATUS_ERROR_ATTN       0x00000004
 /* 0x3408 --> 0x3600 unused */
 
+#define TG3_CPMU_DRV_STATUS            0x0000344c
+
 /* CPMU registers */
 #define TG3_CPMU_CTRL                  0x00003600
 #define  CPMU_CTRL_LINK_IDLE_MODE       0x00000200
 #define  TG3_CPMU_EEEMD_EEE_ENABLE      0x00100000
 #define TG3_CPMU_EEE_DBTMR1            0x000036b4
 #define  TG3_CPMU_DBTMR1_PCIEXIT_2047US         0x07ff0000
-#define  TG3_CPMU_DBTMR1_LNKIDLE_2047US         0x000070ff
+#define  TG3_CPMU_DBTMR1_LNKIDLE_2047US         0x000007ff
 #define TG3_CPMU_EEE_DBTMR2            0x000036b8
 #define  TG3_CPMU_DBTMR2_APE_TX_2047US  0x07ff0000
-#define  TG3_CPMU_DBTMR2_TXIDXEQ_2047US         0x000070ff
+#define  TG3_CPMU_DBTMR2_TXIDXEQ_2047US         0x000007ff
 #define TG3_CPMU_EEE_LNKIDL_CTRL       0x000036bc
 #define  TG3_CPMU_EEE_LNKIDL_PCIE_NL0   0x01000000
 #define  TG3_CPMU_EEE_LNKIDL_UART_IDL   0x00000004
 
 /* Alternate PCIE definitions */
 #define TG3_PCIE_TLDLPL_PORT           0x00007c00
+#define TG3_PCIE_DL_LO_FTSMAX          0x0000000c
+#define TG3_PCIE_DL_LO_FTSMAX_MSK      0x000000ff
+#define TG3_PCIE_DL_LO_FTSMAX_VAL      0x0000002c
 #define TG3_PCIE_PL_LO_PHYCTL1          0x00000004
 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN        0x00001000
 #define TG3_PCIE_PL_LO_PHYCTL5          0x00000014
 
 
 /*** Tigon3 specific PHY MII registers. ***/
-#define  TG3_BMCR_SPEED1000            0x0040
-
-#define MII_TG3_CTRL                   0x09 /* 1000-baseT control register */
-#define  MII_TG3_CTRL_ADV_1000_HALF    0x0100
-#define  MII_TG3_CTRL_ADV_1000_FULL    0x0200
-#define  MII_TG3_CTRL_AS_MASTER                0x0800
-#define  MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
-
 #define MII_TG3_MMD_CTRL               0x0d /* MMD Access Control register */
 #define MII_TG3_MMD_CTRL_DATA_NOINC    0x4000
 #define MII_TG3_MMD_ADDRESS            0x0e /* MMD Address Data register */
 #define  MII_TG3_DSP_TAP26_OPCSINPT    0x0004
 #define MII_TG3_DSP_AADJ1CH0           0x001f
 #define MII_TG3_DSP_CH34TP2            0x4022
-#define MII_TG3_DSP_CH34TP2_HIBW01     0x0010
+#define MII_TG3_DSP_CH34TP2_HIBW01     0x01ff
 #define MII_TG3_DSP_AADJ1CH3           0x601f
 #define  MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
 #define MII_TG3_DSP_EXP1_INT_STAT      0x0f01
 
 
 /* APE registers.  Accessible through BAR1 */
+#define TG3_APE_GPIO_MSG               0x0008
+#define TG3_APE_GPIO_MSG_SHIFT         4
 #define TG3_APE_EVENT                  0x000c
 #define  APE_EVENT_1                    0x00000001
 #define TG3_APE_LOCK_REQ               0x002c
 /* APE convenience enumerations. */
 #define TG3_APE_LOCK_GRC                1
 #define TG3_APE_LOCK_MEM                4
+#define TG3_APE_LOCK_GPIO               7
 
 #define TG3_EEPROM_SB_F1R2_MBA_OFF     0x10
 
@@ -2616,7 +2617,6 @@ struct tg3_hw_stats {
        tg3_stat64_t                    dma_write_prioq_full;
        tg3_stat64_t                    rxbds_empty;
        tg3_stat64_t                    rx_discards;
-       tg3_stat64_t                    mbuf_lwm_thresh_hit;
        tg3_stat64_t                    rx_errors;
        tg3_stat64_t                    rx_threshold_hit;
 
@@ -2635,7 +2635,12 @@ struct tg3_hw_stats {
        tg3_stat64_t                    nic_avoided_irqs;
        tg3_stat64_t                    nic_tx_threshold_hit;
 
-       u8                              __reserved4[0xb00-0x9c0];
+       /* NOT a part of the hardware statistics block format.
+        * These stats are here as storage for tg3_periodic_fetch_stats().
+        */
+       tg3_stat64_t                    mbuf_lwm_thresh_hit;
+
+       u8                              __reserved4[0xb00-0x9c8];
 };
 
 /* 'mapping' is superfluous as the chip does not write into
@@ -2647,6 +2652,12 @@ struct ring_info {
        DEFINE_DMA_UNMAP_ADDR(mapping);
 };
 
+struct tg3_tx_ring_info {
+       struct sk_buff                  *skb;
+       DEFINE_DMA_UNMAP_ADDR(mapping);
+       bool                            fragmented;
+};
+
 struct tg3_link_config {
        /* Describes what we're trying to get. */
        u32                             advertising;
@@ -2767,6 +2778,8 @@ struct tg3_ethtool_stats {
        u64             nic_irqs;
        u64             nic_avoided_irqs;
        u64             nic_tx_threshold_hit;
+
+       u64             mbuf_lwm_thresh_hit;
 };
 
 struct tg3_rx_prodring_set {
@@ -2790,6 +2803,7 @@ struct tg3_napi {
        struct tg3                      *tp;
        struct tg3_hw_status            *hw_status;
 
+       u32                             chk_msi_cnt;
        u32                             last_tag;
        u32                             last_irq_tag;
        u32                             int_mbox;
@@ -2797,6 +2811,7 @@ struct tg3_napi {
 
        u32                             consmbox ____cacheline_aligned;
        u32                             rx_rcb_ptr;
+       u32                             last_rx_cons;
        u16                             *rx_rcb_prod_idx;
        struct tg3_rx_prodring_set      prodring;
        struct tg3_rx_buffer_desc       *rx_rcb;
@@ -2804,9 +2819,10 @@ struct tg3_napi {
        u32                             tx_prod ____cacheline_aligned;
        u32                             tx_cons;
        u32                             tx_pending;
+       u32                             last_tx_cons;
        u32                             prodmbox;
        struct tg3_tx_buffer_desc       *tx_ring;
-       struct ring_info                *tx_buffers;
+       struct tg3_tx_ring_info         *tx_buffers;
 
        dma_addr_t                      status_mapping;
        dma_addr_t                      rx_rcb_mapping;
@@ -2852,7 +2868,7 @@ enum TG3_FLAGS {
        TG3_FLAG_IS_5788,
        TG3_FLAG_MAX_RXPEND_64,
        TG3_FLAG_TSO_CAPABLE,
-       TG3_FLAG_PCI_EXPRESS,
+       TG3_FLAG_PCI_EXPRESS, /* BCM5785 + pci_is_pcie() */
        TG3_FLAG_ASF_NEW_HANDSHAKE,
        TG3_FLAG_HW_AUTONEG,
        TG3_FLAG_IS_NIC,
@@ -2883,14 +2899,13 @@ enum TG3_FLAGS {
        TG3_FLAG_NO_NVRAM,
        TG3_FLAG_ENABLE_RSS,
        TG3_FLAG_ENABLE_TSS,
-       TG3_FLAG_4G_DMA_BNDRY_BUG,
-       TG3_FLAG_40BIT_DMA_LIMIT_BUG,
        TG3_FLAG_SHORT_DMA_BUG,
        TG3_FLAG_USE_JUMBO_BDFLAG,
        TG3_FLAG_L1PLLPD_EN,
        TG3_FLAG_57765_PLUS,
        TG3_FLAG_APE_HAS_NCSI,
        TG3_FLAG_5717_PLUS,
+       TG3_FLAG_4K_FIFO_LIMIT,
 
        /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
        TG3_FLAG_NUMBER_OF_FLAGS,       /* Last entry in enum TG3_FLAGS */
@@ -3017,12 +3032,10 @@ struct tg3 {
        u8                              pci_cacheline_sz;
        u8                              pci_lat_timer;
 
+       int                             pci_fn;
        int                             pm_cap;
        int                             msi_cap;
-       union {
        int                             pcix_cap;
-       int                             pcie_cap;
-       };
        int                             pcie_readrq;
 
        struct mii_bus                  *mdio_bus;