drivers: wireless: bcm4329: set MMC_PM_KEEP_POWER on suspend
[linux-2.6.git] / drivers / net / tg3.h
index a8fb53a..2ea456d 100644 (file)
@@ -4,7 +4,7 @@
  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
  * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
  * Copyright (C) 2004 Sun Microsystems Inc.
- * Copyright (C) 2007-2010 Broadcom Corporation.
+ * Copyright (C) 2007-2011 Broadcom Corporation.
  */
 
 #ifndef _T3_H
 #define TG3_BDINFO_NIC_ADDR            0xcUL /* 32-bit */
 #define TG3_BDINFO_SIZE                        0x10UL
 
-#define RX_COPY_THRESHOLD              256
-
-#define TG3_RX_INTERNAL_RING_SZ_5906   32
-
-#define RX_STD_MAX_SIZE                        1536
-#define RX_STD_MAX_SIZE_5705           512
-#define RX_JUMBO_MAX_SIZE              0xdeadbeef /* XXX */
+#define TG3_RX_STD_MAX_SIZE_5700       512
+#define TG3_RX_STD_MAX_SIZE_5717       2048
+#define TG3_RX_JMB_MAX_SIZE_5700       256
+#define TG3_RX_JMB_MAX_SIZE_5717       1024
+#define TG3_RX_RET_MAX_SIZE_5700       1024
+#define TG3_RX_RET_MAX_SIZE_5705       512
+#define TG3_RX_RET_MAX_SIZE_5717       4096
 
 /* First 256 bytes are a mirror of PCI config space. */
 #define TG3PCI_VENDOR                  0x00000000
 #define  TG3PCI_DEVICE_TIGON3_5785_F    0x16a0 /* 10/100 only */
 #define  TG3PCI_DEVICE_TIGON3_5717      0x1655
 #define  TG3PCI_DEVICE_TIGON3_5718      0x1656
-#define  TG3PCI_DEVICE_TIGON3_5724      0x165c
 #define  TG3PCI_DEVICE_TIGON3_57781     0x16b1
 #define  TG3PCI_DEVICE_TIGON3_57785     0x16b5
 #define  TG3PCI_DEVICE_TIGON3_57761     0x16b0
 #define  TG3PCI_DEVICE_TIGON3_57765     0x16b4
 #define  TG3PCI_DEVICE_TIGON3_57791     0x16b2
 #define  TG3PCI_DEVICE_TIGON3_57795     0x16b6
-/* 0x04 --> 0x64 unused */
+#define  TG3PCI_DEVICE_TIGON3_5719      0x1657
+#define  TG3PCI_DEVICE_TIGON3_5720      0x165f
+/* 0x04 --> 0x2c unused */
+#define TG3PCI_SUBVENDOR_ID_BROADCOM           PCI_VENDOR_ID_BROADCOM
+#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6   0x1644
+#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5   0x0001
+#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6   0x0002
+#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9   0x0003
+#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1   0x0005
+#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8   0x0006
+#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7   0x0007
+#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10  0x0008
+#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12  0x8008
+#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1  0x0009
+#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2  0x8009
+#define TG3PCI_SUBVENDOR_ID_3COM               PCI_VENDOR_ID_3COM
+#define TG3PCI_SUBDEVICE_ID_3COM_3C996T                0x1000
+#define TG3PCI_SUBDEVICE_ID_3COM_3C996BT       0x1006
+#define TG3PCI_SUBDEVICE_ID_3COM_3C996SX       0x1004
+#define TG3PCI_SUBDEVICE_ID_3COM_3C1000T       0x1007
+#define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01     0x1008
+#define TG3PCI_SUBVENDOR_ID_DELL               PCI_VENDOR_ID_DELL
+#define TG3PCI_SUBDEVICE_ID_DELL_VIPER         0x00d1
+#define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR                0x0106
+#define TG3PCI_SUBDEVICE_ID_DELL_MERLOT                0x0109
+#define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT   0x010a
+#define TG3PCI_SUBVENDOR_ID_COMPAQ             PCI_VENDOR_ID_COMPAQ
+#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE     0x007c
+#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2   0x009a
+#define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING  0x007d
+#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780      0x0085
+#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2    0x0099
+#define TG3PCI_SUBVENDOR_ID_IBM                        PCI_VENDOR_ID_IBM
+#define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2       0x0281
+/* 0x30 --> 0x64 unused */
 #define TG3PCI_MSI_DATA                        0x00000064
 /* 0x66 --> 0x68 unused */
 #define TG3PCI_MISC_HOST_CTRL          0x00000068
 #define  CHIPREV_ID_57780_A1            0x57780001
 #define  CHIPREV_ID_5717_A0             0x05717000
 #define  CHIPREV_ID_57765_A0            0x57785000
+#define  CHIPREV_ID_5719_A0             0x05719000
+#define  CHIPREV_ID_5720_A0             0x05720000
 #define  GET_ASIC_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700                         0x07
 #define   ASIC_REV_5701                         0x00
 #define   ASIC_REV_57780                0x57780
 #define   ASIC_REV_5717                         0x5717
 #define   ASIC_REV_57765                0x57785
+#define   ASIC_REV_5719                         0x5719
+#define   ASIC_REV_5720                         0x5720
 #define  GET_CHIP_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX               0x70
 #define   CHIPREV_5700_BX               0x71
 #define   CHIPREV_5750_BX               0x41
 #define   CHIPREV_5784_AX               0x57840
 #define   CHIPREV_5761_AX               0x57610
+#define   CHIPREV_57765_AX              0x577650
 #define  GET_METAL_REV(CHIP_REV_ID)    ((CHIP_REV_ID) & 0xff)
 #define   METAL_REV_A0                  0x00
 #define   METAL_REV_A1                  0x01
 #define   METAL_REV_B2                  0x02
 #define TG3PCI_DMA_RW_CTRL             0x0000006c
 #define  DMA_RWCTRL_DIS_CACHE_ALIGNMENT  0x00000001
+#define  DMA_RWCTRL_TAGGED_STAT_WA      0x00000080
+#define  DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380
 #define  DMA_RWCTRL_READ_BNDRY_MASK     0x00000700
 #define  DMA_RWCTRL_READ_BNDRY_DISAB    0x00000000
 #define  DMA_RWCTRL_READ_BNDRY_16       0x00000100
 #define  PCISTATE_RETRY_SAME_DMA        0x00002000
 #define  PCISTATE_ALLOW_APE_CTLSPC_WR   0x00010000
 #define  PCISTATE_ALLOW_APE_SHMEM_WR    0x00020000
+#define  PCISTATE_ALLOW_APE_PSPACE_WR   0x00040000
 #define TG3PCI_CLOCK_CTRL              0x00000074
 #define  CLOCK_CTRL_CORECLK_DISABLE     0x00000200
 #define  CLOCK_CTRL_RXCLK_DISABLE       0x00000400
 /* 0x94 --> 0x98 unused */
 #define TG3PCI_STD_RING_PROD_IDX       0x00000098 /* 64-bit */
 #define TG3PCI_RCV_RET_RING_CON_IDX    0x000000a0 /* 64-bit */
-/* 0xa0 --> 0xb8 unused */
+/* 0xa8 --> 0xb8 unused */
 #define TG3PCI_DUAL_MAC_CTRL           0x000000b8
 #define  DUAL_MAC_CTRL_CH_MASK          0x00000003
 #define  DUAL_MAC_CTRL_ID               0x00000004
 #define  TX_MODE_FLOW_CTRL_ENABLE       0x00000010
 #define  TX_MODE_BIG_BCKOFF_ENABLE      0x00000020
 #define  TX_MODE_LONG_PAUSE_ENABLE      0x00000040
+#define  TX_MODE_MBUF_LOCKUP_FIX        0x00000100
+#define  TX_MODE_JMB_FRM_LEN            0x00400000
+#define  TX_MODE_CNT_DN_MODE            0x00800000
 #define MAC_TX_STATUS                  0x00000460
 #define  TX_STATUS_XOFFED               0x00000001
 #define  TX_STATUS_SENT_XOFF            0x00000002
 #define  TX_LENGTHS_IPG_SHIFT           8
 #define  TX_LENGTHS_IPG_CRS_MASK        0x00003000
 #define  TX_LENGTHS_IPG_CRS_SHIFT       12
+#define  TX_LENGTHS_JMB_FRM_LEN_MSK     0x00ff0000
+#define  TX_LENGTHS_CNT_DWN_VAL_MSK     0xff000000
 #define MAC_RX_MODE                    0x00000468
 #define  RX_MODE_RESET                  0x00000001
 #define  RX_MODE_ENABLE                         0x00000002
 #define  RCVDBDI_MODE_JUMBOBD_NEEDED    0x00000004
 #define  RCVDBDI_MODE_FRM_TOO_BIG       0x00000008
 #define  RCVDBDI_MODE_INV_RING_SZ       0x00000010
+#define  RCVDBDI_MODE_LRG_RING_SZ       0x00010000
 #define RCVDBDI_STATUS                 0x00002404
 #define  RCVDBDI_STATUS_JUMBOBD_NEEDED  0x00000004
 #define  RCVDBDI_STATUS_FRM_TOO_BIG     0x00000008
 #define  RCVLSC_STATUS_ERROR_ATTN       0x00000004
 /* 0x3408 --> 0x3600 unused */
 
+#define TG3_CPMU_DRV_STATUS            0x0000344c
+
 /* CPMU registers */
 #define TG3_CPMU_CTRL                  0x00003600
 #define  CPMU_CTRL_LINK_IDLE_MODE       0x00000200
 #define TG3_CPMU_HST_ACC               0x0000361c
 #define  CPMU_HST_ACC_MACCLK_MASK       0x001f0000
 #define  CPMU_HST_ACC_MACCLK_6_25       0x00130000
-/* 0x3620 --> 0x362c unused */
+/* 0x3620 --> 0x3630 unused */
+
+#define TG3_CPMU_CLCK_ORIDE            0x00003624
+#define  CPMU_CLCK_ORIDE_MAC_ORIDE_EN   0x80000000
 
-#define TG3_CPMU_STATUS                        0x0000362c
-#define  TG3_CPMU_STATUS_PCIE_FUNC      0x20000000
 #define TG3_CPMU_CLCK_STAT             0x00003630
 #define  CPMU_CLCK_STAT_MAC_CLCK_MASK   0x001f0000
 #define  CPMU_CLCK_STAT_MAC_CLCK_62_5   0x00000000
 #define  CPMU_MUTEX_GNT_DRIVER          0x00001000
 #define TG3_CPMU_PHY_STRAP             0x00003664
 #define TG3_CPMU_PHY_STRAP_IS_SERDES    0x00000020
-/* 0x3664 --> 0x3800 unused */
+/* 0x3664 --> 0x36b0 unused */
+
+#define TG3_CPMU_EEE_MODE              0x000036b0
+#define  TG3_CPMU_EEEMD_APE_TX_DET_EN   0x00000004
+#define  TG3_CPMU_EEEMD_ERLY_L1_XIT_DET         0x00000008
+#define  TG3_CPMU_EEEMD_SND_IDX_DET_EN  0x00000040
+#define  TG3_CPMU_EEEMD_LPI_ENABLE      0x00000080
+#define  TG3_CPMU_EEEMD_LPI_IN_TX       0x00000100
+#define  TG3_CPMU_EEEMD_LPI_IN_RX       0x00000200
+#define  TG3_CPMU_EEEMD_EEE_ENABLE      0x00100000
+#define TG3_CPMU_EEE_DBTMR1            0x000036b4
+#define  TG3_CPMU_DBTMR1_PCIEXIT_2047US         0x07ff0000
+#define  TG3_CPMU_DBTMR1_LNKIDLE_2047US         0x000007ff
+#define TG3_CPMU_EEE_DBTMR2            0x000036b8
+#define  TG3_CPMU_DBTMR2_APE_TX_2047US  0x07ff0000
+#define  TG3_CPMU_DBTMR2_TXIDXEQ_2047US         0x000007ff
+#define TG3_CPMU_EEE_LNKIDL_CTRL       0x000036bc
+#define  TG3_CPMU_EEE_LNKIDL_PCIE_NL0   0x01000000
+#define  TG3_CPMU_EEE_LNKIDL_UART_IDL   0x00000004
+/* 0x36c0 --> 0x36d0 unused */
+
+#define TG3_CPMU_EEE_CTRL              0x000036d0
+#define TG3_CPMU_EEE_CTRL_EXIT_16_5_US  0x0000019d
+#define TG3_CPMU_EEE_CTRL_EXIT_36_US    0x00000384
+#define TG3_CPMU_EEE_CTRL_EXIT_20_1_US  0x000001f8
+/* 0x36d4 --> 0x3800 unused */
 
 /* Mbuf cluster free registers */
 #define MBFREE_MODE                    0x00003800
 #define HOSTCC_STATS_BLK_NIC_ADDR      0x00003c40
 #define HOSTCC_STATUS_BLK_NIC_ADDR     0x00003c44
 #define HOSTCC_FLOW_ATTN               0x00003c48
+#define HOSTCC_FLOW_ATTN_MBUF_LWM       0x00000040
 /* 0x3c4c --> 0x3c50 unused */
 #define HOSTCC_JUMBO_CON_IDX           0x00003c50
 #define HOSTCC_STD_CON_IDX             0x00003c54
 #define  BUFMGR_MODE_ATTN_ENABLE        0x00000004
 #define  BUFMGR_MODE_BM_TEST            0x00000008
 #define  BUFMGR_MODE_MBLOW_ATTN_ENAB    0x00000010
+#define  BUFMGR_MODE_NO_TX_UNDERRUN     0x80000000
 #define BUFMGR_STATUS                  0x00004404
 #define  BUFMGR_STATUS_ERROR            0x00000004
 #define  BUFMGR_STATUS_MBLOW            0x00000010
 #define  RDMAC_MODE_MULT_DMA_RD_DIS     0x01000000
 #define  RDMAC_MODE_IPV4_LSO_EN                 0x08000000
 #define  RDMAC_MODE_IPV6_LSO_EN                 0x10000000
+#define  RDMAC_MODE_H2BNC_VLAN_DET      0x20000000
 #define RDMAC_STATUS                   0x00004804
 #define  RDMAC_STATUS_TGTABORT          0x00000004
 #define  RDMAC_STATUS_MSTABORT          0x00000008
 #define  RDMAC_STATUS_FIFOURUN          0x00000080
 #define  RDMAC_STATUS_FIFOOREAD                 0x00000100
 #define  RDMAC_STATUS_LNGREAD           0x00000200
-/* 0x4808 --> 0x4c00 unused */
+/* 0x4808 --> 0x4900 unused */
+
+#define TG3_RDMA_RSRVCTRL_REG          0x00004900
+#define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX         0x00000004
+#define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K         0x00000c00
+#define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK         0x00000ff0
+#define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K         0x000c0000
+#define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK         0x000ff000
+#define TG3_RDMA_RSRVCTRL_TXMRGN_320B   0x28000000
+#define TG3_RDMA_RSRVCTRL_TXMRGN_MASK   0xffe00000
+/* 0x4904 --> 0x4910 unused */
+
+#define TG3_LSO_RD_DMA_CRPTEN_CTRL     0x00004910
+#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K   0x00030000
+#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K  0x000c0000
+/* 0x4914 --> 0x4c00 unused */
 
 /* Write DMA control registers */
 #define WDMAC_MODE                     0x00004c00
 #define  MSGINT_MODE_ONE_SHOT_DISABLE   0x00000020
 #define  MSGINT_MODE_MULTIVEC_EN        0x00000080
 #define MSGINT_STATUS                  0x00006004
+#define  MSGINT_STATUS_MSI_REQ          0x00000001
 #define MSGINT_FIFO                    0x00006008
 /* 0x600c --> 0x6400 unused */
 
 #define  GRC_MODE_WSWAP_NONFRM_DATA    0x00000004
 #define  GRC_MODE_BSWAP_DATA           0x00000010
 #define  GRC_MODE_WSWAP_DATA           0x00000020
+#define  GRC_MODE_BYTE_SWAP_B2HRX_DATA 0x00000040
+#define  GRC_MODE_WORD_SWAP_B2HRX_DATA 0x00000080
 #define  GRC_MODE_SPLITHDR             0x00000100
 #define  GRC_MODE_NOFRM_CRACKING       0x00000200
 #define  GRC_MODE_INCL_CRC             0x00000400
 #define  GRC_MODE_NOIRQ_ON_SENDS       0x00002000
 #define  GRC_MODE_NOIRQ_ON_RCV         0x00004000
 #define  GRC_MODE_FORCE_PCI32BIT       0x00008000
+#define  GRC_MODE_B2HRX_ENABLE         0x00008000
 #define  GRC_MODE_HOST_STACKUP         0x00010000
 #define  GRC_MODE_HOST_SENDBDS         0x00020000
+#define  GRC_MODE_HTX2B_ENABLE         0x00040000
 #define  GRC_MODE_NO_TX_PHDR_CSUM      0x00100000
 #define  GRC_MODE_NVRAM_WR_ENABLE      0x00200000
 #define  GRC_MODE_PCIE_TL_SEL          0x00000000
 #define  FLASH_5717VENDOR_ATMEL_45USPT  0x03400000
 #define  FLASH_5717VENDOR_ST_25USPT     0x03400002
 #define  FLASH_5717VENDOR_ST_45USPT     0x03400001
+#define  FLASH_5720_EEPROM_HD           0x00000001
+#define  FLASH_5720_EEPROM_LD           0x00000003
+#define  FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000
+#define  FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002
+#define  FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001
+#define  FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003
+#define  FLASH_5720VENDOR_M_ST_M25PE10  0x02000000
+#define  FLASH_5720VENDOR_M_ST_M25PE20  0x02000002
+#define  FLASH_5720VENDOR_M_ST_M25PE40  0x02000001
+#define  FLASH_5720VENDOR_M_ST_M25PE80  0x02000003
+#define  FLASH_5720VENDOR_M_ST_M45PE10  0x03000000
+#define  FLASH_5720VENDOR_M_ST_M45PE20  0x03000002
+#define  FLASH_5720VENDOR_M_ST_M45PE40  0x03000001
+#define  FLASH_5720VENDOR_M_ST_M45PE80  0x03000003
+#define  FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000
+#define  FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002
+#define  FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001
+#define  FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000
+#define  FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002
+#define  FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001
+#define  FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003
+#define  FLASH_5720VENDOR_A_ST_M25PE10  0x02800000
+#define  FLASH_5720VENDOR_A_ST_M25PE20  0x02800002
+#define  FLASH_5720VENDOR_A_ST_M25PE40  0x02800001
+#define  FLASH_5720VENDOR_A_ST_M25PE80  0x02800003
+#define  FLASH_5720VENDOR_A_ST_M45PE10  0x02c00000
+#define  FLASH_5720VENDOR_A_ST_M45PE20  0x02c00002
+#define  FLASH_5720VENDOR_A_ST_M45PE40  0x02c00001
+#define  FLASH_5720VENDOR_A_ST_M45PE80  0x02c00003
+#define  FLASH_5720VENDOR_ATMEL_45USPT  0x03c00000
+#define  FLASH_5720VENDOR_ST_25USPT     0x03c00002
+#define  FLASH_5720VENDOR_ST_45USPT     0x03c00001
 #define  NVRAM_CFG1_5752PAGE_SIZE_MASK  0x70000000
 #define  FLASH_5752PAGE_SIZE_256        0x00000000
 #define  FLASH_5752PAGE_SIZE_512        0x10000000
 #define  TG3_PCIE_LNKCTL_L1_PLL_PD_DIS  0x00000080
 /* 0x7d58 --> 0x7e70 unused */
 
+#define TG3_PCIE_PHY_TSTCTL            0x00007e2c
+#define  TG3_PCIE_PHY_TSTCTL_PCIE10     0x00000040
+#define  TG3_PCIE_PHY_TSTCTL_PSCRAM     0x00000020
+
 #define TG3_PCIE_EIDLE_DELAY           0x00007e70
 #define  TG3_PCIE_EIDLE_DELAY_MASK      0x0000001f
 #define  TG3_PCIE_EIDLE_DELAY_13_CLKS   0x0000000c
 
 /* Alternate PCIE definitions */
 #define TG3_PCIE_TLDLPL_PORT           0x00007c00
+#define TG3_PCIE_DL_LO_FTSMAX          0x0000000c
+#define TG3_PCIE_DL_LO_FTSMAX_MSK      0x000000ff
+#define TG3_PCIE_DL_LO_FTSMAX_VAL      0x0000002c
 #define TG3_PCIE_PL_LO_PHYCTL1          0x00000004
 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN        0x00001000
+#define TG3_PCIE_PL_LO_PHYCTL5          0x00000014
+#define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ      0x80000000
+
+#define TG3_REG_BLK_SIZE               0x00008000
 
 /* OTP bit definitions */
 #define TG3_OTP_AGCTGT_MASK            0x000000e0
 #define TG3_EEPROM_SB_REVISION_0       0x00000000
 #define TG3_EEPROM_SB_REVISION_2       0x00020000
 #define TG3_EEPROM_SB_REVISION_3       0x00030000
+#define TG3_EEPROM_SB_REVISION_4       0x00040000
+#define TG3_EEPROM_SB_REVISION_5       0x00050000
+#define TG3_EEPROM_SB_REVISION_6       0x00060000
 #define TG3_EEPROM_MAGIC_HW            0xabcd
 #define TG3_EEPROM_MAGIC_HW_MSK                0xffff
 
 #define TG3_NVM_DIR_END                        0x78
 #define TG3_NVM_DIRENT_SIZE            0xc
 #define TG3_NVM_DIRTYPE_SHIFT          24
+#define TG3_NVM_DIRTYPE_LENMSK         0x003fffff
 #define TG3_NVM_DIRTYPE_ASFINI         1
+#define TG3_NVM_DIRTYPE_EXTVPD         20
 #define TG3_NVM_PTREV_BCVER            0x94
 #define TG3_NVM_BCVER_MAJMSK           0x0000ff00
 #define TG3_NVM_BCVER_MAJSFT           8
 #define TG3_EEPROM_SB_F1R2_EDH_OFF     0x14
 #define TG3_EEPROM_SB_F1R2_MBA_OFF     0x10
 #define TG3_EEPROM_SB_F1R3_EDH_OFF     0x18
+#define TG3_EEPROM_SB_F1R4_EDH_OFF     0x1c
+#define TG3_EEPROM_SB_F1R5_EDH_OFF     0x20
+#define TG3_EEPROM_SB_F1R6_EDH_OFF     0x4c
 #define TG3_EEPROM_SB_EDH_MAJ_MASK     0x00000700
 #define TG3_EEPROM_SB_EDH_MAJ_SHFT     8
 #define TG3_EEPROM_SB_EDH_MIN_MASK     0x000000ff
 
 #define NIC_SRAM_DATA_CFG_4            0x00000d60
 #define  NIC_SRAM_GMII_MODE             0x00000002
-#define  NIC_SRAM_RGMII_STD_IBND_DISABLE 0x00000004
+#define  NIC_SRAM_RGMII_INBAND_DISABLE  0x00000004
 #define  NIC_SRAM_RGMII_EXT_IBND_RX_EN  0x00000008
 #define  NIC_SRAM_RGMII_EXT_IBND_TX_EN  0x00000010
 
 #define  NIC_SRAM_MBUF_POOL_BASE5705   0x00010000
 #define  NIC_SRAM_MBUF_POOL_SIZE5705   0x0000e000
 
+#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700      128
+#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755      64
+#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906      32
 
-/* Currently this is fixed. */
-#define TG3_PHY_PCIE_ADDR              0x00
-#define TG3_PHY_MII_ADDR               0x01
+#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700      64
+#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717      16
 
 
-/*** Tigon3 specific PHY PCIE registers. ***/
-
-#define TG3_PCIEPHY_BLOCK_ADDR         0x1f
-#define  TG3_PCIEPHY_XGXS_BLK1         0x0801
-#define  TG3_PCIEPHY_TXB_BLK           0x0861
-#define  TG3_PCIEPHY_BLOCK_SHIFT       4
-
-/* TG3_PCIEPHY_TXB_BLK */
-#define TG3_PCIEPHY_TX0CTRL1           0x15
-#define  TG3_PCIEPHY_TX0CTRL1_TXOCM    0x0003
-#define  TG3_PCIEPHY_TX0CTRL1_RDCTL    0x0008
-#define  TG3_PCIEPHY_TX0CTRL1_TXCMV    0x0030
-#define  TG3_PCIEPHY_TX0CTRL1_TKSEL    0x0040
-#define  TG3_PCIEPHY_TX0CTRL1_NB_EN    0x0400
-
-/* TG3_PCIEPHY_XGXS_BLK1 */
-#define TG3_PCIEPHY_PWRMGMT4           0x1a
-#define TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN        0x0038
-#define TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN 0x4000
+/* Currently this is fixed. */
+#define TG3_PHY_MII_ADDR               0x01
 
 
 /*** Tigon3 specific PHY MII registers. ***/
-#define  TG3_BMCR_SPEED1000            0x0040
-
-#define MII_TG3_CTRL                   0x09 /* 1000-baseT control register */
-#define  MII_TG3_CTRL_ADV_1000_HALF    0x0100
-#define  MII_TG3_CTRL_ADV_1000_FULL    0x0200
-#define  MII_TG3_CTRL_AS_MASTER                0x0800
-#define  MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
+#define MII_TG3_MMD_CTRL               0x0d /* MMD Access Control register */
+#define MII_TG3_MMD_CTRL_DATA_NOINC    0x4000
+#define MII_TG3_MMD_ADDRESS            0x0e /* MMD Address Data register */
 
 #define MII_TG3_EXT_CTRL               0x10 /* Extended control register */
 #define  MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
 #define MII_TG3_EXT_STAT               0x11 /* Extended status register */
 #define  MII_TG3_EXT_STAT_LPASS                0x0100
 
+#define MII_TG3_RXR_COUNTERS           0x14 /* Local/Remote Receiver Counts */
 #define MII_TG3_DSP_RW_PORT            0x15 /* DSP coefficient read/write port */
-
+#define MII_TG3_DSP_CONTROL            0x16 /* DSP control register */
 #define MII_TG3_DSP_ADDRESS            0x17 /* DSP address register */
 
 #define MII_TG3_DSP_TAP1               0x0001
 #define  MII_TG3_DSP_TAP1_AGCTGT_DFLT  0x0007
+#define MII_TG3_DSP_TAP26              0x001a
+#define  MII_TG3_DSP_TAP26_ALNOKO      0x0001
+#define  MII_TG3_DSP_TAP26_RMRXSTO     0x0002
+#define  MII_TG3_DSP_TAP26_OPCSINPT    0x0004
 #define MII_TG3_DSP_AADJ1CH0           0x001f
+#define MII_TG3_DSP_CH34TP2            0x4022
+#define MII_TG3_DSP_CH34TP2_HIBW01     0x01ff
 #define MII_TG3_DSP_AADJ1CH3           0x601f
 #define  MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
-#define MII_TG3_DSP_EXP8               0x0708
+#define MII_TG3_DSP_EXP1_INT_STAT      0x0f01
+#define MII_TG3_DSP_EXP8               0x0f08
 #define  MII_TG3_DSP_EXP8_REJ2MHz      0x0001
 #define  MII_TG3_DSP_EXP8_AEDW         0x0200
 #define MII_TG3_DSP_EXP75              0x0f75
 #define MII_TG3_DSP_EXP96              0x0f96
 #define MII_TG3_DSP_EXP97              0x0f97
 
-#define MII_TG3_AUX_CTRL               0x18 /* auxilliary control register */
+#define MII_TG3_AUX_CTRL               0x18 /* auxiliary control register */
 
+#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL  0x0000
+#define MII_TG3_AUXCTL_ACTL_TX_6DB     0x0400
+#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA  0x0800
+#define MII_TG3_AUXCTL_ACTL_EXTPKTLEN  0x4000
+
+#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL  0x0002
+#define MII_TG3_AUXCTL_PCTL_WOL_EN     0x0008
 #define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010
 #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE        0x0020
+#define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC        0x0040
 #define MII_TG3_AUXCTL_PCTL_VREG_11V   0x0180
-#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL  0x0002
 
-#define MII_TG3_AUXCTL_MISC_WREN       0x8000
-#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX        0x0200
-#define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000
+#define MII_TG3_AUXCTL_SHDWSEL_MISCTEST        0x0004
+
 #define MII_TG3_AUXCTL_SHDWSEL_MISC    0x0007
+#define MII_TG3_AUXCTL_MISC_WIRESPD_EN 0x0010
+#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX        0x0200
+#define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT        12
+#define MII_TG3_AUXCTL_MISC_WREN       0x8000
 
-#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA  0x0800
-#define MII_TG3_AUXCTL_ACTL_TX_6DB     0x0400
-#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL  0x0000
 
-#define MII_TG3_AUX_STAT               0x19 /* auxilliary status register */
+#define MII_TG3_AUX_STAT               0x19 /* auxiliary status register */
 #define MII_TG3_AUX_STAT_LPASS         0x0004
 #define MII_TG3_AUX_STAT_SPDMASK       0x0700
 #define MII_TG3_AUX_STAT_10HALF                0x0100
 #define MII_TG3_TEST1_TRIM_EN          0x0010
 #define MII_TG3_TEST1_CRC_EN           0x8000
 
+/* Clause 45 expansion registers */
+#define TG3_CL45_D7_EEERES_STAT                0x803e
+#define TG3_CL45_D7_EEERES_STAT_LP_100TX       0x0002
+#define TG3_CL45_D7_EEERES_STAT_LP_1000T       0x0004
+
 
 /* Fast Ethernet Tranceiver definitions */
 #define MII_TG3_FET_PTEST              0x17
+#define  MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000
+#define  MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800
+
 #define MII_TG3_FET_TEST               0x1f
 #define  MII_TG3_FET_SHADOW_EN         0x0080
 
 
 
 /* APE registers.  Accessible through BAR1 */
+#define TG3_APE_GPIO_MSG               0x0008
+#define TG3_APE_GPIO_MSG_SHIFT         4
 #define TG3_APE_EVENT                  0x000c
 #define  APE_EVENT_1                    0x00000001
 #define TG3_APE_LOCK_REQ               0x002c
 /* APE shared memory.  Accessible through BAR1 */
 #define TG3_APE_FW_STATUS              0x400c
 #define  APE_FW_STATUS_READY            0x00000100
+#define TG3_APE_FW_FEATURES            0x4010
+#define  TG3_APE_FW_FEATURE_NCSI        0x00000002
 #define TG3_APE_FW_VERSION             0x4018
 #define  APE_FW_VERSION_MAJMSK          0xff000000
 #define  APE_FW_VERSION_MAJSFT          24
 #define TG3_APE_HOST_SEG_SIG           0x4200
 #define  APE_HOST_SEG_SIG_MAGIC                 0x484f5354
 #define TG3_APE_HOST_SEG_LEN           0x4204
-#define  APE_HOST_SEG_LEN_MAGIC                 0x0000001c
+#define  APE_HOST_SEG_LEN_MAGIC                 0x00000020
 #define TG3_APE_HOST_INIT_COUNT                0x4208
 #define TG3_APE_HOST_DRIVER_ID         0x420c
-#define  APE_HOST_DRIVER_ID_MAGIC       0xf0035100
+#define  APE_HOST_DRIVER_ID_LINUX       0xf0000000
+#define  APE_HOST_DRIVER_ID_MAGIC(maj, min)    \
+       (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8)
 #define TG3_APE_HOST_BEHAVIOR          0x4210
 #define  APE_HOST_BEHAV_NO_PHYLOCK      0x00000001
 #define TG3_APE_HOST_HEARTBEAT_INT_MS  0x4214
 #define  APE_HOST_HEARTBEAT_INT_DISABLE         0
 #define  APE_HOST_HEARTBEAT_INT_5SEC    5000
 #define TG3_APE_HOST_HEARTBEAT_COUNT   0x4218
+#define TG3_APE_HOST_DRVR_STATE                0x421c
+#define TG3_APE_HOST_DRVR_STATE_START   0x00000001
+#define TG3_APE_HOST_DRVR_STATE_UNLOAD  0x00000002
+#define TG3_APE_HOST_DRVR_STATE_WOL     0x00000003
+#define TG3_APE_HOST_WOL_SPEED         0x4224
+#define TG3_APE_HOST_WOL_SPEED_AUTO     0x00008000
 
 #define TG3_APE_EVENT_STATUS           0x4300
 
 #define  APE_EVENT_STATUS_STATE_SUSPEND         0x00040000
 #define  APE_EVENT_STATUS_EVENT_PENDING         0x80000000
 
+#define TG3_APE_PER_LOCK_REQ           0x8400
+#define  APE_LOCK_PER_REQ_DRIVER        0x00001000
+#define TG3_APE_PER_LOCK_GRANT         0x8420
+#define  APE_PER_LOCK_GRANT_DRIVER      0x00001000
+
 /* APE convenience enumerations. */
 #define TG3_APE_LOCK_GRC                1
 #define TG3_APE_LOCK_MEM                4
+#define TG3_APE_LOCK_GPIO               7
 
 #define TG3_EEPROM_SB_F1R2_MBA_OFF     0x10
 
@@ -2464,7 +2635,12 @@ struct tg3_hw_stats {
        tg3_stat64_t                    nic_avoided_irqs;
        tg3_stat64_t                    nic_tx_threshold_hit;
 
-       u8                              __reserved4[0xb00-0x9c0];
+       /* NOT a part of the hardware statistics block format.
+        * These stats are here as storage for tg3_periodic_fetch_stats().
+        */
+       tg3_stat64_t                    mbuf_lwm_thresh_hit;
+
+       u8                              __reserved4[0xb00-0x9c8];
 };
 
 /* 'mapping' is superfluous as the chip does not write into
@@ -2473,11 +2649,13 @@ struct tg3_hw_stats {
  */
 struct ring_info {
        struct sk_buff                  *skb;
-       DECLARE_PCI_UNMAP_ADDR(mapping)
+       DEFINE_DMA_UNMAP_ADDR(mapping);
 };
 
-struct tg3_config_info {
-       u32                             flags;
+struct tg3_tx_ring_info {
+       struct sk_buff                  *skb;
+       DEFINE_DMA_UNMAP_ADDR(mapping);
+       bool                            fragmented;
 };
 
 struct tg3_link_config {
@@ -2500,7 +2678,6 @@ struct tg3_link_config {
        /* When we go in and out of low power mode we need
         * to swap with this state.
         */
-       int                             phy_is_low_power;
        u16                             orig_speed;
        u8                              orig_duplex;
        u8                              orig_autoneg;
@@ -2522,7 +2699,7 @@ struct tg3_bufmgr_config {
 
 struct tg3_ethtool_stats {
        /* Statistics maintained by Receive MAC. */
-       u64             rx_octets;
+       u64             rx_octets;
        u64             rx_fragments;
        u64             rx_ucast_packets;
        u64             rx_mcast_packets;
@@ -2601,6 +2778,8 @@ struct tg3_ethtool_stats {
        u64             nic_irqs;
        u64             nic_avoided_irqs;
        u64             nic_tx_threshold_hit;
+
+       u64             mbuf_lwm_thresh_hit;
 };
 
 struct tg3_rx_prodring_set {
@@ -2616,30 +2795,34 @@ struct tg3_rx_prodring_set {
        dma_addr_t                      rx_jmb_mapping;
 };
 
-#define TG3_IRQ_MAX_VECS 5
+#define TG3_IRQ_MAX_VECS_RSS           5
+#define TG3_IRQ_MAX_VECS               TG3_IRQ_MAX_VECS_RSS
 
 struct tg3_napi {
        struct napi_struct              napi    ____cacheline_aligned;
        struct tg3                      *tp;
        struct tg3_hw_status            *hw_status;
 
+       u32                             chk_msi_cnt;
        u32                             last_tag;
        u32                             last_irq_tag;
        u32                             int_mbox;
        u32                             coal_now;
-       u32                             tx_prod;
-       u32                             tx_cons;
-       u32                             tx_pending;
-       u32                             prodmbox;
 
-       u32                             consmbox;
+       u32                             consmbox ____cacheline_aligned;
        u32                             rx_rcb_ptr;
+       u32                             last_rx_cons;
        u16                             *rx_rcb_prod_idx;
-       struct tg3_rx_prodring_set      *prodring;
-
+       struct tg3_rx_prodring_set      prodring;
        struct tg3_rx_buffer_desc       *rx_rcb;
+
+       u32                             tx_prod ____cacheline_aligned;
+       u32                             tx_cons;
+       u32                             tx_pending;
+       u32                             last_tx_cons;
+       u32                             prodmbox;
        struct tg3_tx_buffer_desc       *tx_ring;
-       struct ring_info                *tx_buffers;
+       struct tg3_tx_ring_info         *tx_buffers;
 
        dma_addr_t                      status_mapping;
        dma_addr_t                      rx_rcb_mapping;
@@ -2649,6 +2832,85 @@ struct tg3_napi {
        unsigned int                    irq_vec;
 };
 
+enum TG3_FLAGS {
+       TG3_FLAG_TAGGED_STATUS = 0,
+       TG3_FLAG_TXD_MBOX_HWBUG,
+       TG3_FLAG_USE_LINKCHG_REG,
+       TG3_FLAG_ERROR_PROCESSED,
+       TG3_FLAG_ENABLE_ASF,
+       TG3_FLAG_ASPM_WORKAROUND,
+       TG3_FLAG_POLL_SERDES,
+       TG3_FLAG_MBOX_WRITE_REORDER,
+       TG3_FLAG_PCIX_TARGET_HWBUG,
+       TG3_FLAG_WOL_SPEED_100MB,
+       TG3_FLAG_WOL_ENABLE,
+       TG3_FLAG_EEPROM_WRITE_PROT,
+       TG3_FLAG_NVRAM,
+       TG3_FLAG_NVRAM_BUFFERED,
+       TG3_FLAG_SUPPORT_MSI,
+       TG3_FLAG_SUPPORT_MSIX,
+       TG3_FLAG_PCIX_MODE,
+       TG3_FLAG_PCI_HIGH_SPEED,
+       TG3_FLAG_PCI_32BIT,
+       TG3_FLAG_SRAM_USE_CONFIG,
+       TG3_FLAG_TX_RECOVERY_PENDING,
+       TG3_FLAG_WOL_CAP,
+       TG3_FLAG_JUMBO_RING_ENABLE,
+       TG3_FLAG_PAUSE_AUTONEG,
+       TG3_FLAG_CPMU_PRESENT,
+       TG3_FLAG_40BIT_DMA_BUG,
+       TG3_FLAG_BROKEN_CHECKSUMS,
+       TG3_FLAG_JUMBO_CAPABLE,
+       TG3_FLAG_CHIP_RESETTING,
+       TG3_FLAG_INIT_COMPLETE,
+       TG3_FLAG_RESTART_TIMER,
+       TG3_FLAG_TSO_BUG,
+       TG3_FLAG_IS_5788,
+       TG3_FLAG_MAX_RXPEND_64,
+       TG3_FLAG_TSO_CAPABLE,
+       TG3_FLAG_PCI_EXPRESS, /* BCM5785 + pci_is_pcie() */
+       TG3_FLAG_ASF_NEW_HANDSHAKE,
+       TG3_FLAG_HW_AUTONEG,
+       TG3_FLAG_IS_NIC,
+       TG3_FLAG_FLASH,
+       TG3_FLAG_HW_TSO_1,
+       TG3_FLAG_5705_PLUS,
+       TG3_FLAG_5750_PLUS,
+       TG3_FLAG_HW_TSO_3,
+       TG3_FLAG_USING_MSI,
+       TG3_FLAG_USING_MSIX,
+       TG3_FLAG_ICH_WORKAROUND,
+       TG3_FLAG_5780_CLASS,
+       TG3_FLAG_HW_TSO_2,
+       TG3_FLAG_1SHOT_MSI,
+       TG3_FLAG_NO_FWARE_REPORTED,
+       TG3_FLAG_NO_NVRAM_ADDR_TRANS,
+       TG3_FLAG_ENABLE_APE,
+       TG3_FLAG_PROTECTED_NVRAM,
+       TG3_FLAG_5701_DMA_BUG,
+       TG3_FLAG_USE_PHYLIB,
+       TG3_FLAG_MDIOBUS_INITED,
+       TG3_FLAG_LRG_PROD_RING_CAP,
+       TG3_FLAG_RGMII_INBAND_DISABLE,
+       TG3_FLAG_RGMII_EXT_IBND_RX_EN,
+       TG3_FLAG_RGMII_EXT_IBND_TX_EN,
+       TG3_FLAG_CLKREQ_BUG,
+       TG3_FLAG_5755_PLUS,
+       TG3_FLAG_NO_NVRAM,
+       TG3_FLAG_ENABLE_RSS,
+       TG3_FLAG_ENABLE_TSS,
+       TG3_FLAG_SHORT_DMA_BUG,
+       TG3_FLAG_USE_JUMBO_BDFLAG,
+       TG3_FLAG_L1PLLPD_EN,
+       TG3_FLAG_57765_PLUS,
+       TG3_FLAG_APE_HAS_NCSI,
+       TG3_FLAG_5717_PLUS,
+       TG3_FLAG_4K_FIFO_LIMIT,
+
+       /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
+       TG3_FLAG_NUMBER_OF_FLAGS,       /* Last entry in enum TG3_FLAGS */
+};
+
 struct tg3 {
        /* begin "general, frequently-used members" cacheline section */
 
@@ -2672,7 +2934,7 @@ struct tg3 {
        /* SMP locking strategy:
         *
         * lock: Held during reset, PHY access, timer, and when
-        *       updating tg3_flags and tg3_flags2.
+        *       updating tg3_flags.
         *
         * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
         *                netif_tx_lock when it needs to call
@@ -2712,128 +2974,30 @@ struct tg3 {
        struct tg3_napi                 napi[TG3_IRQ_MAX_VECS];
        void                            (*write32_rx_mbox) (struct tg3 *, u32,
                                                            u32);
+       u32                             rx_copy_thresh;
+       u32                             rx_std_ring_mask;
+       u32                             rx_jmb_ring_mask;
+       u32                             rx_ret_ring_mask;
        u32                             rx_pending;
        u32                             rx_jumbo_pending;
        u32                             rx_std_max_post;
+       u32                             rx_offset;
        u32                             rx_pkt_map_sz;
-#if TG3_VLAN_TAG_USED
-       struct vlan_group               *vlgrp;
-#endif
-
-       struct tg3_rx_prodring_set      prodring[TG3_IRQ_MAX_VECS];
 
 
        /* begin "everything else" cacheline(s) section */
-       struct net_device_stats         net_stats;
-       struct net_device_stats         net_stats_prev;
+       unsigned long                   rx_dropped;
+       struct rtnl_link_stats64        net_stats_prev;
        struct tg3_ethtool_stats        estats;
        struct tg3_ethtool_stats        estats_prev;
 
+       DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS);
+
        union {
        unsigned long                   phy_crc_errors;
        unsigned long                   last_event_jiffies;
        };
 
-       u32                             rx_offset;
-       u32                             tg3_flags;
-#define TG3_FLAG_TAGGED_STATUS         0x00000001
-#define TG3_FLAG_TXD_MBOX_HWBUG                0x00000002
-#define TG3_FLAG_RX_CHECKSUMS          0x00000004
-#define TG3_FLAG_USE_LINKCHG_REG       0x00000008
-#define TG3_FLAG_USE_MI_INTERRUPT      0x00000010
-#define TG3_FLAG_ENABLE_ASF            0x00000020
-#define TG3_FLAG_ASPM_WORKAROUND       0x00000040
-#define TG3_FLAG_POLL_SERDES           0x00000080
-#define TG3_FLAG_MBOX_WRITE_REORDER    0x00000100
-#define TG3_FLAG_PCIX_TARGET_HWBUG     0x00000200
-#define TG3_FLAG_WOL_SPEED_100MB       0x00000400
-#define TG3_FLAG_WOL_ENABLE            0x00000800
-#define TG3_FLAG_EEPROM_WRITE_PROT     0x00001000
-#define TG3_FLAG_NVRAM                 0x00002000
-#define TG3_FLAG_NVRAM_BUFFERED                0x00004000
-#define TG3_FLAG_SUPPORT_MSI           0x00008000
-#define TG3_FLAG_SUPPORT_MSIX          0x00010000
-#define TG3_FLAG_SUPPORT_MSI_OR_MSIX   (TG3_FLAG_SUPPORT_MSI | \
-                                        TG3_FLAG_SUPPORT_MSIX)
-#define TG3_FLAG_PCIX_MODE             0x00020000
-#define TG3_FLAG_PCI_HIGH_SPEED                0x00040000
-#define TG3_FLAG_PCI_32BIT             0x00080000
-#define TG3_FLAG_SRAM_USE_CONFIG       0x00100000
-#define TG3_FLAG_TX_RECOVERY_PENDING   0x00200000
-#define TG3_FLAG_WOL_CAP               0x00400000
-#define TG3_FLAG_JUMBO_RING_ENABLE     0x00800000
-#define TG3_FLAG_10_100_ONLY           0x01000000
-#define TG3_FLAG_PAUSE_AUTONEG         0x02000000
-#define TG3_FLAG_CPMU_PRESENT          0x04000000
-#define TG3_FLAG_40BIT_DMA_BUG         0x08000000
-#define TG3_FLAG_BROKEN_CHECKSUMS      0x10000000
-#define TG3_FLAG_JUMBO_CAPABLE         0x20000000
-#define TG3_FLAG_CHIP_RESETTING                0x40000000
-#define TG3_FLAG_INIT_COMPLETE         0x80000000
-       u32                             tg3_flags2;
-#define TG3_FLG2_RESTART_TIMER         0x00000001
-#define TG3_FLG2_TSO_BUG               0x00000002
-#define TG3_FLG2_NO_ETH_WIRE_SPEED     0x00000004
-#define TG3_FLG2_IS_5788               0x00000008
-#define TG3_FLG2_MAX_RXPEND_64         0x00000010
-#define TG3_FLG2_TSO_CAPABLE           0x00000020
-#define TG3_FLG2_PHY_ADC_BUG           0x00000040
-#define TG3_FLG2_PHY_5704_A0_BUG       0x00000080
-#define TG3_FLG2_PHY_BER_BUG           0x00000100
-#define TG3_FLG2_PCI_EXPRESS           0x00000200
-#define TG3_FLG2_ASF_NEW_HANDSHAKE     0x00000400
-#define TG3_FLG2_HW_AUTONEG            0x00000800
-#define TG3_FLG2_IS_NIC                        0x00001000
-#define TG3_FLG2_PHY_SERDES            0x00002000
-#define TG3_FLG2_CAPACITIVE_COUPLING   0x00004000
-#define TG3_FLG2_FLASH                 0x00008000
-#define TG3_FLG2_HW_TSO_1              0x00010000
-#define TG3_FLG2_SERDES_PREEMPHASIS    0x00020000
-#define TG3_FLG2_5705_PLUS             0x00040000
-#define TG3_FLG2_5750_PLUS             0x00080000
-#define TG3_FLG2_HW_TSO_3              0x00100000
-#define TG3_FLG2_USING_MSI             0x00200000
-#define TG3_FLG2_USING_MSIX            0x00400000
-#define TG3_FLG2_USING_MSI_OR_MSIX     (TG3_FLG2_USING_MSI | \
-                                       TG3_FLG2_USING_MSIX)
-#define TG3_FLG2_MII_SERDES            0x00800000
-#define TG3_FLG2_ANY_SERDES            (TG3_FLG2_PHY_SERDES |  \
-                                       TG3_FLG2_MII_SERDES)
-#define TG3_FLG2_PARALLEL_DETECT       0x01000000
-#define TG3_FLG2_ICH_WORKAROUND                0x02000000
-#define TG3_FLG2_5780_CLASS            0x04000000
-#define TG3_FLG2_HW_TSO_2              0x08000000
-#define TG3_FLG2_HW_TSO                        (TG3_FLG2_HW_TSO_1 | \
-                                        TG3_FLG2_HW_TSO_2 | \
-                                        TG3_FLG2_HW_TSO_3)
-#define TG3_FLG2_1SHOT_MSI             0x10000000
-#define TG3_FLG2_PHY_JITTER_BUG                0x20000000
-#define TG3_FLG2_NO_FWARE_REPORTED     0x40000000
-#define TG3_FLG2_PHY_ADJUST_TRIM       0x80000000
-       u32                             tg3_flags3;
-#define TG3_FLG3_NO_NVRAM_ADDR_TRANS   0x00000001
-#define TG3_FLG3_ENABLE_APE            0x00000002
-#define TG3_FLG3_PROTECTED_NVRAM       0x00000004
-#define TG3_FLG3_5701_DMA_BUG          0x00000008
-#define TG3_FLG3_USE_PHYLIB            0x00000010
-#define TG3_FLG3_MDIOBUS_INITED                0x00000020
-#define TG3_FLG3_PHY_CONNECTED         0x00000080
-#define TG3_FLG3_RGMII_STD_IBND_DISABLE        0x00000100
-#define TG3_FLG3_RGMII_EXT_IBND_RX_EN  0x00000200
-#define TG3_FLG3_RGMII_EXT_IBND_TX_EN  0x00000400
-#define TG3_FLG3_CLKREQ_BUG            0x00000800
-#define TG3_FLG3_PHY_ENABLE_APD                0x00001000
-#define TG3_FLG3_5755_PLUS             0x00002000
-#define TG3_FLG3_NO_NVRAM              0x00004000
-#define TG3_FLG3_PHY_IS_FET            0x00010000
-#define TG3_FLG3_ENABLE_RSS            0x00020000
-#define TG3_FLG3_ENABLE_TSS            0x00040000
-#define TG3_FLG3_4G_DMA_BNDRY_BUG      0x00080000
-#define TG3_FLG3_40BIT_DMA_LIMIT_BUG   0x00100000
-#define TG3_FLG3_SHORT_DMA_BUG         0x00200000
-#define TG3_FLG3_USE_JUMBO_BDFLAG      0x00400000
-#define TG3_FLG3_L1PLLPD_EN            0x00800000
-
        struct timer_list               timer;
        u16                             timer_counter;
        u16                             timer_multiplier;
@@ -2868,12 +3032,11 @@ struct tg3 {
        u8                              pci_cacheline_sz;
        u8                              pci_lat_timer;
 
+       int                             pci_fn;
        int                             pm_cap;
        int                             msi_cap;
-       union {
        int                             pcix_cap;
-       int                             pcie_cap;
-       };
+       int                             pcie_readrq;
 
        struct mii_bus                  *mdio_bus;
        int                             mdio_irq[PHY_MAX_ADDR];
@@ -2882,47 +3045,79 @@ struct tg3 {
 
        /* PHY info */
        u32                             phy_id;
-#define PHY_ID_MASK                    0xfffffff0
-#define PHY_ID_BCM5400                 0x60008040
-#define PHY_ID_BCM5401                 0x60008050
-#define PHY_ID_BCM5411                 0x60008070
-#define PHY_ID_BCM5701                 0x60008110
-#define PHY_ID_BCM5703                 0x60008160
-#define PHY_ID_BCM5704                 0x60008190
-#define PHY_ID_BCM5705                 0x600081a0
-#define PHY_ID_BCM5750                 0x60008180
-#define PHY_ID_BCM5752                 0x60008100
-#define PHY_ID_BCM5714                 0x60008340
-#define PHY_ID_BCM5780                 0x60008350
-#define PHY_ID_BCM5755                 0xbc050cc0
-#define PHY_ID_BCM5787                 0xbc050ce0
-#define PHY_ID_BCM5756                 0xbc050ed0
-#define PHY_ID_BCM5784                 0xbc050fa0
-#define PHY_ID_BCM5761                 0xbc050fd0
-#define PHY_ID_BCM5718C                        0x5c0d8a00
-#define PHY_ID_BCM5718S                        0xbc050ff0
-#define PHY_ID_BCM57765                        0x5c0d8a40
-#define PHY_ID_BCM5906                 0xdc00ac40
-#define PHY_ID_BCM8002                 0x60010140
-#define PHY_ID_INVALID                 0xffffffff
-#define PHY_ID_REV_MASK                        0x0000000f
-#define PHY_REV_BCM5401_B0             0x1
-#define PHY_REV_BCM5401_B2             0x3
-#define PHY_REV_BCM5401_C0             0x6
-#define PHY_REV_BCM5411_X0             0x1 /* Found on Netgear GA302T */
-#define TG3_PHY_ID_BCM50610            0x143bd60
-#define TG3_PHY_ID_BCM50610M   0x143bd70
-#define TG3_PHY_ID_BCMAC131            0x143bc70
-#define TG3_PHY_ID_RTL8211C            0x001cc910
-#define TG3_PHY_ID_RTL8201E            0x00008200
-#define TG3_PHY_ID_BCM57780            0x03625d90
-#define TG3_PHY_OUI_MASK               0xfffffc00
-#define TG3_PHY_OUI_1                  0x00206000
-#define TG3_PHY_OUI_2                  0x0143bc00
-#define TG3_PHY_OUI_3                  0x03625c00
+#define TG3_PHY_ID_MASK                        0xfffffff0
+#define TG3_PHY_ID_BCM5400             0x60008040
+#define TG3_PHY_ID_BCM5401             0x60008050
+#define TG3_PHY_ID_BCM5411             0x60008070
+#define TG3_PHY_ID_BCM5701             0x60008110
+#define TG3_PHY_ID_BCM5703             0x60008160
+#define TG3_PHY_ID_BCM5704             0x60008190
+#define TG3_PHY_ID_BCM5705             0x600081a0
+#define TG3_PHY_ID_BCM5750             0x60008180
+#define TG3_PHY_ID_BCM5752             0x60008100
+#define TG3_PHY_ID_BCM5714             0x60008340
+#define TG3_PHY_ID_BCM5780             0x60008350
+#define TG3_PHY_ID_BCM5755             0xbc050cc0
+#define TG3_PHY_ID_BCM5787             0xbc050ce0
+#define TG3_PHY_ID_BCM5756             0xbc050ed0
+#define TG3_PHY_ID_BCM5784             0xbc050fa0
+#define TG3_PHY_ID_BCM5761             0xbc050fd0
+#define TG3_PHY_ID_BCM5718C            0x5c0d8a00
+#define TG3_PHY_ID_BCM5718S            0xbc050ff0
+#define TG3_PHY_ID_BCM57765            0x5c0d8a40
+#define TG3_PHY_ID_BCM5719C            0x5c0d8a20
+#define TG3_PHY_ID_BCM5720C            0x5c0d8b60
+#define TG3_PHY_ID_BCM5906             0xdc00ac40
+#define TG3_PHY_ID_BCM8002             0x60010140
+#define TG3_PHY_ID_INVALID             0xffffffff
+
+#define PHY_ID_RTL8211C                        0x001cc910
+#define PHY_ID_RTL8201E                        0x00008200
+
+#define TG3_PHY_ID_REV_MASK            0x0000000f
+#define TG3_PHY_REV_BCM5401_B0         0x1
+
+       /* This macro assumes the passed PHY ID is
+        * already masked with TG3_PHY_ID_MASK.
+        */
+#define TG3_KNOWN_PHY_ID(X)            \
+       ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \
+        (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \
+        (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \
+        (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \
+        (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \
+        (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \
+        (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
+        (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
+        (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
+        (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
+        (X) == TG3_PHY_ID_BCM8002)
+
+       u32                             phy_flags;
+#define TG3_PHYFLG_IS_LOW_POWER                0x00000001
+#define TG3_PHYFLG_IS_CONNECTED                0x00000002
+#define TG3_PHYFLG_USE_MI_INTERRUPT    0x00000004
+#define TG3_PHYFLG_PHY_SERDES          0x00000010
+#define TG3_PHYFLG_MII_SERDES          0x00000020
+#define TG3_PHYFLG_ANY_SERDES          (TG3_PHYFLG_PHY_SERDES |        \
+                                       TG3_PHYFLG_MII_SERDES)
+#define TG3_PHYFLG_IS_FET              0x00000040
+#define TG3_PHYFLG_10_100_ONLY         0x00000080
+#define TG3_PHYFLG_ENABLE_APD          0x00000100
+#define TG3_PHYFLG_CAPACITIVE_COUPLING 0x00000200
+#define TG3_PHYFLG_NO_ETH_WIRE_SPEED   0x00000400
+#define TG3_PHYFLG_JITTER_BUG          0x00000800
+#define TG3_PHYFLG_ADJUST_TRIM         0x00001000
+#define TG3_PHYFLG_ADC_BUG             0x00002000
+#define TG3_PHYFLG_5704_A0_BUG         0x00004000
+#define TG3_PHYFLG_BER_BUG             0x00008000
+#define TG3_PHYFLG_SERDES_PREEMPHASIS  0x00010000
+#define TG3_PHYFLG_PARALLEL_DETECT     0x00020000
+#define TG3_PHYFLG_EEE_CAP             0x00040000
 
        u32                             led_ctrl;
        u32                             phy_otp;
+       u32                             setlpicnt;
 
 #define TG3_BPN_SIZE                   24
        char                            board_part_number[TG3_BPN_SIZE];
@@ -2932,27 +3127,13 @@ struct tg3 {
        u32                             pci_clock_ctrl;
        struct pci_dev                  *pdev_peer;
 
-       /* This macro assumes the passed PHY ID is already masked
-        * with PHY_ID_MASK.
-        */
-#define KNOWN_PHY_ID(X)                \
-       ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
-        (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
-        (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
-        (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
-        (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
-        (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
-        (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
-        (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
-        (X) == PHY_ID_BCM5718C || (X) == PHY_ID_BCM5718S || \
-        (X) == PHY_ID_BCM57765 || (X) == PHY_ID_BCM8002)
-
        struct tg3_hw_stats             *hw_stats;
        dma_addr_t                      stats_mapping;
        struct work_struct              reset_task;
 
        int                             nvram_lock_cnt;
        u32                             nvram_size;
+#define TG3_NVRAM_SIZE_2KB             0x00000800
 #define TG3_NVRAM_SIZE_64KB            0x00010000
 #define TG3_NVRAM_SIZE_128KB           0x00020000
 #define TG3_NVRAM_SIZE_256KB           0x00040000
@@ -2968,6 +3149,9 @@ struct tg3 {
 #define JEDEC_SAIFUN                   0x4f
 #define JEDEC_SST                      0xbf
 
+#define ATMEL_AT24C02_CHIP_SIZE                TG3_NVRAM_SIZE_2KB
+#define ATMEL_AT24C02_PAGE_SIZE                (8)
+
 #define ATMEL_AT24C64_CHIP_SIZE                TG3_NVRAM_SIZE_64KB
 #define ATMEL_AT24C64_PAGE_SIZE                (32)