tg3: Revise 5719 internal FIFO overflow solution
[linux-2.6.git] / drivers / net / tg3.h
index f6b709a..0a0987a 100644 (file)
 #define  CPMU_MUTEX_GNT_DRIVER          0x00001000
 #define TG3_CPMU_PHY_STRAP             0x00003664
 #define TG3_CPMU_PHY_STRAP_IS_SERDES    0x00000020
-/* 0x3664 --> 0x3800 unused */
+/* 0x3664 --> 0x36b0 unused */
+
+#define TG3_CPMU_EEE_MODE              0x000036b0
+#define  TG3_CPMU_EEEMD_APE_TX_DET_EN   0x00000004
+#define  TG3_CPMU_EEEMD_ERLY_L1_XIT_DET         0x00000008
+#define  TG3_CPMU_EEEMD_SND_IDX_DET_EN  0x00000040
+#define  TG3_CPMU_EEEMD_LPI_ENABLE      0x00000080
+#define  TG3_CPMU_EEEMD_LPI_IN_TX       0x00000100
+#define  TG3_CPMU_EEEMD_LPI_IN_RX       0x00000200
+#define  TG3_CPMU_EEEMD_EEE_ENABLE      0x00100000
+#define TG3_CPMU_EEE_DBTMR1            0x000036b4
+#define  TG3_CPMU_DBTMR1_PCIEXIT_2047US         0x07ff0000
+#define  TG3_CPMU_DBTMR1_LNKIDLE_2047US         0x000070ff
+#define TG3_CPMU_EEE_DBTMR2            0x000036b8
+#define  TG3_CPMU_DBTMR1_APE_TX_2047US  0x07ff0000
+#define  TG3_CPMU_DBTMR2_TXIDXEQ_2047US         0x000070ff
+#define TG3_CPMU_EEE_LNKIDL_CTRL       0x000036bc
+#define  TG3_CPMU_EEE_LNKIDL_PCIE_NL0   0x01000000
+#define  TG3_CPMU_EEE_LNKIDL_UART_IDL   0x00000004
+/* 0x36c0 --> 0x36d0 unused */
+
+#define TG3_CPMU_EEE_CTRL              0x000036d0
+#define TG3_CPMU_EEE_CTRL_EXIT_16_5_US  0x0000019d
+#define TG3_CPMU_EEE_CTRL_EXIT_36_US    0x00000384
+#define TG3_CPMU_EEE_CTRL_EXIT_20_1_US  0x000001f8
+/* 0x36d4 --> 0x3800 unused */
 
 /* Mbuf cluster free registers */
 #define MBFREE_MODE                    0x00003800
 
 #define TG3_RDMA_RSRVCTRL_REG          0x00004900
 #define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX         0x00000004
+#define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K         0x00000c00
+#define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK         0x00000ff0
+#define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K         0x000c0000
+#define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK         0x000ff000
+#define TG3_RDMA_RSRVCTRL_TXMRGN_320B   0x28000000
+#define TG3_RDMA_RSRVCTRL_TXMRGN_MASK   0xffe00000
 /* 0x4904 --> 0x4910 unused */
 
 #define TG3_LSO_RD_DMA_CRPTEN_CTRL     0x00004910
 #define TG3_EEPROM_SB_REVISION_3       0x00030000
 #define TG3_EEPROM_SB_REVISION_4       0x00040000
 #define TG3_EEPROM_SB_REVISION_5       0x00050000
+#define TG3_EEPROM_SB_REVISION_6       0x00060000
 #define TG3_EEPROM_MAGIC_HW            0xabcd
 #define TG3_EEPROM_MAGIC_HW_MSK                0xffff
 
 #define TG3_EEPROM_SB_F1R3_EDH_OFF     0x18
 #define TG3_EEPROM_SB_F1R4_EDH_OFF     0x1c
 #define TG3_EEPROM_SB_F1R5_EDH_OFF     0x20
+#define TG3_EEPROM_SB_F1R6_EDH_OFF     0x4c
 #define TG3_EEPROM_SB_EDH_MAJ_MASK     0x00000700
 #define TG3_EEPROM_SB_EDH_MAJ_SHFT     8
 #define TG3_EEPROM_SB_EDH_MIN_MASK     0x000000ff
 #define  MII_TG3_CTRL_AS_MASTER                0x0800
 #define  MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
 
+#define MII_TG3_MMD_CTRL               0x0d /* MMD Access Control register */
+#define MII_TG3_MMD_CTRL_DATA_NOINC    0x4000
+#define MII_TG3_MMD_ADDRESS            0x0e /* MMD Address Data register */
+
 #define MII_TG3_EXT_CTRL               0x10 /* Extended control register */
 #define  MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
 #define  MII_TG3_EXT_CTRL_LNK3_LED_MODE        0x0002
 #define MII_TG3_DSP_TAP1               0x0001
 #define  MII_TG3_DSP_TAP1_AGCTGT_DFLT  0x0007
 #define MII_TG3_DSP_AADJ1CH0           0x001f
+#define MII_TG3_DSP_CH34TP2            0x4022
+#define MII_TG3_DSP_CH34TP2_HIBW01     0x0010
 #define MII_TG3_DSP_AADJ1CH3           0x601f
 #define  MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
 #define MII_TG3_DSP_EXP1_INT_STAT      0x0f01
 #define MII_TG3_TEST1_TRIM_EN          0x0010
 #define MII_TG3_TEST1_CRC_EN           0x8000
 
+/* Clause 45 expansion registers */
+#define TG3_CL45_D7_EEERES_STAT                0x803e
+#define TG3_CL45_D7_EEERES_STAT_LP_100TX       0x0002
+#define TG3_CL45_D7_EEERES_STAT_LP_1000T       0x0004
+
 
 /* Fast Ethernet Tranceiver definitions */
 #define MII_TG3_FET_PTEST              0x17
@@ -2527,10 +2571,6 @@ struct ring_info {
        DEFINE_DMA_UNMAP_ADDR(mapping);
 };
 
-struct tg3_config_info {
-       u32                             flags;
-};
-
 struct tg3_link_config {
        /* Describes what we're trying to get. */
        u32                             advertising;
@@ -2678,17 +2718,17 @@ struct tg3_napi {
        u32                             last_irq_tag;
        u32                             int_mbox;
        u32                             coal_now;
-       u32                             tx_prod;
-       u32                             tx_cons;
-       u32                             tx_pending;
-       u32                             prodmbox;
 
-       u32                             consmbox;
+       u32                             consmbox ____cacheline_aligned;
        u32                             rx_rcb_ptr;
        u16                             *rx_rcb_prod_idx;
        struct tg3_rx_prodring_set      prodring;
-
        struct tg3_rx_buffer_desc       *rx_rcb;
+
+       u32                             tx_prod ____cacheline_aligned;
+       u32                             tx_cons;
+       u32                             tx_pending;
+       u32                             prodmbox;
        struct tg3_tx_buffer_desc       *tx_ring;
        struct ring_info                *tx_buffers;
 
@@ -2778,7 +2818,7 @@ struct tg3 {
 
 
        /* begin "everything else" cacheline(s) section */
-       struct rtnl_link_stats64        net_stats;
+       unsigned long                   rx_dropped;
        struct rtnl_link_stats64        net_stats_prev;
        struct tg3_ethtool_stats        estats;
        struct tg3_ethtool_stats        estats_prev;
@@ -2911,6 +2951,7 @@ struct tg3 {
        int                             pcix_cap;
        int                             pcie_cap;
        };
+       int                             pcie_readrq;
 
        struct mii_bus                  *mdio_bus;
        int                             mdio_irq[PHY_MAX_ADDR];
@@ -2986,9 +3027,11 @@ struct tg3 {
 #define TG3_PHYFLG_BER_BUG             0x00008000
 #define TG3_PHYFLG_SERDES_PREEMPHASIS  0x00010000
 #define TG3_PHYFLG_PARALLEL_DETECT     0x00020000
+#define TG3_PHYFLG_EEE_CAP             0x00040000
 
        u32                             led_ctrl;
        u32                             phy_otp;
+       u32                             setlpicnt;
 
 #define TG3_BPN_SIZE                   24
        char                            board_part_number[TG3_BPN_SIZE];