net: usb: raw-ip: Fix autopm / system suspend issues.
[linux-2.6.git] / drivers / net / tg3.c
index 5135655..d469004 100644 (file)
@@ -26,6 +26,7 @@
 #include <linux/delay.h>
 #include <linux/in.h>
 #include <linux/init.h>
+#include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/pci.h>
 #include <linux/netdevice.h>
 
 #include "tg3.h"
 
+/* Functions & macros to verify TG3_FLAGS types */
+
+static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
+{
+       return test_bit(flag, bits);
+}
+
+static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
+{
+       set_bit(flag, bits);
+}
+
+static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
+{
+       clear_bit(flag, bits);
+}
+
+#define tg3_flag(tp, flag)                             \
+       _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
+#define tg3_flag_set(tp, flag)                         \
+       _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
+#define tg3_flag_clear(tp, flag)                       \
+       _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
+
 #define DRV_MODULE_NAME                "tg3"
 #define TG3_MAJ_NUM                    3
-#define TG3_MIN_NUM                    117
+#define TG3_MIN_NUM                    119
 #define DRV_MODULE_VERSION     \
        __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
-#define DRV_MODULE_RELDATE     "January 25, 2011"
+#define DRV_MODULE_RELDATE     "May 18, 2011"
 
 #define TG3_DEF_MAC_MODE       0
 #define TG3_DEF_RX_MODE                0
         NETIF_MSG_RX_ERR       | \
         NETIF_MSG_TX_ERR)
 
+#define TG3_GRC_LCLCTL_PWRSW_DELAY     100
+
 /* length of time before we decide the hardware is borked,
  * and dev->tx_timeout() should be called to fix the problem
  */
+
 #define TG3_TX_TIMEOUT                 (5 * HZ)
 
 /* hardware minimum and maximum for a single frame's data payload */
 #define TG3_MIN_MTU                    60
 #define TG3_MAX_MTU(tp)        \
-       ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
+       (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
 
 /* These numbers seem to be hard coded in the NIC firmware somehow.
  * You can't change the ring sizes, but you can change where you place
  * them in the NIC onboard memory.
  */
 #define TG3_RX_STD_RING_SIZE(tp) \
-       ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
-         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
-        RX_STD_MAX_SIZE_5717 : 512)
+       (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
+        TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
 #define TG3_DEF_RX_RING_PENDING                200
 #define TG3_RX_JMB_RING_SIZE(tp) \
-       ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
-         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
-        1024 : 256)
+       (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
+        TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
 #define TG3_DEF_RX_JUMBO_RING_PENDING  100
 #define TG3_RSS_INDIR_TBL_SIZE         128
 
 
 /* minimum number of free TX descriptors required to wake up TX process */
 #define TG3_TX_WAKEUP_THRESH(tnapi)            ((tnapi)->tx_pending / 4)
+#define TG3_TX_BD_DMA_MAX              4096
 
 #define TG3_RAW_IP_ALIGN 2
 
-/* number of ETHTOOL_GSTATS u64's */
-#define TG3_NUM_STATS          (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
-
-#define TG3_NUM_TEST           6
-
 #define TG3_FW_UPDATE_TIMEOUT_SEC      5
 
 #define FIRMWARE_TG3           "tigon/tg3.bin"
@@ -266,6 +288,7 @@ static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
        {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
        {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
        {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
@@ -273,6 +296,7 @@ static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
        {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
        {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
        {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
+       {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
        {}
 };
 
@@ -280,7 +304,7 @@ MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 
 static const struct {
        const char string[ETH_GSTRING_LEN];
-} ethtool_stats_keys[TG3_NUM_STATS] = {
+} ethtool_stats_keys[] = {
        { "rx_octets" },
        { "rx_fragments" },
        { "rx_ucast_packets" },
@@ -356,12 +380,17 @@ static const struct {
        { "ring_status_update" },
        { "nic_irqs" },
        { "nic_avoided_irqs" },
-       { "nic_tx_threshold_hit" }
+       { "nic_tx_threshold_hit" },
+
+       { "mbuf_lwm_thresh_hit" },
 };
 
+#define TG3_NUM_STATS  ARRAY_SIZE(ethtool_stats_keys)
+
+
 static const struct {
        const char string[ETH_GSTRING_LEN];
-} ethtool_test_keys[TG3_NUM_TEST] = {
+} ethtool_test_keys[] = {
        { "nvram test     (online) " },
        { "link test      (online) " },
        { "register test  (offline)" },
@@ -370,6 +399,9 @@ static const struct {
        { "interrupt test (offline)" },
 };
 
+#define TG3_NUM_TEST   ARRAY_SIZE(ethtool_test_keys)
+
+
 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 {
        writel(val, tp->regs + off);
@@ -467,8 +499,7 @@ static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
  */
 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 {
-       if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
-           (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
+       if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
                /* Non-posted methods */
                tp->write32(tp, off, val);
        else {
@@ -488,8 +519,7 @@ static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 {
        tp->write32_mbox(tp, off, val);
-       if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
-           !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
+       if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
                tp->read32_mbox(tp, off);
 }
 
@@ -497,9 +527,9 @@ static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 {
        void __iomem *mbox = tp->regs + off;
        writel(val, mbox);
-       if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
+       if (tg3_flag(tp, TXD_MBOX_HWBUG))
                writel(val, mbox);
-       if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
+       if (tg3_flag(tp, MBOX_WRITE_REORDER))
                readl(mbox);
 }
 
@@ -528,12 +558,12 @@ static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 {
        unsigned long flags;
 
-       if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
            (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
                return;
 
        spin_lock_irqsave(&tp->indirect_lock, flags);
-       if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
+       if (tg3_flag(tp, SRAM_USE_CONFIG)) {
                pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
                pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 
@@ -553,14 +583,14 @@ static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 {
        unsigned long flags;
 
-       if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
            (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
                *val = 0;
                return;
        }
 
        spin_lock_irqsave(&tp->indirect_lock, flags);
-       if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
+       if (tg3_flag(tp, SRAM_USE_CONFIG)) {
                pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
                pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 
@@ -579,7 +609,7 @@ static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 static void tg3_ape_lock_init(struct tg3 *tp)
 {
        int i;
-       u32 regbase;
+       u32 regbase, bit;
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
                regbase = TG3_APE_LOCK_GRANT;
@@ -587,20 +617,34 @@ static void tg3_ape_lock_init(struct tg3 *tp)
                regbase = TG3_APE_PER_LOCK_GRANT;
 
        /* Make sure the driver hasn't any stale locks. */
-       for (i = 0; i < 8; i++)
+       for (i = 0; i < 8; i++) {
+               if (i == TG3_APE_LOCK_GPIO)
+                       continue;
                tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
+       }
+
+       /* Clear the correct bit of the GPIO lock too. */
+       if (!tp->pci_fn)
+               bit = APE_LOCK_GRANT_DRIVER;
+       else
+               bit = 1 << tp->pci_fn;
+
+       tg3_ape_write32(tp, regbase + 4 * TG3_APE_LOCK_GPIO, bit);
 }
 
 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 {
        int i, off;
        int ret = 0;
-       u32 status, req, gnt;
+       u32 status, req, gnt, bit;
 
-       if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
+       if (!tg3_flag(tp, ENABLE_APE))
                return 0;
 
        switch (locknum) {
+       case TG3_APE_LOCK_GPIO:
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
+                       return 0;
        case TG3_APE_LOCK_GRC:
        case TG3_APE_LOCK_MEM:
                break;
@@ -618,21 +662,24 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum)
 
        off = 4 * locknum;
 
-       tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
+       if (locknum != TG3_APE_LOCK_GPIO || !tp->pci_fn)
+               bit = APE_LOCK_REQ_DRIVER;
+       else
+               bit = 1 << tp->pci_fn;
+
+       tg3_ape_write32(tp, req + off, bit);
 
        /* Wait for up to 1 millisecond to acquire lock. */
        for (i = 0; i < 100; i++) {
                status = tg3_ape_read32(tp, gnt + off);
-               if (status == APE_LOCK_GRANT_DRIVER)
+               if (status == bit)
                        break;
                udelay(10);
        }
 
-       if (status != APE_LOCK_GRANT_DRIVER) {
+       if (status != bit) {
                /* Revoke the lock request. */
-               tg3_ape_write32(tp, gnt + off,
-                               APE_LOCK_GRANT_DRIVER);
-
+               tg3_ape_write32(tp, gnt + off, bit);
                ret = -EBUSY;
        }
 
@@ -641,12 +688,15 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum)
 
 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 {
-       u32 gnt;
+       u32 gnt, bit;
 
-       if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
+       if (!tg3_flag(tp, ENABLE_APE))
                return;
 
        switch (locknum) {
+       case TG3_APE_LOCK_GPIO:
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
+                       return;
        case TG3_APE_LOCK_GRC:
        case TG3_APE_LOCK_MEM:
                break;
@@ -659,7 +709,12 @@ static void tg3_ape_unlock(struct tg3 *tp, int locknum)
        else
                gnt = TG3_APE_PER_LOCK_GRANT;
 
-       tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
+       if (locknum != TG3_APE_LOCK_GPIO || !tp->pci_fn)
+               bit = APE_LOCK_GRANT_DRIVER;
+       else
+               bit = 1 << tp->pci_fn;
+
+       tg3_ape_write32(tp, gnt + 4 * locknum, bit);
 }
 
 static void tg3_disable_ints(struct tg3 *tp)
@@ -687,14 +742,14 @@ static void tg3_enable_ints(struct tg3 *tp)
                struct tg3_napi *tnapi = &tp->napi[i];
 
                tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
-               if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
+               if (tg3_flag(tp, 1SHOT_MSI))
                        tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 
                tp->coal_now |= tnapi->coal_now;
        }
 
        /* Force an initial interrupt */
-       if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
+       if (!tg3_flag(tp, TAGGED_STATUS) &&
            (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
                tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
        else
@@ -710,9 +765,7 @@ static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
        unsigned int work_exists = 0;
 
        /* check for phy events */
-       if (!(tp->tg3_flags &
-             (TG3_FLAG_USE_LINKCHG_REG |
-              TG3_FLAG_POLL_SERDES))) {
+       if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
                if (sblk->status & SD_STATUS_LINK_CHG)
                        work_exists = 1;
        }
@@ -740,8 +793,7 @@ static void tg3_int_reenable(struct tg3_napi *tnapi)
         * The last_tag we write above tells the chip which piece of
         * work we've completed.
         */
-       if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
-           tg3_has_work(tnapi))
+       if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
                tw32(HOSTCC_MODE, tp->coalesce_mode |
                     HOSTCC_MODE_ENABLE | tnapi->coal_now);
 }
@@ -751,8 +803,7 @@ static void tg3_switch_clocks(struct tg3 *tp)
        u32 clock_ctrl;
        u32 orig_clock_ctrl;
 
-       if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
-           (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
+       if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
                return;
 
        clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
@@ -763,7 +814,7 @@ static void tg3_switch_clocks(struct tg3 *tp)
                       0x1f);
        tp->pci_clock_ctrl = clock_ctrl;
 
-       if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
+       if (tg3_flag(tp, 5705_PLUS)) {
                if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
                        tw32_wait_f(TG3PCI_CLOCK_CTRL,
                                    clock_ctrl | CLOCK_CTRL_625_CORE, 40);
@@ -838,7 +889,7 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
        int ret;
 
        if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
-           (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
+           (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
                return 0;
 
        if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
@@ -880,6 +931,104 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
        return ret;
 }
 
+static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
+{
+       int err;
+
+       err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
+       if (err)
+               goto done;
+
+       err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
+       if (err)
+               goto done;
+
+       err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
+                          MII_TG3_MMD_CTRL_DATA_NOINC | devad);
+       if (err)
+               goto done;
+
+       err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
+
+done:
+       return err;
+}
+
+static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
+{
+       int err;
+
+       err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
+       if (err)
+               goto done;
+
+       err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
+       if (err)
+               goto done;
+
+       err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
+                          MII_TG3_MMD_CTRL_DATA_NOINC | devad);
+       if (err)
+               goto done;
+
+       err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
+
+done:
+       return err;
+}
+
+static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
+{
+       int err;
+
+       err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
+       if (!err)
+               err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
+
+       return err;
+}
+
+static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
+{
+       int err;
+
+       err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
+       if (!err)
+               err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
+
+       return err;
+}
+
+static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
+{
+       int err;
+
+       err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
+                          (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
+                          MII_TG3_AUXCTL_SHDWSEL_MISC);
+       if (!err)
+               err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
+
+       return err;
+}
+
+static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
+{
+       if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
+               set |= MII_TG3_AUXCTL_MISC_WREN;
+
+       return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
+}
+
+#define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
+       tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
+                            MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
+                            MII_TG3_AUXCTL_ACTL_TX_6DB)
+
+#define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
+       tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
+                            MII_TG3_AUXCTL_ACTL_TX_6DB);
+
 static int tg3_bmcr_reset(struct tg3 *tp)
 {
        u32 phy_control;
@@ -982,7 +1131,7 @@ static void tg3_mdio_config_5785(struct tg3 *tp)
                return;
        }
 
-       if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
+       if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
                val |= MAC_PHYCFG2_EMODE_MASK_MASK |
                       MAC_PHYCFG2_FMODE_MASK_MASK |
                       MAC_PHYCFG2_GMODE_MASK_MASK |
@@ -995,10 +1144,10 @@ static void tg3_mdio_config_5785(struct tg3 *tp)
        val = tr32(MAC_PHYCFG1);
        val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
                 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
-       if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
-               if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
+       if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
+               if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
                        val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
-               if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
+               if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
                        val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
        }
        val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
@@ -1013,13 +1162,13 @@ static void tg3_mdio_config_5785(struct tg3 *tp)
                 MAC_RGMII_MODE_TX_ENABLE |
                 MAC_RGMII_MODE_TX_LOWPWR |
                 MAC_RGMII_MODE_TX_RESET);
-       if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
-               if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
+       if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
+               if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
                        val |= MAC_RGMII_MODE_RX_INT_B |
                               MAC_RGMII_MODE_RX_QUALITY |
                               MAC_RGMII_MODE_RX_ACTIVITY |
                               MAC_RGMII_MODE_RX_ENG_DET;
-               if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
+               if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
                        val |= MAC_RGMII_MODE_TX_ENABLE |
                               MAC_RGMII_MODE_TX_LOWPWR |
                               MAC_RGMII_MODE_TX_RESET;
@@ -1033,7 +1182,7 @@ static void tg3_mdio_start(struct tg3 *tp)
        tw32_f(MAC_MI_MODE, tp->mi_mode);
        udelay(80);
 
-       if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
+       if (tg3_flag(tp, MDIOBUS_INITED) &&
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
                tg3_mdio_config_5785(tp);
 }
@@ -1044,11 +1193,10 @@ static int tg3_mdio_init(struct tg3 *tp)
        u32 reg;
        struct phy_device *phydev;
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
+       if (tg3_flag(tp, 5717_PLUS)) {
                u32 is_serdes;
 
-               tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
+               tp->phy_addr = tp->pci_fn + 1;
 
                if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
                        is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
@@ -1062,8 +1210,7 @@ static int tg3_mdio_init(struct tg3 *tp)
 
        tg3_mdio_start(tp);
 
-       if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
-           (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
+       if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
                return 0;
 
        tp->mdio_bus = mdiobus_alloc();
@@ -1119,11 +1266,11 @@ static int tg3_mdio_init(struct tg3 *tp)
                                     PHY_BRCM_RX_REFCLK_UNUSED |
                                     PHY_BRCM_DIS_TXCRXC_NOENRGY |
                                     PHY_BRCM_AUTO_PWRDWN_ENABLE;
-               if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
+               if (tg3_flag(tp, RGMII_INBAND_DISABLE))
                        phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
-               if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
+               if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
                        phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
-               if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
+               if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
                        phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
                /* fallthru */
        case PHY_ID_RTL8211C:
@@ -1137,7 +1284,7 @@ static int tg3_mdio_init(struct tg3 *tp)
                break;
        }
 
-       tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
+       tg3_flag_set(tp, MDIOBUS_INITED);
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
                tg3_mdio_config_5785(tp);
@@ -1147,59 +1294,13 @@ static int tg3_mdio_init(struct tg3 *tp)
 
 static void tg3_mdio_fini(struct tg3 *tp)
 {
-       if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
-               tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
+       if (tg3_flag(tp, MDIOBUS_INITED)) {
+               tg3_flag_clear(tp, MDIOBUS_INITED);
                mdiobus_unregister(tp->mdio_bus);
                mdiobus_free(tp->mdio_bus);
        }
 }
 
-static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
-{
-       int err;
-
-       err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
-       if (err)
-               goto done;
-
-       err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
-       if (err)
-               goto done;
-
-       err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
-                          MII_TG3_MMD_CTRL_DATA_NOINC | devad);
-       if (err)
-               goto done;
-
-       err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
-
-done:
-       return err;
-}
-
-static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
-{
-       int err;
-
-       err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
-       if (err)
-               goto done;
-
-       err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
-       if (err)
-               goto done;
-
-       err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
-                          MII_TG3_MMD_CTRL_DATA_NOINC | devad);
-       if (err)
-               goto done;
-
-       err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
-
-done:
-       return err;
-}
-
 /* tp->lock is held. */
 static inline void tg3_generate_fw_event(struct tg3 *tp)
 {
@@ -1247,8 +1348,7 @@ static void tg3_ump_link_report(struct tg3 *tp)
        u32 reg;
        u32 val;
 
-       if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
-           !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
+       if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
                return;
 
        tg3_wait_for_event_ack(tp);
@@ -1308,6 +1408,11 @@ static void tg3_link_report(struct tg3 *tp)
                            "on" : "off",
                            (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
                            "on" : "off");
+
+               if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
+                       netdev_info(tp->dev, "EEE is %s\n",
+                                   tp->setlpicnt ? "enabled" : "disabled");
+
                tg3_ump_link_report(tp);
        }
 }
@@ -1373,13 +1478,12 @@ static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
        u32 old_rx_mode = tp->rx_mode;
        u32 old_tx_mode = tp->tx_mode;
 
-       if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
+       if (tg3_flag(tp, USE_PHYLIB))
                autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
        else
                autoneg = tp->link_config.autoneg;
 
-       if (autoneg == AUTONEG_ENABLE &&
-           (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
+       if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
                if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
                        flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
                else
@@ -1576,28 +1680,6 @@ static void tg3_phy_fini(struct tg3 *tp)
        }
 }
 
-static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
-{
-       int err;
-
-       err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
-       if (!err)
-               err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
-
-       return err;
-}
-
-static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
-{
-       int err;
-
-       err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
-       if (!err)
-               err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
-
-       return err;
-}
-
 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
 {
        u32 phytest;
@@ -1622,9 +1704,8 @@ static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
 {
        u32 reg;
 
-       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
-           ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
+       if (!tg3_flag(tp, 5705_PLUS) ||
+           (tg3_flag(tp, 5717_PLUS) &&
             (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
                return;
 
@@ -1658,7 +1739,7 @@ static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
 {
        u32 phy;
 
-       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
+       if (!tg3_flag(tp, 5705_PLUS) ||
            (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
                return;
 
@@ -1680,31 +1761,33 @@ static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
                        tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
                }
        } else {
-               phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
-                     MII_TG3_AUXCTL_SHDWSEL_MISC;
-               if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
-                   !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
+               int ret;
+
+               ret = tg3_phy_auxctl_read(tp,
+                                         MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
+               if (!ret) {
                        if (enable)
                                phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
                        else
                                phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
-                       phy |= MII_TG3_AUXCTL_MISC_WREN;
-                       tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
+                       tg3_phy_auxctl_write(tp,
+                                            MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
                }
        }
 }
 
 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 {
+       int ret;
        u32 val;
 
        if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
                return;
 
-       if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
-           !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
-               tg3_writephy(tp, MII_TG3_AUX_CTRL,
-                            (val | (1 << 15) | (1 << 4)));
+       ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
+       if (!ret)
+               tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
+                                    val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
 }
 
 static void tg3_phy_apply_otp(struct tg3 *tp)
@@ -1716,11 +1799,8 @@ static void tg3_phy_apply_otp(struct tg3 *tp)
 
        otp = tp->phy_otp;
 
-       /* Enable SM_DSP clock and tx 6dB coding. */
-       phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
-             MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
-             MII_TG3_AUXCTL_ACTL_TX_6DB;
-       tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
+       if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
+               return;
 
        phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
        phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
@@ -1744,10 +1824,7 @@ static void tg3_phy_apply_otp(struct tg3 *tp)
              ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
        tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
 
-       /* Turn off SM_DSP clock. */
-       phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
-             MII_TG3_AUXCTL_ACTL_TX_6DB;
-       tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
+       TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
 }
 
 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
@@ -1776,37 +1853,42 @@ static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
                tg3_phy_cl45_read(tp, MDIO_MMD_AN,
                                  TG3_CL45_D7_EEERES_STAT, &val);
 
-               switch (val) {
-               case TG3_CL45_D7_EEERES_STAT_LP_1000T:
-                       switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
-                       case ASIC_REV_5717:
-                       case ASIC_REV_5719:
-                       case ASIC_REV_57765:
-                               /* Enable SM_DSP clock and tx 6dB coding. */
-                               val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
-                                     MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
-                                     MII_TG3_AUXCTL_ACTL_TX_6DB;
-                               tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
-
-                               tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
-
-                               /* Turn off SM_DSP clock. */
-                               val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
-                                     MII_TG3_AUXCTL_ACTL_TX_6DB;
-                               tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
-                       }
-                       /* Fallthrough */
-               case TG3_CL45_D7_EEERES_STAT_LP_100TX:
+               if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
+                   val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
                        tp->setlpicnt = 2;
-               }
        }
 
        if (!tp->setlpicnt) {
+               if (current_link_up == 1 &&
+                  !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
+                       tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
+                       TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
+               }
+
                val = tr32(TG3_CPMU_EEE_MODE);
                tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
        }
 }
 
+static void tg3_phy_eee_enable(struct tg3 *tp)
+{
+       u32 val;
+
+       if (tp->link_config.active_speed == SPEED_1000 &&
+           (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
+            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
+           !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
+               val = MII_TG3_DSP_TAP26_ALNOKO |
+                     MII_TG3_DSP_TAP26_RMRXSTO;
+               tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
+               TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
+       }
+
+       val = tr32(TG3_CPMU_EEE_MODE);
+       tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
+}
+
 static int tg3_wait_macro_done(struct tg3 *tp)
 {
        int limit = 100;
@@ -1935,18 +2017,18 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 
                /* Set full-duplex, 1000 mbps.  */
                tg3_writephy(tp, MII_BMCR,
-                            BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
+                            BMCR_FULLDPLX | BMCR_SPEED1000);
 
                /* Set to master mode.  */
-               if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
+               if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
                        continue;
 
-               tg3_writephy(tp, MII_TG3_CTRL,
-                            (MII_TG3_CTRL_AS_MASTER |
-                             MII_TG3_CTRL_ENABLE_AS_MASTER));
+               tg3_writephy(tp, MII_CTRL1000,
+                            CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
 
-               /* Enable SM_DSP_CLOCK and 6dB.  */
-               tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
+               err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
+               if (err)
+                       return err;
 
                /* Block the PHY control access.  */
                tg3_phydsp_write(tp, 0x8005, 0x0800);
@@ -1965,15 +2047,9 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
        tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
        tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
-               /* Set Extended packet length bit for jumbo frames */
-               tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
-       } else {
-               tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
-       }
+       TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
 
-       tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
+       tg3_writephy(tp, MII_CTRL1000, phy9_orig);
 
        if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
                reg32 &= ~0x3000;
@@ -2047,8 +2123,7 @@ static int tg3_phy_reset(struct tg3 *tp)
                }
        }
 
-       if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
+       if (tg3_flag(tp, 5717_PLUS) &&
            (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
                return 0;
 
@@ -2060,49 +2135,57 @@ static int tg3_phy_reset(struct tg3 *tp)
                tg3_phy_toggle_apd(tp, false);
 
 out:
-       if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
-               tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
+       if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
+           !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
                tg3_phydsp_write(tp, 0x201f, 0x2aaa);
                tg3_phydsp_write(tp, 0x000a, 0x0323);
-               tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
+               TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
        }
+
        if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
                tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
                tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
        }
+
        if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
-               tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
-               tg3_phydsp_write(tp, 0x000a, 0x310b);
-               tg3_phydsp_write(tp, 0x201f, 0x9506);
-               tg3_phydsp_write(tp, 0x401f, 0x14e2);
-               tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
+               if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
+                       tg3_phydsp_write(tp, 0x000a, 0x310b);
+                       tg3_phydsp_write(tp, 0x201f, 0x9506);
+                       tg3_phydsp_write(tp, 0x401f, 0x14e2);
+                       TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
+               }
        } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
-               tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
-               tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
-               if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
-                       tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
-                       tg3_writephy(tp, MII_TG3_TEST1,
-                                    MII_TG3_TEST1_TRIM_EN | 0x4);
-               } else
-                       tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
-               tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
+               if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
+                       tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
+                       if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
+                               tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
+                               tg3_writephy(tp, MII_TG3_TEST1,
+                                            MII_TG3_TEST1_TRIM_EN | 0x4);
+                       } else
+                               tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
+
+                       TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
+               }
        }
+
        /* Set Extended packet length bit (bit 14) on all chips that */
        /* support jumbo frames */
        if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
                /* Cannot do read-modify-write on 5401 */
-               tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
-       } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
+               tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
+       } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
                /* Set bit 14 with read-modify-write to preserve other bits */
-               if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
-                   !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
-                       tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
+               err = tg3_phy_auxctl_read(tp,
+                                         MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
+               if (!err)
+                       tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
+                                          val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
        }
 
        /* Set phy register 0x10 bit 0 to high fifo elasticity to support
         * jumbo frames transmission.
         */
-       if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
+       if (tg3_flag(tp, JUMBO_CAPABLE)) {
                if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
                        tg3_writephy(tp, MII_TG3_EXT_CTRL,
                                     val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
@@ -2118,121 +2201,239 @@ out:
        return 0;
 }
 
-static void tg3_frob_aux_power(struct tg3 *tp)
+#define TG3_GPIO_MSG_DRVR_PRES          0x00000001
+#define TG3_GPIO_MSG_NEED_VAUX          0x00000002
+#define TG3_GPIO_MSG_MASK               (TG3_GPIO_MSG_DRVR_PRES | \
+                                         TG3_GPIO_MSG_NEED_VAUX)
+#define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
+       ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
+        (TG3_GPIO_MSG_DRVR_PRES << 4) | \
+        (TG3_GPIO_MSG_DRVR_PRES << 8) | \
+        (TG3_GPIO_MSG_DRVR_PRES << 12))
+
+#define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
+       ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
+        (TG3_GPIO_MSG_NEED_VAUX << 4) | \
+        (TG3_GPIO_MSG_NEED_VAUX << 8) | \
+        (TG3_GPIO_MSG_NEED_VAUX << 12))
+
+static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
 {
-       bool need_vaux = false;
+       u32 status, shift;
 
-       /* The GPIOs do something completely different on 57765. */
-       if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
-               return;
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
+               status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
+       else
+               status = tr32(TG3_CPMU_DRV_STATUS);
 
-       if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
-            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
-            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) &&
-           tp->pdev_peer != tp->pdev) {
-               struct net_device *dev_peer;
+       shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
+       status &= ~(TG3_GPIO_MSG_MASK << shift);
+       status |= (newstat << shift);
 
-               dev_peer = pci_get_drvdata(tp->pdev_peer);
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
+               tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
+       else
+               tw32(TG3_CPMU_DRV_STATUS, status);
 
-               /* remove_one() may have been run on the peer. */
-               if (dev_peer) {
-                       struct tg3 *tp_peer = netdev_priv(dev_peer);
+       return status >> TG3_APE_GPIO_MSG_SHIFT;
+}
 
-                       if (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE)
-                               return;
+static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
+{
+       if (!tg3_flag(tp, IS_NIC))
+               return 0;
 
-                       if ((tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
-                           (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF))
-                               need_vaux = true;
-               }
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
+               if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
+                       return -EIO;
+
+               tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
+
+               tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
+                           TG3_GRC_LCLCTL_PWRSW_DELAY);
+
+               tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
+       } else {
+               tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
+                           TG3_GRC_LCLCTL_PWRSW_DELAY);
        }
 
-       if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) ||
-           (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
-               need_vaux = true;
+       return 0;
+}
 
-       if (need_vaux) {
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
-                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
-                       tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
-                                   (GRC_LCLCTRL_GPIO_OE0 |
+static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
+{
+       u32 grc_local_ctrl;
+
+       if (!tg3_flag(tp, IS_NIC) ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
+               return;
+
+       grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
+
+       tw32_wait_f(GRC_LOCAL_CTRL,
+                   grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
+                   TG3_GRC_LCLCTL_PWRSW_DELAY);
+
+       tw32_wait_f(GRC_LOCAL_CTRL,
+                   grc_local_ctrl,
+                   TG3_GRC_LCLCTL_PWRSW_DELAY);
+
+       tw32_wait_f(GRC_LOCAL_CTRL,
+                   grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
+                   TG3_GRC_LCLCTL_PWRSW_DELAY);
+}
+
+static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
+{
+       if (!tg3_flag(tp, IS_NIC))
+               return;
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
+               tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
+                           (GRC_LCLCTRL_GPIO_OE0 |
+                            GRC_LCLCTRL_GPIO_OE1 |
+                            GRC_LCLCTRL_GPIO_OE2 |
+                            GRC_LCLCTRL_GPIO_OUTPUT0 |
+                            GRC_LCLCTRL_GPIO_OUTPUT1),
+                           TG3_GRC_LCLCTL_PWRSW_DELAY);
+       } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
+                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
+               /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
+               u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
                                     GRC_LCLCTRL_GPIO_OE1 |
                                     GRC_LCLCTRL_GPIO_OE2 |
                                     GRC_LCLCTRL_GPIO_OUTPUT0 |
-                                    GRC_LCLCTRL_GPIO_OUTPUT1),
-                                   100);
-               } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
-                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
-                       /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
-                       u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
-                                            GRC_LCLCTRL_GPIO_OE1 |
-                                            GRC_LCLCTRL_GPIO_OE2 |
-                                            GRC_LCLCTRL_GPIO_OUTPUT0 |
-                                            GRC_LCLCTRL_GPIO_OUTPUT1 |
-                                            tp->grc_local_ctrl;
-                       tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
-
-                       grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
-                       tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
-
-                       grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
-                       tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
-               } else {
-                       u32 no_gpio2;
-                       u32 grc_local_ctrl = 0;
-
-                       /* Workaround to prevent overdrawing Amps. */
-                       if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
-                           ASIC_REV_5714) {
-                               grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
-                               tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
-                                           grc_local_ctrl, 100);
-                       }
+                                    GRC_LCLCTRL_GPIO_OUTPUT1 |
+                                    tp->grc_local_ctrl;
+               tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
+                           TG3_GRC_LCLCTL_PWRSW_DELAY);
+
+               grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
+               tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
+                           TG3_GRC_LCLCTL_PWRSW_DELAY);
+
+               grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
+               tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
+                           TG3_GRC_LCLCTL_PWRSW_DELAY);
+       } else {
+               u32 no_gpio2;
+               u32 grc_local_ctrl = 0;
 
-                       /* On 5753 and variants, GPIO2 cannot be used. */
-                       no_gpio2 = tp->nic_sram_data_cfg &
-                                   NIC_SRAM_DATA_CFG_NO_GPIO2;
-
-                       grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
-                                        GRC_LCLCTRL_GPIO_OE1 |
-                                        GRC_LCLCTRL_GPIO_OE2 |
-                                        GRC_LCLCTRL_GPIO_OUTPUT1 |
-                                        GRC_LCLCTRL_GPIO_OUTPUT2;
-                       if (no_gpio2) {
-                               grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
-                                                   GRC_LCLCTRL_GPIO_OUTPUT2);
-                       }
+               /* Workaround to prevent overdrawing Amps. */
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
+                       grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
                        tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
-                                                   grc_local_ctrl, 100);
+                                   grc_local_ctrl,
+                                   TG3_GRC_LCLCTL_PWRSW_DELAY);
+               }
 
-                       grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
+               /* On 5753 and variants, GPIO2 cannot be used. */
+               no_gpio2 = tp->nic_sram_data_cfg &
+                          NIC_SRAM_DATA_CFG_NO_GPIO2;
 
-                       tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
-                                                   grc_local_ctrl, 100);
+               grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
+                                 GRC_LCLCTRL_GPIO_OE1 |
+                                 GRC_LCLCTRL_GPIO_OE2 |
+                                 GRC_LCLCTRL_GPIO_OUTPUT1 |
+                                 GRC_LCLCTRL_GPIO_OUTPUT2;
+               if (no_gpio2) {
+                       grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
+                                           GRC_LCLCTRL_GPIO_OUTPUT2);
+               }
+               tw32_wait_f(GRC_LOCAL_CTRL,
+                           tp->grc_local_ctrl | grc_local_ctrl,
+                           TG3_GRC_LCLCTL_PWRSW_DELAY);
 
-                       if (!no_gpio2) {
-                               grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
-                               tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
-                                           grc_local_ctrl, 100);
-                       }
+               grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
+
+               tw32_wait_f(GRC_LOCAL_CTRL,
+                           tp->grc_local_ctrl | grc_local_ctrl,
+                           TG3_GRC_LCLCTL_PWRSW_DELAY);
+
+               if (!no_gpio2) {
+                       grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
+                       tw32_wait_f(GRC_LOCAL_CTRL,
+                                   tp->grc_local_ctrl | grc_local_ctrl,
+                                   TG3_GRC_LCLCTL_PWRSW_DELAY);
                }
-       } else {
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
-                   GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
-                       tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
-                                   (GRC_LCLCTRL_GPIO_OE1 |
-                                    GRC_LCLCTRL_GPIO_OUTPUT1), 100);
+       }
+}
 
-                       tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
-                                   GRC_LCLCTRL_GPIO_OE1, 100);
+static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
+{
+       u32 msg = 0;
 
-                       tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
-                                   (GRC_LCLCTRL_GPIO_OE1 |
-                                    GRC_LCLCTRL_GPIO_OUTPUT1), 100);
+       /* Serialize power state transitions */
+       if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
+               return;
+
+       if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
+               msg = TG3_GPIO_MSG_NEED_VAUX;
+
+       msg = tg3_set_function_status(tp, msg);
+
+       if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
+               goto done;
+
+       if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
+               tg3_pwrsrc_switch_to_vaux(tp);
+       else
+               tg3_pwrsrc_die_with_vmain(tp);
+
+done:
+       tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
+}
+
+static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
+{
+       bool need_vaux = false;
+
+       /* The GPIOs do something completely different on 57765. */
+       if (!tg3_flag(tp, IS_NIC) ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
+               return;
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
+               tg3_frob_aux_power_5717(tp, include_wol ?
+                                       tg3_flag(tp, WOL_ENABLE) != 0 : 0);
+               return;
+       }
+
+       if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
+               struct net_device *dev_peer;
+
+               dev_peer = pci_get_drvdata(tp->pdev_peer);
+
+               /* remove_one() may have been run on the peer. */
+               if (dev_peer) {
+                       struct tg3 *tp_peer = netdev_priv(dev_peer);
+
+                       if (tg3_flag(tp_peer, INIT_COMPLETE))
+                               return;
+
+                       if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
+                           tg3_flag(tp_peer, ENABLE_ASF))
+                               need_vaux = true;
                }
        }
+
+       if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
+           tg3_flag(tp, ENABLE_ASF))
+               need_vaux = true;
+
+       if (need_vaux)
+               tg3_pwrsrc_switch_to_vaux(tp);
+       else
+               tg3_pwrsrc_die_with_vmain(tp);
 }
 
 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
@@ -2304,11 +2505,10 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
                tg3_writephy(tp, MII_TG3_EXT_CTRL,
                             MII_TG3_EXT_CTRL_FORCE_LED_OFF);
 
-               tg3_writephy(tp, MII_TG3_AUX_CTRL,
-                            MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
-                            MII_TG3_AUXCTL_PCTL_100TX_LPWR |
-                            MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
-                            MII_TG3_AUXCTL_PCTL_VREG_11V);
+               val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
+                     MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
+                     MII_TG3_AUXCTL_PCTL_VREG_11V;
+               tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
        }
 
        /* The PHY should not be powered down on some chips because
@@ -2334,7 +2534,7 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
 /* tp->lock is held. */
 static int tg3_nvram_lock(struct tg3 *tp)
 {
-       if (tp->tg3_flags & TG3_FLAG_NVRAM) {
+       if (tg3_flag(tp, NVRAM)) {
                int i;
 
                if (tp->nvram_lock_cnt == 0) {
@@ -2357,7 +2557,7 @@ static int tg3_nvram_lock(struct tg3 *tp)
 /* tp->lock is held. */
 static void tg3_nvram_unlock(struct tg3 *tp)
 {
-       if (tp->tg3_flags & TG3_FLAG_NVRAM) {
+       if (tg3_flag(tp, NVRAM)) {
                if (tp->nvram_lock_cnt > 0)
                        tp->nvram_lock_cnt--;
                if (tp->nvram_lock_cnt == 0)
@@ -2368,8 +2568,7 @@ static void tg3_nvram_unlock(struct tg3 *tp)
 /* tp->lock is held. */
 static void tg3_enable_nvram_access(struct tg3 *tp)
 {
-       if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
-           !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
+       if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
                u32 nvaccess = tr32(NVRAM_ACCESS);
 
                tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
@@ -2379,8 +2578,7 @@ static void tg3_enable_nvram_access(struct tg3 *tp)
 /* tp->lock is held. */
 static void tg3_disable_nvram_access(struct tg3 *tp)
 {
-       if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
-           !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
+       if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
                u32 nvaccess = tr32(NVRAM_ACCESS);
 
                tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
@@ -2450,10 +2648,10 @@ static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
 
 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
 {
-       if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
-           (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
-           (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
-          !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
+       if (tg3_flag(tp, NVRAM) &&
+           tg3_flag(tp, NVRAM_BUFFERED) &&
+           tg3_flag(tp, FLASH) &&
+           !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
            (tp->nvram_jedecnum == JEDEC_ATMEL))
 
                addr = ((addr / tp->nvram_pagesize) <<
@@ -2465,10 +2663,10 @@ static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
 
 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
 {
-       if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
-           (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
-           (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
-          !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
+       if (tg3_flag(tp, NVRAM) &&
+           tg3_flag(tp, NVRAM_BUFFERED) &&
+           tg3_flag(tp, FLASH) &&
+           !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
            (tp->nvram_jedecnum == JEDEC_ATMEL))
 
                addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
@@ -2488,7 +2686,7 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
 {
        int ret;
 
-       if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
+       if (!tg3_flag(tp, NVRAM))
                return tg3_nvram_read_using_eeprom(tp, offset, val);
 
        offset = tg3_nvram_phys_addr(tp, offset);
@@ -2575,15 +2773,19 @@ static void tg3_enable_register_access(struct tg3 *tp)
 
 static int tg3_power_up(struct tg3 *tp)
 {
-       tg3_enable_register_access(tp);
+       int err;
 
-       pci_set_power_state(tp->pdev, PCI_D0);
+       tg3_enable_register_access(tp);
 
-       /* Switch out of Vaux if it is a NIC */
-       if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
-               tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
+       err = pci_set_power_state(tp->pdev, PCI_D0);
+       if (!err) {
+               /* Switch out of Vaux if it is a NIC */
+               tg3_pwrsrc_switch_to_vmain(tp);
+       } else {
+               netdev_err(tp->dev, "Transition to D0 failed\n");
+       }
 
-       return 0;
+       return err;
 }
 
 static int tg3_power_down_prepare(struct tg3 *tp)
@@ -2594,15 +2796,15 @@ static int tg3_power_down_prepare(struct tg3 *tp)
        tg3_enable_register_access(tp);
 
        /* Restore the CLKREQ setting. */
-       if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
+       if (tg3_flag(tp, CLKREQ_BUG)) {
                u16 lnkctl;
 
                pci_read_config_word(tp->pdev,
-                                    tp->pcie_cap + PCI_EXP_LNKCTL,
+                                    pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
                                     &lnkctl);
                lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
                pci_write_config_word(tp->pdev,
-                                     tp->pcie_cap + PCI_EXP_LNKCTL,
+                                     pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
                                      lnkctl);
        }
 
@@ -2611,9 +2813,9 @@ static int tg3_power_down_prepare(struct tg3 *tp)
             misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
 
        device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
-                            (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
+                            tg3_flag(tp, WOL_ENABLE);
 
-       if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
+       if (tg3_flag(tp, USE_PHYLIB)) {
                do_low_power = false;
                if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
                    !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
@@ -2634,9 +2836,8 @@ static int tg3_power_down_prepare(struct tg3 *tp)
                                      ADVERTISED_Autoneg |
                                      ADVERTISED_10baseT_Half;
 
-                       if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
-                           device_should_wake) {
-                               if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
+                       if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
+                               if (tg3_flag(tp, WOL_SPEED_100MB))
                                        advertising |=
                                                ADVERTISED_100baseT_Half |
                                                ADVERTISED_100baseT_Full |
@@ -2681,7 +2882,7 @@ static int tg3_power_down_prepare(struct tg3 *tp)
 
                val = tr32(GRC_VCPU_EXT_CTRL);
                tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
-       } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
+       } else if (!tg3_flag(tp, ENABLE_ASF)) {
                int i;
                u32 val;
 
@@ -2692,7 +2893,7 @@ static int tg3_power_down_prepare(struct tg3 *tp)
                        msleep(1);
                }
        }
-       if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
+       if (tg3_flag(tp, WOL_CAP))
                tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
                                                     WOL_DRV_STATE_SHUTDOWN |
                                                     WOL_DRV_WOL |
@@ -2702,8 +2903,13 @@ static int tg3_power_down_prepare(struct tg3 *tp)
                u32 mac_mode;
 
                if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
-                       if (do_low_power) {
-                               tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
+                       if (do_low_power &&
+                           !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
+                               tg3_phy_auxctl_write(tp,
+                                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
+                                              MII_TG3_AUXCTL_PCTL_WOL_EN |
+                                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
+                                              MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
                                udelay(40);
                        }
 
@@ -2715,8 +2921,7 @@ static int tg3_power_down_prepare(struct tg3 *tp)
                        mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
                        if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
                            ASIC_REV_5700) {
-                               u32 speed = (tp->tg3_flags &
-                                            TG3_FLAG_WOL_SPEED_100MB) ?
+                               u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
                                             SPEED_100 : SPEED_10;
                                if (tg3_5700_link_polarity(tp, speed))
                                        mac_mode |= MAC_MODE_LINK_POLARITY;
@@ -2727,17 +2932,15 @@ static int tg3_power_down_prepare(struct tg3 *tp)
                        mac_mode = MAC_MODE_PORT_MODE_TBI;
                }
 
-               if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
+               if (!tg3_flag(tp, 5750_PLUS))
                        tw32(MAC_LED_CTRL, tp->led_ctrl);
 
                mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
-               if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
-                   !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
-                   ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
-                    (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
+               if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
+                   (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
                        mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
 
-               if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
+               if (tg3_flag(tp, ENABLE_APE))
                        mac_mode |= MAC_MODE_APE_TX_EN |
                                    MAC_MODE_APE_RX_EN |
                                    MAC_MODE_TDE_ENABLE;
@@ -2749,7 +2952,7 @@ static int tg3_power_down_prepare(struct tg3 *tp)
                udelay(10);
        }
 
-       if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
+       if (!tg3_flag(tp, WOL_SPEED_100MB) &&
            (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
                u32 base_val;
@@ -2760,12 +2963,11 @@ static int tg3_power_down_prepare(struct tg3 *tp)
 
                tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
                            CLOCK_CTRL_PWRDOWN_PLL133, 40);
-       } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
-                  (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
-                  (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
+       } else if (tg3_flag(tp, 5780_CLASS) ||
+                  tg3_flag(tp, CPMU_PRESENT) ||
+                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
                /* do nothing */
-       } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
-                    (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
+       } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
                u32 newbits1, newbits2;
 
                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
@@ -2774,7 +2976,7 @@ static int tg3_power_down_prepare(struct tg3 *tp)
                                    CLOCK_CTRL_TXCLK_DISABLE |
                                    CLOCK_CTRL_ALTCLK);
                        newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
-               } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
+               } else if (tg3_flag(tp, 5705_PLUS)) {
                        newbits1 = CLOCK_CTRL_625_CORE;
                        newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
                } else {
@@ -2788,7 +2990,7 @@ static int tg3_power_down_prepare(struct tg3 *tp)
                tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
                            40);
 
-               if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
+               if (!tg3_flag(tp, 5705_PLUS)) {
                        u32 newbits3;
 
                        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
@@ -2805,11 +3007,10 @@ static int tg3_power_down_prepare(struct tg3 *tp)
                }
        }
 
-       if (!(device_should_wake) &&
-           !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
+       if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
                tg3_power_down_phy(tp, do_low_power);
 
-       tg3_frob_aux_power(tp);
+       tg3_frob_aux_power(tp, true);
 
        /* Workaround for unstable PLL clock */
        if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
@@ -2818,7 +3019,7 @@ static int tg3_power_down_prepare(struct tg3 *tp)
 
                val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
                tw32(0x7d00, val);
-               if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
+               if (!tg3_flag(tp, ENABLE_ASF)) {
                        int err;
 
                        err = tg3_nvram_lock(tp);
@@ -2837,7 +3038,7 @@ static void tg3_power_down(struct tg3 *tp)
 {
        tg3_power_down_prepare(tp);
 
-       pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
+       pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
        pci_set_power_state(tp->pdev, PCI_D3hot);
 }
 
@@ -2888,138 +3089,134 @@ static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8
        }
 }
 
-static void tg3_phy_copper_begin(struct tg3 *tp)
+static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
 {
-       u32 new_adv;
-       int i;
+       int err = 0;
+       u32 val, new_adv;
 
-       if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
-               /* Entering low power mode.  Disable gigabit and
-                * 100baseT advertisements.
-                */
-               tg3_writephy(tp, MII_TG3_CTRL, 0);
+       new_adv = ADVERTISE_CSMA;
+       if (advertise & ADVERTISED_10baseT_Half)
+               new_adv |= ADVERTISE_10HALF;
+       if (advertise & ADVERTISED_10baseT_Full)
+               new_adv |= ADVERTISE_10FULL;
+       if (advertise & ADVERTISED_100baseT_Half)
+               new_adv |= ADVERTISE_100HALF;
+       if (advertise & ADVERTISED_100baseT_Full)
+               new_adv |= ADVERTISE_100FULL;
 
-               new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
-                          ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
-               if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
-                       new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
+       new_adv |= tg3_advert_flowctrl_1000T(flowctrl);
 
-               tg3_writephy(tp, MII_ADVERTISE, new_adv);
-       } else if (tp->link_config.speed == SPEED_INVALID) {
-               if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
-                       tp->link_config.advertising &=
-                               ~(ADVERTISED_1000baseT_Half |
-                                 ADVERTISED_1000baseT_Full);
+       err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
+       if (err)
+               goto done;
 
-               new_adv = ADVERTISE_CSMA;
-               if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
-                       new_adv |= ADVERTISE_10HALF;
-               if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
-                       new_adv |= ADVERTISE_10FULL;
-               if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
-                       new_adv |= ADVERTISE_100HALF;
-               if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
-                       new_adv |= ADVERTISE_100FULL;
-
-               new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
-
-               tg3_writephy(tp, MII_ADVERTISE, new_adv);
-
-               if (tp->link_config.advertising &
-                   (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
-                       new_adv = 0;
-                       if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
-                               new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
-                       if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
-                               new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
-                       if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
-                           (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
-                            tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
-                               new_adv |= (MII_TG3_CTRL_AS_MASTER |
-                                           MII_TG3_CTRL_ENABLE_AS_MASTER);
-                       tg3_writephy(tp, MII_TG3_CTRL, new_adv);
-               } else {
-                       tg3_writephy(tp, MII_TG3_CTRL, 0);
-               }
-       } else {
-               new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
-               new_adv |= ADVERTISE_CSMA;
+       if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
+               goto done;
 
-               /* Asking for a specific link mode. */
-               if (tp->link_config.speed == SPEED_1000) {
-                       tg3_writephy(tp, MII_ADVERTISE, new_adv);
+       new_adv = 0;
+       if (advertise & ADVERTISED_1000baseT_Half)
+               new_adv |= ADVERTISE_1000HALF;
+       if (advertise & ADVERTISED_1000baseT_Full)
+               new_adv |= ADVERTISE_1000FULL;
 
-                       if (tp->link_config.duplex == DUPLEX_FULL)
-                               new_adv = MII_TG3_CTRL_ADV_1000_FULL;
-                       else
-                               new_adv = MII_TG3_CTRL_ADV_1000_HALF;
-                       if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
-                           tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
-                               new_adv |= (MII_TG3_CTRL_AS_MASTER |
-                                           MII_TG3_CTRL_ENABLE_AS_MASTER);
-               } else {
-                       if (tp->link_config.speed == SPEED_100) {
-                               if (tp->link_config.duplex == DUPLEX_FULL)
-                                       new_adv |= ADVERTISE_100FULL;
-                               else
-                                       new_adv |= ADVERTISE_100HALF;
-                       } else {
-                               if (tp->link_config.duplex == DUPLEX_FULL)
-                                       new_adv |= ADVERTISE_10FULL;
-                               else
-                                       new_adv |= ADVERTISE_10HALF;
-                       }
-                       tg3_writephy(tp, MII_ADVERTISE, new_adv);
+       if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
+           tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
+               new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
 
-                       new_adv = 0;
-               }
+       err = tg3_writephy(tp, MII_CTRL1000, new_adv);
+       if (err)
+               goto done;
 
-               tg3_writephy(tp, MII_TG3_CTRL, new_adv);
-       }
+       if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
+               goto done;
 
-       if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
-               u32 val;
+       tw32(TG3_CPMU_EEE_MODE,
+            tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
 
-               tw32(TG3_CPMU_EEE_MODE,
-                    tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
+       err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
+       if (!err) {
+               u32 err2;
 
-               /* Enable SM_DSP clock and tx 6dB coding. */
-               val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
-                     MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
-                     MII_TG3_AUXCTL_ACTL_TX_6DB;
-               tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
+               val = 0;
+               /* Advertise 100-BaseTX EEE ability */
+               if (advertise & ADVERTISED_100baseT_Full)
+                       val |= MDIO_AN_EEE_ADV_100TX;
+               /* Advertise 1000-BaseT EEE ability */
+               if (advertise & ADVERTISED_1000baseT_Full)
+                       val |= MDIO_AN_EEE_ADV_1000T;
+               err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
+               if (err)
+                       val = 0;
 
                switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
                case ASIC_REV_5717:
                case ASIC_REV_57765:
+               case ASIC_REV_5719:
+                       /* If we advertised any eee advertisements above... */
+                       if (val)
+                               val = MII_TG3_DSP_TAP26_ALNOKO |
+                                     MII_TG3_DSP_TAP26_RMRXSTO |
+                                     MII_TG3_DSP_TAP26_OPCSINPT;
+                       tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
+                       /* Fall through */
+               case ASIC_REV_5720:
                        if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
                                tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
                                                 MII_TG3_DSP_CH34TP2_HIBW01);
-                       /* Fall through */
-               case ASIC_REV_5719:
-                       val = MII_TG3_DSP_TAP26_ALNOKO |
-                             MII_TG3_DSP_TAP26_RMRXSTO |
-                             MII_TG3_DSP_TAP26_OPCSINPT;
-                       tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
                }
 
-               val = 0;
-               if (tp->link_config.autoneg == AUTONEG_ENABLE) {
-                       /* Advertise 100-BaseTX EEE ability */
-                       if (tp->link_config.advertising &
-                           ADVERTISED_100baseT_Full)
-                               val |= MDIO_AN_EEE_ADV_100TX;
-                       /* Advertise 1000-BaseT EEE ability */
-                       if (tp->link_config.advertising &
-                           ADVERTISED_1000baseT_Full)
-                               val |= MDIO_AN_EEE_ADV_1000T;
+               err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
+               if (!err)
+                       err = err2;
+       }
+
+done:
+       return err;
+}
+
+static void tg3_phy_copper_begin(struct tg3 *tp)
+{
+       u32 new_adv;
+       int i;
+
+       if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
+               new_adv = ADVERTISED_10baseT_Half |
+                         ADVERTISED_10baseT_Full;
+               if (tg3_flag(tp, WOL_SPEED_100MB))
+                       new_adv |= ADVERTISED_100baseT_Half |
+                                  ADVERTISED_100baseT_Full;
+
+               tg3_phy_autoneg_cfg(tp, new_adv,
+                                   FLOW_CTRL_TX | FLOW_CTRL_RX);
+       } else if (tp->link_config.speed == SPEED_INVALID) {
+               if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
+                       tp->link_config.advertising &=
+                               ~(ADVERTISED_1000baseT_Half |
+                                 ADVERTISED_1000baseT_Full);
+
+               tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
+                                   tp->link_config.flowctrl);
+       } else {
+               /* Asking for a specific link mode. */
+               if (tp->link_config.speed == SPEED_1000) {
+                       if (tp->link_config.duplex == DUPLEX_FULL)
+                               new_adv = ADVERTISED_1000baseT_Full;
+                       else
+                               new_adv = ADVERTISED_1000baseT_Half;
+               } else if (tp->link_config.speed == SPEED_100) {
+                       if (tp->link_config.duplex == DUPLEX_FULL)
+                               new_adv = ADVERTISED_100baseT_Full;
+                       else
+                               new_adv = ADVERTISED_100baseT_Half;
+               } else {
+                       if (tp->link_config.duplex == DUPLEX_FULL)
+                               new_adv = ADVERTISED_10baseT_Full;
+                       else
+                               new_adv = ADVERTISED_10baseT_Half;
                }
-               tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
 
-               /* Turn off SM_DSP clock. */
-               val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
-                     MII_TG3_AUXCTL_ACTL_TX_6DB;
-               tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
+               tg3_phy_autoneg_cfg(tp, new_adv,
+                                   tp->link_config.flowctrl);
        }
 
        if (tp->link_config.autoneg == AUTONEG_DISABLE &&
@@ -3040,7 +3237,7 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
                        break;
 
                case SPEED_1000:
-                       bmcr |= TG3_BMCR_SPEED1000;
+                       bmcr |= BMCR_SPEED1000;
                        break;
                }
 
@@ -3077,7 +3274,7 @@ static int tg3_init_5401phy_dsp(struct tg3 *tp)
 
        /* Turn off tap power management. */
        /* Set Extended packet length bit */
-       err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
+       err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
 
        err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
        err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
@@ -3117,7 +3314,7 @@ static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
                if (mask & ADVERTISED_1000baseT_Full)
                        all_mask |= ADVERTISE_1000FULL;
 
-               if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
+               if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
                        return 0;
 
                if ((tg3_ctrl & all_mask) != all_mask)
@@ -3140,7 +3337,7 @@ static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
                if (curadv != reqadv)
                        return 0;
 
-               if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
+               if (tg3_flag(tp, PAUSE_AUTONEG))
                        tg3_readphy(tp, MII_LPA, rmtadv);
        } else {
                /* Reprogram the advertisement register, even if it
@@ -3183,7 +3380,7 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
                udelay(80);
        }
 
-       tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
+       tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
 
        /* Some third-party PHYs need to be reset on link going
         * down.
@@ -3203,7 +3400,7 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
        if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
                tg3_readphy(tp, MII_BMSR, &bmsr);
                if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
-                   !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
+                   !tg3_flag(tp, INIT_COMPLETE))
                        bmsr = 0;
 
                if (!(bmsr & BMSR_LSTATUS)) {
@@ -3264,11 +3461,13 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
        current_duplex = DUPLEX_INVALID;
 
        if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
-               tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
-               tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
-               if (!(val & (1 << 10))) {
-                       val |= (1 << 10);
-                       tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
+               err = tg3_phy_auxctl_read(tp,
+                                         MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
+                                         &val);
+               if (!err && !(val & (1 << 10))) {
+                       tg3_phy_auxctl_write(tp,
+                                            MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
+                                            val | (1 << 10));
                        goto relink;
                }
        }
@@ -3341,8 +3540,8 @@ relink:
                tg3_phy_copper_begin(tp);
 
                tg3_readphy(tp, MII_BMSR, &bmsr);
-               if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
-                   (bmsr & BMSR_LSTATUS))
+               if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
+                   (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
                        current_link_up = 1;
        }
 
@@ -3385,7 +3584,7 @@ relink:
 
        tg3_phy_eee_adjust(tp, current_link_up);
 
-       if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
+       if (tg3_flag(tp, USE_LINKCHG_REG)) {
                /* Polled via timer. */
                tw32_f(MAC_EVENT, 0);
        } else {
@@ -3396,8 +3595,7 @@ relink:
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
            current_link_up == 1 &&
            tp->link_config.active_speed == SPEED_1000 &&
-           ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
-            (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
+           (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
                udelay(120);
                tw32_f(MAC_STATUS,
                     (MAC_STATUS_SYNC_CHANGED |
@@ -3409,11 +3607,11 @@ relink:
        }
 
        /* Prevent send BD corruption. */
-       if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
+       if (tg3_flag(tp, CLKREQ_BUG)) {
                u16 oldlnkctl, newlnkctl;
 
                pci_read_config_word(tp->pdev,
-                                    tp->pcie_cap + PCI_EXP_LNKCTL,
+                                    pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
                                     &oldlnkctl);
                if (tp->link_config.active_speed == SPEED_100 ||
                    tp->link_config.active_speed == SPEED_10)
@@ -3422,7 +3620,7 @@ relink:
                        newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
                if (newlnkctl != oldlnkctl)
                        pci_write_config_word(tp->pdev,
-                                             tp->pcie_cap + PCI_EXP_LNKCTL,
+                                             pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
                                              newlnkctl);
        }
 
@@ -3804,7 +4002,7 @@ static void tg3_init_bcm8002(struct tg3 *tp)
        int i;
 
        /* Reset when initting first time or we have a link. */
-       if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
+       if (tg3_flag(tp, INIT_COMPLETE) &&
            !(mac_status & MAC_STATUS_PCS_SYNCED))
                return;
 
@@ -4065,9 +4263,9 @@ static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
        orig_active_speed = tp->link_config.active_speed;
        orig_active_duplex = tp->link_config.active_duplex;
 
-       if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
+       if (!tg3_flag(tp, HW_AUTONEG) &&
            netif_carrier_ok(tp->dev) &&
-           (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
+           tg3_flag(tp, INIT_COMPLETE)) {
                mac_status = tr32(MAC_STATUS);
                mac_status &= (MAC_STATUS_PCS_SYNCED |
                               MAC_STATUS_SIGNAL_DET |
@@ -4098,7 +4296,7 @@ static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
        current_link_up = 0;
        mac_status = tr32(MAC_STATUS);
 
-       if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
+       if (tg3_flag(tp, HW_AUTONEG))
                current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
        else
                current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
@@ -4297,7 +4495,7 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
                                        current_duplex = DUPLEX_FULL;
                                else
                                        current_duplex = DUPLEX_HALF;
-                       } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
+                       } else if (!tg3_flag(tp, 5780_CLASS)) {
                                /* Link is up via parallel detect */
                        } else {
                                current_link_up = 0;
@@ -4394,6 +4592,7 @@ static void tg3_serdes_parallel_detect(struct tg3 *tp)
 
 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
 {
+       u32 val;
        int err;
 
        if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
@@ -4404,7 +4603,7 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
                err = tg3_setup_copper_phy(tp, force_reset);
 
        if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
-               u32 val, scale;
+               u32 scale;
 
                val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
                if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
@@ -4419,19 +4618,22 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
                tw32(GRC_MISC_CFG, val);
        }
 
+       val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
+             (6 << TX_LENGTHS_IPG_SHIFT);
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
+               val |= tr32(MAC_TX_LENGTHS) &
+                      (TX_LENGTHS_JMB_FRM_LEN_MSK |
+                       TX_LENGTHS_CNT_DWN_VAL_MSK);
+
        if (tp->link_config.active_speed == SPEED_1000 &&
            tp->link_config.active_duplex == DUPLEX_HALF)
-               tw32(MAC_TX_LENGTHS,
-                    ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
-                     (6 << TX_LENGTHS_IPG_SHIFT) |
-                     (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
+               tw32(MAC_TX_LENGTHS, val |
+                    (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
        else
-               tw32(MAC_TX_LENGTHS,
-                    ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
-                     (6 << TX_LENGTHS_IPG_SHIFT) |
-                     (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
+               tw32(MAC_TX_LENGTHS, val |
+                    (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
 
-       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
+       if (!tg3_flag(tp, 5705_PLUS)) {
                if (netif_carrier_ok(tp->dev)) {
                        tw32(HOSTCC_STAT_COAL_TICKS,
                             tp->coal.stats_block_coalesce_usecs);
@@ -4440,8 +4642,8 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
                }
        }
 
-       if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
-               u32 val = tr32(PCIE_PWR_MGMT_THRESH);
+       if (tg3_flag(tp, ASPM_WORKAROUND)) {
+               val = tr32(PCIE_PWR_MGMT_THRESH);
                if (!netif_carrier_ok(tp->dev))
                        val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
                              tp->pwrmgmt_thresh;
@@ -4458,6 +4660,123 @@ static inline int tg3_irq_sync(struct tg3 *tp)
        return tp->irq_sync;
 }
 
+static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
+{
+       int i;
+
+       dst = (u32 *)((u8 *)dst + off);
+       for (i = 0; i < len; i += sizeof(u32))
+               *dst++ = tr32(off + i);
+}
+
+static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
+{
+       tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
+       tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
+       tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
+       tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
+       tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
+       tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
+       tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
+       tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
+       tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
+       tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
+       tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
+       tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
+       tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
+       tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
+       tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
+       tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
+       tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
+       tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
+       tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
+
+       if (tg3_flag(tp, SUPPORT_MSIX))
+               tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
+
+       tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
+       tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
+       tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
+       tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
+       tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
+       tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
+       tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
+       tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
+
+       if (!tg3_flag(tp, 5705_PLUS)) {
+               tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
+               tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
+               tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
+       }
+
+       tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
+       tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
+       tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
+       tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
+       tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
+
+       if (tg3_flag(tp, NVRAM))
+               tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
+}
+
+static void tg3_dump_state(struct tg3 *tp)
+{
+       int i;
+       u32 *regs;
+
+       regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
+       if (!regs) {
+               netdev_err(tp->dev, "Failed allocating register dump buffer\n");
+               return;
+       }
+
+       if (tg3_flag(tp, PCI_EXPRESS)) {
+               /* Read up to but not including private PCI registers */
+               for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
+                       regs[i / sizeof(u32)] = tr32(i);
+       } else
+               tg3_dump_legacy_regs(tp, regs);
+
+       for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
+               if (!regs[i + 0] && !regs[i + 1] &&
+                   !regs[i + 2] && !regs[i + 3])
+                       continue;
+
+               netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
+                          i * 4,
+                          regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
+       }
+
+       kfree(regs);
+
+       for (i = 0; i < tp->irq_cnt; i++) {
+               struct tg3_napi *tnapi = &tp->napi[i];
+
+               /* SW status block */
+               netdev_err(tp->dev,
+                        "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
+                          i,
+                          tnapi->hw_status->status,
+                          tnapi->hw_status->status_tag,
+                          tnapi->hw_status->rx_jumbo_consumer,
+                          tnapi->hw_status->rx_consumer,
+                          tnapi->hw_status->rx_mini_consumer,
+                          tnapi->hw_status->idx[0].rx_producer,
+                          tnapi->hw_status->idx[0].tx_consumer);
+
+               netdev_err(tp->dev,
+               "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
+                          i,
+                          tnapi->last_tag, tnapi->last_irq_tag,
+                          tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
+                          tnapi->rx_rcb_ptr,
+                          tnapi->prodring.rx_std_prod_idx,
+                          tnapi->prodring.rx_std_cons_idx,
+                          tnapi->prodring.rx_jmb_prod_idx,
+                          tnapi->prodring.rx_jmb_cons_idx);
+       }
+}
+
 /* This is called whenever we suspect that the system chipset is re-
  * ordering the sequence of MMIO to the tx send mailbox. The symptom
  * is bogus tx completions. We try to recover by setting the
@@ -4466,7 +4785,7 @@ static inline int tg3_irq_sync(struct tg3 *tp)
  */
 static void tg3_tx_recover(struct tg3 *tp)
 {
-       BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
+       BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
               tp->write32_tx_mbox == tg3_write_indirect_mbox);
 
        netdev_warn(tp->dev,
@@ -4476,7 +4795,7 @@ static void tg3_tx_recover(struct tg3 *tp)
                    "and include system chipset information.\n");
 
        spin_lock(&tp->lock);
-       tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
+       tg3_flag_set(tp, TX_RECOVERY_PENDING);
        spin_unlock(&tp->lock);
 }
 
@@ -4500,13 +4819,13 @@ static void tg3_tx(struct tg3_napi *tnapi)
        struct netdev_queue *txq;
        int index = tnapi - tp->napi;
 
-       if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
+       if (tg3_flag(tp, ENABLE_TSS))
                index--;
 
        txq = netdev_get_tx_queue(tp->dev, index);
 
        while (sw_idx != hw_idx) {
-               struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
+               struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
                struct sk_buff *skb = ri->skb;
                int i, tx_bug = 0;
 
@@ -4522,6 +4841,12 @@ static void tg3_tx(struct tg3_napi *tnapi)
 
                ri->skb = NULL;
 
+               while (ri->fragmented) {
+                       ri->fragmented = false;
+                       sw_idx = NEXT_TX(sw_idx);
+                       ri = &tnapi->tx_buffers[sw_idx];
+               }
+
                sw_idx = NEXT_TX(sw_idx);
 
                for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
@@ -4533,6 +4858,13 @@ static void tg3_tx(struct tg3_napi *tnapi)
                                       dma_unmap_addr(ri, mapping),
                                       skb_shinfo(skb)->frags[i].size,
                                       PCI_DMA_TODEVICE);
+
+                       while (ri->fragmented) {
+                               ri->fragmented = false;
+                               sw_idx = NEXT_TX(sw_idx);
+                               ri = &tnapi->tx_buffers[sw_idx];
+                       }
+
                        sw_idx = NEXT_TX(sw_idx);
                }
 
@@ -4815,7 +5147,7 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget)
                        skb = copy_skb;
                }
 
-               if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
+               if ((tp->dev->features & NETIF_F_RXCSUM) &&
                    (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
                    (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
                      >> RXD_TCPCSUM_SHIFT) == 0xffff))
@@ -4868,7 +5200,7 @@ next_pkt_nopost:
        tw32_rx_mbox(tnapi->consmbox, sw_idx);
 
        /* Refill RX ring(s). */
-       if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
+       if (!tg3_flag(tp, ENABLE_RSS)) {
                if (work_mask & RXD_OPAQUE_RING_STD) {
                        tpr->rx_std_prod_idx = std_prod_idx &
                                               tp->rx_std_ring_mask;
@@ -4901,16 +5233,14 @@ next_pkt_nopost:
 static void tg3_poll_link(struct tg3 *tp)
 {
        /* handle link change and other phy events */
-       if (!(tp->tg3_flags &
-             (TG3_FLAG_USE_LINKCHG_REG |
-              TG3_FLAG_POLL_SERDES))) {
+       if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
                struct tg3_hw_status *sblk = tp->napi[0].hw_status;
 
                if (sblk->status & SD_STATUS_LINK_CHG) {
                        sblk->status = SD_STATUS_UPDATED |
                                       (sblk->status & ~SD_STATUS_LINK_CHG);
                        spin_lock(&tp->lock);
-                       if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
+                       if (tg3_flag(tp, USE_PHYLIB)) {
                                tw32_f(MAC_STATUS,
                                     (MAC_STATUS_SYNC_CHANGED |
                                      MAC_STATUS_CFG_CHANGED |
@@ -5057,7 +5387,7 @@ static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
        /* run TX completion thread */
        if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
                tg3_tx(tnapi);
-               if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
+               if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
                        return work_done;
        }
 
@@ -5068,7 +5398,7 @@ static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
        if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
                work_done += tg3_rx(tnapi, budget - work_done);
 
-       if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
+       if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
                struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
                int i, err = 0;
                u32 std_prod_idx = dpr->rx_std_prod_idx;
@@ -5107,7 +5437,7 @@ static int tg3_poll_msix(struct napi_struct *napi, int budget)
        while (1) {
                work_done = tg3_poll_work(tnapi, work_done, budget);
 
-               if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
+               if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
                        goto tx_recovery;
 
                if (unlikely(work_done >= budget))
@@ -5141,6 +5471,40 @@ tx_recovery:
        return work_done;
 }
 
+static void tg3_process_error(struct tg3 *tp)
+{
+       u32 val;
+       bool real_error = false;
+
+       if (tg3_flag(tp, ERROR_PROCESSED))
+               return;
+
+       /* Check Flow Attention register */
+       val = tr32(HOSTCC_FLOW_ATTN);
+       if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
+               netdev_err(tp->dev, "FLOW Attention error.  Resetting chip.\n");
+               real_error = true;
+       }
+
+       if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
+               netdev_err(tp->dev, "MSI Status error.  Resetting chip.\n");
+               real_error = true;
+       }
+
+       if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
+               netdev_err(tp->dev, "DMA Status error.  Resetting chip.\n");
+               real_error = true;
+       }
+
+       if (!real_error)
+               return;
+
+       tg3_dump_state(tp);
+
+       tg3_flag_set(tp, ERROR_PROCESSED);
+       schedule_work(&tp->reset_task);
+}
+
 static int tg3_poll(struct napi_struct *napi, int budget)
 {
        struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
@@ -5149,17 +5513,20 @@ static int tg3_poll(struct napi_struct *napi, int budget)
        struct tg3_hw_status *sblk = tnapi->hw_status;
 
        while (1) {
+               if (sblk->status & SD_STATUS_ERROR)
+                       tg3_process_error(tp);
+
                tg3_poll_link(tp);
 
                work_done = tg3_poll_work(tnapi, work_done, budget);
 
-               if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
+               if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
                        goto tx_recovery;
 
                if (unlikely(work_done >= budget))
                        break;
 
-               if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
+               if (tg3_flag(tp, TAGGED_STATUS)) {
                        /* tp->last_tag is used in tg3_int_reenable() below
                         * to tell the hw how much work has been processed,
                         * so we must read it before checking for more work.
@@ -5326,7 +5693,7 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id)
         * interrupt is ours and will flush the status block.
         */
        if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
-               if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
+               if (tg3_flag(tp, CHIP_RESETTING) ||
                    (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
                        handled = 0;
                        goto out;
@@ -5375,7 +5742,7 @@ static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
         * interrupt is ours and will flush the status block.
         */
        if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
-               if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
+               if (tg3_flag(tp, CHIP_RESETTING) ||
                    (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
                        handled = 0;
                        goto out;
@@ -5488,14 +5855,14 @@ static void tg3_reset_task(struct work_struct *work)
 
        tg3_full_lock(tp, 1);
 
-       restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
-       tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
+       restart_timer = tg3_flag(tp, RESTART_TIMER);
+       tg3_flag_clear(tp, RESTART_TIMER);
 
-       if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
+       if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
                tp->write32_tx_mbox = tg3_write32_tx_mbox;
                tp->write32_rx_mbox = tg3_write_flush_reg32;
-               tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
-               tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
+               tg3_flag_set(tp, MBOX_WRITE_REORDER);
+               tg3_flag_clear(tp, TX_RECOVERY_PENDING);
        }
 
        tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
@@ -5515,21 +5882,13 @@ out:
                tg3_phy_start(tp);
 }
 
-static void tg3_dump_short_state(struct tg3 *tp)
-{
-       netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
-                  tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
-       netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
-                  tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
-}
-
 static void tg3_tx_timeout(struct net_device *dev)
 {
        struct tg3 *tp = netdev_priv(dev);
 
        if (netif_msg_tx_err(tp)) {
                netdev_err(dev, "transmit timed out, resetting\n");
-               tg3_dump_short_state(tp);
+               tg3_dump_state(tp);
        }
 
        schedule_work(&tp->reset_task);
@@ -5548,7 +5907,7 @@ static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
                                          int len)
 {
 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
-       if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
+       if (tg3_flag(tp, 40BIT_DMA_BUG))
                return ((u64) mapping + len) > DMA_BIT_MASK(40);
        return 0;
 #else
@@ -5556,285 +5915,172 @@ static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
 #endif
 }
 
-static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
+static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
+                                dma_addr_t mapping, u32 len, u32 flags,
+                                u32 mss, u32 vlan)
+{
+       txbd->addr_hi = ((u64) mapping >> 32);
+       txbd->addr_lo = ((u64) mapping & 0xffffffff);
+       txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
+       txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
+}
 
-/* Workaround 4GB and 40-bit hardware DMA bugs. */
-static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
-                                      struct sk_buff *skb, u32 last_plus_one,
-                                      u32 *start, u32 base_flags, u32 mss)
+static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
+                           dma_addr_t map, u32 len, u32 flags,
+                           u32 mss, u32 vlan)
 {
        struct tg3 *tp = tnapi->tp;
-       struct sk_buff *new_skb;
-       dma_addr_t new_addr = 0;
-       u32 entry = *start;
-       int i, ret = 0;
+       bool hwbug = false;
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
-               new_skb = skb_copy(skb, GFP_ATOMIC);
-       else {
-               int more_headroom = 4 - ((unsigned long)skb->data & 3);
+       if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
+               hwbug = 1;
 
-               new_skb = skb_copy_expand(skb,
-                                         skb_headroom(skb) + more_headroom,
-                                         skb_tailroom(skb), GFP_ATOMIC);
-       }
+       if (tg3_4g_overflow_test(map, len))
+               hwbug = 1;
 
-       if (!new_skb) {
-               ret = -1;
-       } else {
-               /* New SKB is guaranteed to be linear. */
-               entry = *start;
-               new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
-                                         PCI_DMA_TODEVICE);
-               /* Make sure the mapping succeeded */
-               if (pci_dma_mapping_error(tp->pdev, new_addr)) {
-                       ret = -1;
-                       dev_kfree_skb(new_skb);
-                       new_skb = NULL;
+       if (tg3_40bit_overflow_test(tp, map, len))
+               hwbug = 1;
 
-               /* Make sure new skb does not cross any 4G boundaries.
-                * Drop the packet if it does.
-                */
-               } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
-                           tg3_4g_overflow_test(new_addr, new_skb->len)) {
-                       pci_unmap_single(tp->pdev, new_addr, new_skb->len,
-                                        PCI_DMA_TODEVICE);
-                       ret = -1;
-                       dev_kfree_skb(new_skb);
-                       new_skb = NULL;
-               } else {
-                       tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
-                                   base_flags, 1 | (mss << 1));
-                       *start = NEXT_TX(entry);
-               }
-       }
+       if (tg3_flag(tp, 4K_FIFO_LIMIT)) {
+               u32 tmp_flag = flags & ~TXD_FLAG_END;
+               while (len > TG3_TX_BD_DMA_MAX) {
+                       u32 frag_len = TG3_TX_BD_DMA_MAX;
+                       len -= TG3_TX_BD_DMA_MAX;
 
-       /* Now clean up the sw ring entries. */
-       i = 0;
-       while (entry != last_plus_one) {
-               int len;
+                       if (len) {
+                               tnapi->tx_buffers[*entry].fragmented = true;
+                               /* Avoid the 8byte DMA problem */
+                               if (len <= 8) {
+                                       len += TG3_TX_BD_DMA_MAX / 2;
+                                       frag_len = TG3_TX_BD_DMA_MAX / 2;
+                               }
+                       } else
+                               tmp_flag = flags;
 
-               if (i == 0)
-                       len = skb_headlen(skb);
-               else
-                       len = skb_shinfo(skb)->frags[i-1].size;
+                       if (*budget) {
+                               tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
+                                             frag_len, tmp_flag, mss, vlan);
+                               (*budget)--;
+                               *entry = NEXT_TX(*entry);
+                       } else {
+                               hwbug = 1;
+                               break;
+                       }
 
-               pci_unmap_single(tp->pdev,
-                                dma_unmap_addr(&tnapi->tx_buffers[entry],
-                                               mapping),
-                                len, PCI_DMA_TODEVICE);
-               if (i == 0) {
-                       tnapi->tx_buffers[entry].skb = new_skb;
-                       dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
-                                          new_addr);
-               } else {
-                       tnapi->tx_buffers[entry].skb = NULL;
+                       map += frag_len;
                }
-               entry = NEXT_TX(entry);
-               i++;
-       }
 
-       dev_kfree_skb(skb);
-
-       return ret;
-}
-
-static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
-                       dma_addr_t mapping, int len, u32 flags,
-                       u32 mss_and_is_end)
-{
-       struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
-       int is_end = (mss_and_is_end & 0x1);
-       u32 mss = (mss_and_is_end >> 1);
-       u32 vlan_tag = 0;
-
-       if (is_end)
-               flags |= TXD_FLAG_END;
-       if (flags & TXD_FLAG_VLAN) {
-               vlan_tag = flags >> 16;
-               flags &= 0xffff;
+               if (len) {
+                       if (*budget) {
+                               tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
+                                             len, flags, mss, vlan);
+                               (*budget)--;
+                               *entry = NEXT_TX(*entry);
+                       } else {
+                               hwbug = 1;
+                       }
+               }
+       } else {
+               tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
+                             len, flags, mss, vlan);
+               *entry = NEXT_TX(*entry);
        }
-       vlan_tag |= (mss << TXD_MSS_SHIFT);
 
-       txd->addr_hi = ((u64) mapping >> 32);
-       txd->addr_lo = ((u64) mapping & 0xffffffff);
-       txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
-       txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
+       return hwbug;
 }
 
-/* hard_start_xmit for devices that don't have any bugs and
- * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
- */
-static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
-                                 struct net_device *dev)
+static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
 {
-       struct tg3 *tp = netdev_priv(dev);
-       u32 len, entry, base_flags, mss;
-       dma_addr_t mapping;
-       struct tg3_napi *tnapi;
-       struct netdev_queue *txq;
-       unsigned int i, last;
-
-       txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
-       tnapi = &tp->napi[skb_get_queue_mapping(skb)];
-       if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
-               tnapi++;
-
-       /* We are running in BH disabled context with netif_tx_lock
-        * and TX reclaim runs via tp->napi.poll inside of a software
-        * interrupt.  Furthermore, IRQ processing runs lockless so we have
-        * no IRQ context deadlocks to worry about either.  Rejoice!
-        */
-       if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
-               if (!netif_tx_queue_stopped(txq)) {
-                       netif_tx_stop_queue(txq);
-
-                       /* This is a hard error, log it. */
-                       netdev_err(dev,
-                                  "BUG! Tx Ring full when queue awake!\n");
-               }
-               return NETDEV_TX_BUSY;
-       }
-
-       entry = tnapi->tx_prod;
-       base_flags = 0;
-       mss = skb_shinfo(skb)->gso_size;
-       if (mss) {
-               int tcp_opt_len, ip_tcp_len;
-               u32 hdrlen;
-
-               if (skb_header_cloned(skb) &&
-                   pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
-                       dev_kfree_skb(skb);
-                       goto out_unlock;
-               }
-
-               if (skb_is_gso_v6(skb)) {
-                       hdrlen = skb_headlen(skb) - ETH_HLEN;
-               } else {
-                       struct iphdr *iph = ip_hdr(skb);
-
-                       tcp_opt_len = tcp_optlen(skb);
-                       ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
-
-                       iph->check = 0;
-                       iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
-                       hdrlen = ip_tcp_len + tcp_opt_len;
-               }
-
-               if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
-                       mss |= (hdrlen & 0xc) << 12;
-                       if (hdrlen & 0x10)
-                               base_flags |= 0x00000010;
-                       base_flags |= (hdrlen & 0x3e0) << 5;
-               } else
-                       mss |= hdrlen << 9;
-
-               base_flags |= (TXD_FLAG_CPU_PRE_DMA |
-                              TXD_FLAG_CPU_POST_DMA);
-
-               tcp_hdr(skb)->check = 0;
-
-       } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
-               base_flags |= TXD_FLAG_TCPUDP_CSUM;
-       }
+       int i;
+       struct sk_buff *skb;
+       struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
 
-       if (vlan_tx_tag_present(skb))
-               base_flags |= (TXD_FLAG_VLAN |
-                              (vlan_tx_tag_get(skb) << 16));
+       skb = txb->skb;
+       txb->skb = NULL;
 
-       len = skb_headlen(skb);
+       pci_unmap_single(tnapi->tp->pdev,
+                        dma_unmap_addr(txb, mapping),
+                        skb_headlen(skb),
+                        PCI_DMA_TODEVICE);
 
-       /* Queue skb data, a.k.a. the main skb fragment. */
-       mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
-       if (pci_dma_mapping_error(tp->pdev, mapping)) {
-               dev_kfree_skb(skb);
-               goto out_unlock;
+       while (txb->fragmented) {
+               txb->fragmented = false;
+               entry = NEXT_TX(entry);
+               txb = &tnapi->tx_buffers[entry];
        }
 
-       tnapi->tx_buffers[entry].skb = skb;
-       dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
-
-       if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
-           !mss && skb->len > VLAN_ETH_FRAME_LEN)
-               base_flags |= TXD_FLAG_JMB_PKT;
-
-       tg3_set_txd(tnapi, entry, mapping, len, base_flags,
-                   (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
-
-       entry = NEXT_TX(entry);
-
-       /* Now loop through additional data fragments, and queue them. */
-       if (skb_shinfo(skb)->nr_frags > 0) {
-               last = skb_shinfo(skb)->nr_frags - 1;
-               for (i = 0; i <= last; i++) {
-                       skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
-
-                       len = frag->size;
-                       mapping = pci_map_page(tp->pdev,
-                                              frag->page,
-                                              frag->page_offset,
-                                              len, PCI_DMA_TODEVICE);
-                       if (pci_dma_mapping_error(tp->pdev, mapping))
-                               goto dma_error;
+       for (i = 0; i < last; i++) {
+               skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 
-                       tnapi->tx_buffers[entry].skb = NULL;
-                       dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
-                                          mapping);
+               entry = NEXT_TX(entry);
+               txb = &tnapi->tx_buffers[entry];
 
-                       tg3_set_txd(tnapi, entry, mapping, len,
-                                   base_flags, (i == last) | (mss << 1));
+               pci_unmap_page(tnapi->tp->pdev,
+                              dma_unmap_addr(txb, mapping),
+                              frag->size, PCI_DMA_TODEVICE);
 
+               while (txb->fragmented) {
+                       txb->fragmented = false;
                        entry = NEXT_TX(entry);
+                       txb = &tnapi->tx_buffers[entry];
                }
        }
+}
 
-       /* Packets are ready, update Tx producer idx local and on card. */
-       tw32_tx_mbox(tnapi->prodmbox, entry);
+/* Workaround 4GB and 40-bit hardware DMA bugs. */
+static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
+                                      struct sk_buff **pskb,
+                                      u32 *entry, u32 *budget,
+                                      u32 base_flags, u32 mss, u32 vlan)
+{
+       struct tg3 *tp = tnapi->tp;
+       struct sk_buff *new_skb, *skb = *pskb;
+       dma_addr_t new_addr = 0;
+       int ret = 0;
 
-       tnapi->tx_prod = entry;
-       if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
-               netif_tx_stop_queue(txq);
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
+               new_skb = skb_copy(skb, GFP_ATOMIC);
+       else {
+               int more_headroom = 4 - ((unsigned long)skb->data & 3);
 
-               /* netif_tx_stop_queue() must be done before checking
-                * checking tx index in tg3_tx_avail() below, because in
-                * tg3_tx(), we update tx index before checking for
-                * netif_tx_queue_stopped().
-                */
-               smp_mb();
-               if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
-                       netif_tx_wake_queue(txq);
+               new_skb = skb_copy_expand(skb,
+                                         skb_headroom(skb) + more_headroom,
+                                         skb_tailroom(skb), GFP_ATOMIC);
        }
 
-out_unlock:
-       mmiowb();
-
-       return NETDEV_TX_OK;
-
-dma_error:
-       last = i;
-       entry = tnapi->tx_prod;
-       tnapi->tx_buffers[entry].skb = NULL;
-       pci_unmap_single(tp->pdev,
-                        dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
-                        skb_headlen(skb),
-                        PCI_DMA_TODEVICE);
-       for (i = 0; i <= last; i++) {
-               skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
-               entry = NEXT_TX(entry);
-
-               pci_unmap_page(tp->pdev,
-                              dma_unmap_addr(&tnapi->tx_buffers[entry],
-                                             mapping),
-                              frag->size, PCI_DMA_TODEVICE);
+       if (!new_skb) {
+               ret = -1;
+       } else {
+               /* New SKB is guaranteed to be linear. */
+               new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
+                                         PCI_DMA_TODEVICE);
+               /* Make sure the mapping succeeded */
+               if (pci_dma_mapping_error(tp->pdev, new_addr)) {
+                       dev_kfree_skb(new_skb);
+                       ret = -1;
+               } else {
+                       base_flags |= TXD_FLAG_END;
+
+                       tnapi->tx_buffers[*entry].skb = new_skb;
+                       dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
+                                          mapping, new_addr);
+
+                       if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
+                                           new_skb->len, base_flags,
+                                           mss, vlan)) {
+                               tg3_tx_skb_unmap(tnapi, *entry, 0);
+                               dev_kfree_skb(new_skb);
+                               ret = -1;
+                       }
+               }
        }
 
        dev_kfree_skb(skb);
-       return NETDEV_TX_OK;
+       *pskb = new_skb;
+       return ret;
 }
 
-static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
-                                         struct net_device *);
+static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
 
 /* Use GSO to workaround a rare TSO bug that may be triggered when the
  * TSO header is greater than 80 bytes.
@@ -5868,7 +6114,7 @@ static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
                nskb = segs;
                segs = segs->next;
                nskb->next = NULL;
-               tg3_start_xmit_dma_bug(nskb, tp->dev);
+               tg3_start_xmit(nskb, tp->dev);
        } while (segs);
 
 tg3_tso_bug_end:
@@ -5878,30 +6124,32 @@ tg3_tso_bug_end:
 }
 
 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
- * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
+ * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
  */
-static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
-                                         struct net_device *dev)
+static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
 {
        struct tg3 *tp = netdev_priv(dev);
-       u32 len, entry, base_flags, mss;
-       int would_hit_hwbug;
+       u32 len, entry, base_flags, mss, vlan = 0;
+       u32 budget;
+       int i = -1, would_hit_hwbug;
        dma_addr_t mapping;
        struct tg3_napi *tnapi;
        struct netdev_queue *txq;
-       unsigned int i, last;
+       unsigned int last;
 
        txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
        tnapi = &tp->napi[skb_get_queue_mapping(skb)];
-       if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
+       if (tg3_flag(tp, ENABLE_TSS))
                tnapi++;
 
+       budget = tg3_tx_avail(tnapi);
+
        /* We are running in BH disabled context with netif_tx_lock
         * and TX reclaim runs via tp->napi.poll inside of a software
         * interrupt.  Furthermore, IRQ processing runs lockless so we have
         * no IRQ context deadlocks to worry about either.  Rejoice!
         */
-       if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
+       if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
                if (!netif_tx_queue_stopped(txq)) {
                        netif_tx_stop_queue(txq);
 
@@ -5944,13 +6192,15 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
                }
 
                if (unlikely((ETH_HLEN + hdr_len) > 80) &&
-                            (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
+                   tg3_flag(tp, TSO_BUG))
                        return tg3_tso_bug(tp, skb);
 
                base_flags |= (TXD_FLAG_CPU_PRE_DMA |
                               TXD_FLAG_CPU_POST_DMA);
 
-               if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
+               if (tg3_flag(tp, HW_TSO_1) ||
+                   tg3_flag(tp, HW_TSO_2) ||
+                   tg3_flag(tp, HW_TSO_3)) {
                        tcp_hdr(skb)->check = 0;
                        base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
                } else
@@ -5959,14 +6209,14 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
                                                                 IPPROTO_TCP,
                                                                 0);
 
-               if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
+               if (tg3_flag(tp, HW_TSO_3)) {
                        mss |= (hdr_len & 0xc) << 12;
                        if (hdr_len & 0x10)
                                base_flags |= 0x00000010;
                        base_flags |= (hdr_len & 0x3e0) << 5;
-               } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
+               } else if (tg3_flag(tp, HW_TSO_2))
                        mss |= hdr_len << 9;
-               else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
+               else if (tg3_flag(tp, HW_TSO_1) ||
                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
                        if (tcp_opt_len || iph->ihl > 5) {
                                int tsflags;
@@ -5984,11 +6234,12 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
                }
        }
 
-       if (vlan_tx_tag_present(skb))
-               base_flags |= (TXD_FLAG_VLAN |
-                              (vlan_tx_tag_get(skb) << 16));
+       if (vlan_tx_tag_present(skb)) {
+               base_flags |= TXD_FLAG_VLAN;
+               vlan = vlan_tx_tag_get(skb);
+       }
 
-       if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
+       if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
            !mss && skb->len > VLAN_ETH_FRAME_LEN)
                base_flags |= TXD_FLAG_JMB_PKT;
 
@@ -6005,27 +6256,23 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
 
        would_hit_hwbug = 0;
 
-       if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
-               would_hit_hwbug = 1;
-
-       if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
-           tg3_4g_overflow_test(mapping, len))
-               would_hit_hwbug = 1;
-
-       if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
-           tg3_40bit_overflow_test(tp, mapping, len))
+       if (tg3_flag(tp, 5701_DMA_BUG))
                would_hit_hwbug = 1;
 
-       if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
+       if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
+                         ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
+                           mss, vlan))
                would_hit_hwbug = 1;
 
-       tg3_set_txd(tnapi, entry, mapping, len, base_flags,
-                   (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
-
-       entry = NEXT_TX(entry);
-
        /* Now loop through additional data fragments, and queue them. */
        if (skb_shinfo(skb)->nr_frags > 0) {
+               u32 tmp_mss = mss;
+
+               if (!tg3_flag(tp, HW_TSO_1) &&
+                   !tg3_flag(tp, HW_TSO_2) &&
+                   !tg3_flag(tp, HW_TSO_3))
+                       tmp_mss = 0;
+
                last = skb_shinfo(skb)->nr_frags - 1;
                for (i = 0; i <= last; i++) {
                        skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
@@ -6042,46 +6289,29 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
                        if (pci_dma_mapping_error(tp->pdev, mapping))
                                goto dma_error;
 
-                       if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
-                           len <= 8)
+                       if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
+                                           len, base_flags |
+                                           ((i == last) ? TXD_FLAG_END : 0),
+                                           tmp_mss, vlan))
                                would_hit_hwbug = 1;
-
-                       if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
-                           tg3_4g_overflow_test(mapping, len))
-                               would_hit_hwbug = 1;
-
-                       if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
-                           tg3_40bit_overflow_test(tp, mapping, len))
-                               would_hit_hwbug = 1;
-
-                       if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
-                               tg3_set_txd(tnapi, entry, mapping, len,
-                                           base_flags, (i == last)|(mss << 1));
-                       else
-                               tg3_set_txd(tnapi, entry, mapping, len,
-                                           base_flags, (i == last));
-
-                       entry = NEXT_TX(entry);
                }
        }
 
        if (would_hit_hwbug) {
-               u32 last_plus_one = entry;
-               u32 start;
-
-               start = entry - 1 - skb_shinfo(skb)->nr_frags;
-               start &= (TG3_TX_RING_SIZE - 1);
+               tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
 
                /* If the workaround fails due to memory/mapping
                 * failure, silently drop this packet.
                 */
-               if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
-                                               &start, base_flags, mss))
+               entry = tnapi->tx_prod;
+               budget = tg3_tx_avail(tnapi);
+               if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
+                                               base_flags, mss, vlan))
                        goto out_unlock;
-
-               entry = start;
        }
 
+       skb_tx_timestamp(skb);
+
        /* Packets are ready, update Tx producer idx local and on card. */
        tw32_tx_mbox(tnapi->prodmbox, entry);
 
@@ -6105,25 +6335,66 @@ out_unlock:
        return NETDEV_TX_OK;
 
 dma_error:
-       last = i;
-       entry = tnapi->tx_prod;
-       tnapi->tx_buffers[entry].skb = NULL;
-       pci_unmap_single(tp->pdev,
-                        dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
-                        skb_headlen(skb),
-                        PCI_DMA_TODEVICE);
-       for (i = 0; i <= last; i++) {
-               skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
-               entry = NEXT_TX(entry);
+       tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
+       dev_kfree_skb(skb);
+       tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
+       return NETDEV_TX_OK;
+}
 
-               pci_unmap_page(tp->pdev,
-                              dma_unmap_addr(&tnapi->tx_buffers[entry],
-                                             mapping),
-                              frag->size, PCI_DMA_TODEVICE);
+static void tg3_set_loopback(struct net_device *dev, u32 features)
+{
+       struct tg3 *tp = netdev_priv(dev);
+
+       if (features & NETIF_F_LOOPBACK) {
+               if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
+                       return;
+
+               /*
+                * Clear MAC_MODE_HALF_DUPLEX or you won't get packets back in
+                * loopback mode if Half-Duplex mode was negotiated earlier.
+                */
+               tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
+
+               /* Enable internal MAC loopback mode */
+               tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
+               spin_lock_bh(&tp->lock);
+               tw32(MAC_MODE, tp->mac_mode);
+               netif_carrier_on(tp->dev);
+               spin_unlock_bh(&tp->lock);
+               netdev_info(dev, "Internal MAC loopback mode enabled.\n");
+       } else {
+               if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
+                       return;
+
+               /* Disable internal MAC loopback mode */
+               tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
+               spin_lock_bh(&tp->lock);
+               tw32(MAC_MODE, tp->mac_mode);
+               /* Force link status check */
+               tg3_setup_phy(tp, 1);
+               spin_unlock_bh(&tp->lock);
+               netdev_info(dev, "Internal MAC loopback mode disabled.\n");
        }
+}
 
-       dev_kfree_skb(skb);
-       return NETDEV_TX_OK;
+static u32 tg3_fix_features(struct net_device *dev, u32 features)
+{
+       struct tg3 *tp = netdev_priv(dev);
+
+       if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
+               features &= ~NETIF_F_ALL_TSO;
+
+       return features;
+}
+
+static int tg3_set_features(struct net_device *dev, u32 features)
+{
+       u32 changed = dev->features ^ features;
+
+       if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
+               tg3_set_loopback(dev, features);
+
+       return 0;
 }
 
 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
@@ -6132,16 +6403,18 @@ static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
        dev->mtu = new_mtu;
 
        if (new_mtu > ETH_DATA_LEN) {
-               if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
-                       tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
-                       ethtool_op_set_tso(dev, 0);
+               if (tg3_flag(tp, 5780_CLASS)) {
+                       netdev_update_features(dev);
+                       tg3_flag_clear(tp, TSO_CAPABLE);
                } else {
-                       tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
+                       tg3_flag_set(tp, JUMBO_RING_ENABLE);
                }
        } else {
-               if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
-                       tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
-               tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
+               if (tg3_flag(tp, 5780_CLASS)) {
+                       tg3_flag_set(tp, TSO_CAPABLE);
+                       netdev_update_features(dev);
+               }
+               tg3_flag_clear(tp, JUMBO_RING_ENABLE);
        }
 }
 
@@ -6195,7 +6468,7 @@ static void tg3_rx_prodring_free(struct tg3 *tp,
                        tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
                                        tp->rx_pkt_map_sz);
 
-               if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
+               if (tg3_flag(tp, JUMBO_CAPABLE)) {
                        for (i = tpr->rx_jmb_cons_idx;
                             i != tpr->rx_jmb_prod_idx;
                             i = (i + 1) & tp->rx_jmb_ring_mask) {
@@ -6211,8 +6484,7 @@ static void tg3_rx_prodring_free(struct tg3 *tp,
                tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
                                tp->rx_pkt_map_sz);
 
-       if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
-           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
+       if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
                for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
                        tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
                                        TG3_RX_JMB_MAP_SZ);
@@ -6249,7 +6521,7 @@ static int tg3_rx_prodring_alloc(struct tg3 *tp,
        memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
 
        rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
-       if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
+       if (tg3_flag(tp, 5780_CLASS) &&
            tp->dev->mtu > ETH_DATA_LEN)
                rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
        tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
@@ -6282,13 +6554,12 @@ static int tg3_rx_prodring_alloc(struct tg3 *tp,
                }
        }
 
-       if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ||
-           (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
+       if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
                goto done;
 
        memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
 
-       if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
+       if (!tg3_flag(tp, JUMBO_RING_ENABLE))
                goto done;
 
        for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
@@ -6357,8 +6628,7 @@ static int tg3_rx_prodring_init(struct tg3 *tp,
        if (!tpr->rx_std)
                goto err_out;
 
-       if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
-           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
+       if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
                tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
                                              GFP_KERNEL);
                if (!tpr->rx_jmb_buffers)
@@ -6398,35 +6668,13 @@ static void tg3_free_rings(struct tg3 *tp)
                if (!tnapi->tx_buffers)
                        continue;
 
-               for (i = 0; i < TG3_TX_RING_SIZE; ) {
-                       struct ring_info *txp;
-                       struct sk_buff *skb;
-                       unsigned int k;
+               for (i = 0; i < TG3_TX_RING_SIZE; i++) {
+                       struct sk_buff *skb = tnapi->tx_buffers[i].skb;
 
-                       txp = &tnapi->tx_buffers[i];
-                       skb = txp->skb;
-
-                       if (skb == NULL) {
-                               i++;
+                       if (!skb)
                                continue;
-                       }
-
-                       pci_unmap_single(tp->pdev,
-                                        dma_unmap_addr(txp, mapping),
-                                        skb_headlen(skb),
-                                        PCI_DMA_TODEVICE);
-                       txp->skb = NULL;
-
-                       i++;
 
-                       for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
-                               txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
-                               pci_unmap_page(tp->pdev,
-                                              dma_unmap_addr(txp, mapping),
-                                              skb_shinfo(skb)->frags[k].size,
-                                              PCI_DMA_TODEVICE);
-                               i++;
-                       }
+                       tg3_tx_skb_unmap(tnapi, i, skb_shinfo(skb)->nr_frags);
 
                        dev_kfree_skb_any(skb);
                }
@@ -6556,11 +6804,11 @@ static int tg3_alloc_consistent(struct tg3 *tp)
                /* If multivector TSS is enabled, vector 0 does not handle
                 * tx interrupts.  Don't allocate any resources for it.
                 */
-               if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
-                   (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
-                       tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
-                                                   TG3_TX_RING_SIZE,
-                                                   GFP_KERNEL);
+               if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
+                   (i && tg3_flag(tp, ENABLE_TSS))) {
+                       tnapi->tx_buffers = kzalloc(
+                                              sizeof(struct tg3_tx_ring_info) *
+                                              TG3_TX_RING_SIZE, GFP_KERNEL);
                        if (!tnapi->tx_buffers)
                                goto err_out;
 
@@ -6597,7 +6845,7 @@ static int tg3_alloc_consistent(struct tg3 *tp)
                 * If multivector RSS is enabled, vector 0 does not handle
                 * rx or tx interrupts.  Don't allocate any resources for it.
                 */
-               if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
+               if (!i && tg3_flag(tp, ENABLE_RSS))
                        continue;
 
                tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
@@ -6627,7 +6875,7 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int
        unsigned int i;
        u32 val;
 
-       if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
+       if (tg3_flag(tp, 5705_PLUS)) {
                switch (ofs) {
                case RCVLSC_MODE:
                case DMAC_MODE:
@@ -6737,7 +6985,7 @@ static void tg3_ape_send_event(struct tg3 *tp, u32 event)
        u32 apedata;
 
        /* NCSI does not support APE events */
-       if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
+       if (tg3_flag(tp, APE_HAS_NCSI))
                return;
 
        apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
@@ -6776,7 +7024,7 @@ static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
        u32 event;
        u32 apedata;
 
-       if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
+       if (!tg3_flag(tp, ENABLE_APE))
                return;
 
        switch (kind) {
@@ -6805,7 +7053,7 @@ static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
                tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
 
                if (device_may_wakeup(&tp->pdev->dev) &&
-                   (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
+                   tg3_flag(tp, WOL_ENABLE)) {
                        tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
                                            TG3_APE_HOST_WOL_SPEED_AUTO);
                        apedata = TG3_APE_HOST_DRVR_STATE_WOL;
@@ -6834,7 +7082,7 @@ static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
        tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
                      NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
 
-       if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
+       if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
                switch (kind) {
                case RESET_KIND_INIT:
                        tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
@@ -6864,7 +7112,7 @@ static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
 /* tp->lock is held. */
 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
 {
-       if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
+       if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
                switch (kind) {
                case RESET_KIND_INIT:
                        tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
@@ -6888,7 +7136,7 @@ static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
 /* tp->lock is held. */
 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
 {
-       if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
+       if (tg3_flag(tp, ENABLE_ASF)) {
                switch (kind) {
                case RESET_KIND_INIT:
                        tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
@@ -6939,9 +7187,8 @@ static int tg3_poll_fw(struct tg3 *tp)
         * of the above loop as an error, but do report the lack of
         * running firmware once.
         */
-       if (i >= 100000 &&
-           !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
-               tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
+       if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
+               tg3_flag_set(tp, NO_FWARE_REPORTED);
 
                netdev_info(tp->dev, "No firmware running\n");
        }
@@ -6974,10 +7221,10 @@ static void tg3_restore_pci_state(struct tg3 *tp)
        /* Set MAX PCI retry to zero. */
        val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
        if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
-           (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
+           tg3_flag(tp, PCIX_MODE))
                val |= PCISTATE_RETRY_SAME_DMA;
        /* Allow reads and writes to the APE register and memory space. */
-       if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
+       if (tg3_flag(tp, ENABLE_APE))
                val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
                       PCISTATE_ALLOW_APE_SHMEM_WR |
                       PCISTATE_ALLOW_APE_PSPACE_WR;
@@ -6986,7 +7233,7 @@ static void tg3_restore_pci_state(struct tg3 *tp)
        pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
-               if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
+               if (tg3_flag(tp, PCI_EXPRESS))
                        pcie_set_readrq(tp->pdev, tp->pcie_readrq);
                else {
                        pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
@@ -6997,7 +7244,7 @@ static void tg3_restore_pci_state(struct tg3 *tp)
        }
 
        /* Make sure PCI-X relaxed ordering bit is clear. */
-       if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
+       if (tg3_flag(tp, PCIX_MODE)) {
                u16 pcix_cmd;
 
                pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
@@ -7007,12 +7254,12 @@ static void tg3_restore_pci_state(struct tg3 *tp)
                                      pcix_cmd);
        }
 
-       if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
+       if (tg3_flag(tp, 5780_CLASS)) {
 
                /* Chip reset on 5780 will reset MSI enable bit,
                 * so need to restore it.
                 */
-               if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
+               if (tg3_flag(tp, USING_MSI)) {
                        u16 ctrl;
 
                        pci_read_config_word(tp->pdev,
@@ -7052,7 +7299,7 @@ static int tg3_chip_reset(struct tg3 *tp)
        tg3_save_pci_state(tp);
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
-           (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
+           tg3_flag(tp, 5755_PLUS))
                tw32(GRC_FASTBOOT_PC, 0);
 
        /*
@@ -7071,7 +7318,7 @@ static int tg3_chip_reset(struct tg3 *tp)
         * at this time, but the irq handler may still be called due to irq
         * sharing or irqpoll.
         */
-       tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
+       tg3_flag_set(tp, CHIP_RESETTING);
        for (i = 0; i < tp->irq_cnt; i++) {
                struct tg3_napi *tnapi = &tp->napi[i];
                if (tnapi->hw_status) {
@@ -7094,10 +7341,10 @@ static int tg3_chip_reset(struct tg3 *tp)
        /* do the reset */
        val = GRC_MISC_CFG_CORECLK_RESET;
 
-       if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
+       if (tg3_flag(tp, PCI_EXPRESS)) {
                /* Force PCIe 1.0a mode */
                if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
-                   !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
+                   !tg3_flag(tp, 57765_PLUS) &&
                    tr32(TG3_PCIE_PHY_TSTCTL) ==
                    (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
                        tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
@@ -7115,8 +7362,7 @@ static int tg3_chip_reset(struct tg3 *tp)
        }
 
        /* Manage gphy power for all CPMU absent PCIe devices. */
-       if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
-           !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
+       if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
                val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
 
        tw32(GRC_MISC_CFG, val);
@@ -7149,7 +7395,7 @@ static int tg3_chip_reset(struct tg3 *tp)
 
        udelay(120);
 
-       if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
+       if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) {
                u16 val16;
 
                if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
@@ -7167,7 +7413,7 @@ static int tg3_chip_reset(struct tg3 *tp)
 
                /* Clear the "no snoop" and "relaxed ordering" bits. */
                pci_read_config_word(tp->pdev,
-                                    tp->pcie_cap + PCI_EXP_DEVCTL,
+                                    pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
                                     &val16);
                val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
                           PCI_EXP_DEVCTL_NOSNOOP_EN);
@@ -7175,17 +7421,17 @@ static int tg3_chip_reset(struct tg3 *tp)
                 * Older PCIe devices only support the 128 byte
                 * MPS setting.  Enforce the restriction.
                 */
-               if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
+               if (!tg3_flag(tp, CPMU_PRESENT))
                        val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
                pci_write_config_word(tp->pdev,
-                                     tp->pcie_cap + PCI_EXP_DEVCTL,
+                                     pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
                                      val16);
 
                pcie_set_readrq(tp->pdev, tp->pcie_readrq);
 
                /* Clear error status */
                pci_write_config_word(tp->pdev,
-                                     tp->pcie_cap + PCI_EXP_DEVSTA,
+                                     pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA,
                                      PCI_EXP_DEVSTA_CED |
                                      PCI_EXP_DEVSTA_NFED |
                                      PCI_EXP_DEVSTA_FED |
@@ -7194,10 +7440,11 @@ static int tg3_chip_reset(struct tg3 *tp)
 
        tg3_restore_pci_state(tp);
 
-       tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
+       tg3_flag_clear(tp, CHIP_RESETTING);
+       tg3_flag_clear(tp, ERROR_PROCESSED);
 
        val = 0;
-       if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
+       if (tg3_flag(tp, 5780_CLASS))
                val = tr32(MEMARB_MODE);
        tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
 
@@ -7222,16 +7469,11 @@ static int tg3_chip_reset(struct tg3 *tp)
                tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
        }
 
-       if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
-               tp->mac_mode = MAC_MODE_APE_TX_EN |
-                              MAC_MODE_APE_RX_EN |
-                              MAC_MODE_TDE_ENABLE;
-
        if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
-               tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
+               tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
                val = tp->mac_mode;
        } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
-               tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
+               tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
                val = tp->mac_mode;
        } else
                val = 0;
@@ -7247,28 +7489,33 @@ static int tg3_chip_reset(struct tg3 *tp)
 
        tg3_mdio_start(tp);
 
-       if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
+       if (tg3_flag(tp, PCI_EXPRESS) &&
            tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
-           !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
+           !tg3_flag(tp, 57765_PLUS)) {
                val = tr32(0x7c00);
 
                tw32(0x7c00, val | (1 << 25));
        }
 
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
+               val = tr32(TG3_CPMU_CLCK_ORIDE);
+               tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
+       }
+
        /* Reprobe ASF enable state.  */
-       tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
-       tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
+       tg3_flag_clear(tp, ENABLE_ASF);
+       tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
        tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
        if (val == NIC_SRAM_DATA_SIG_MAGIC) {
                u32 nic_cfg;
 
                tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
                if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
-                       tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
+                       tg3_flag_set(tp, ENABLE_ASF);
                        tp->last_event_jiffies = jiffies;
-                       if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
-                               tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
+                       if (tg3_flag(tp, 5750_PLUS))
+                               tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
                }
        }
 
@@ -7278,8 +7525,7 @@ static int tg3_chip_reset(struct tg3 *tp)
 /* tp->lock is held. */
 static void tg3_stop_fw(struct tg3 *tp)
 {
-       if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
-          !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
+       if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
                /* Wait for RX cpu to ACK the previous event. */
                tg3_wait_for_event_ack(tp);
 
@@ -7325,8 +7571,7 @@ static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
 {
        int i;
 
-       BUG_ON(offset == TX_CPU_BASE &&
-           (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
+       BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
                u32 val = tr32(GRC_VCPU_EXT_CTRL);
@@ -7361,7 +7606,7 @@ static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
        }
 
        /* Clear firmware's nvram arbitration. */
-       if (tp->tg3_flags & TG3_FLAG_NVRAM)
+       if (tg3_flag(tp, NVRAM))
                tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
        return 0;
 }
@@ -7379,15 +7624,14 @@ static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_b
        int err, lock_err, i;
        void (*write_op)(struct tg3 *, u32, u32);
 
-       if (cpu_base == TX_CPU_BASE &&
-           (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
+       if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
                netdev_err(tp->dev,
                           "%s: Trying to load TX cpu firmware which is 5705\n",
                           __func__);
                return -EINVAL;
        }
 
-       if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
+       if (tg3_flag(tp, 5705_PLUS))
                write_op = tg3_write_mem;
        else
                write_op = tg3_write_indirect_reg32;
@@ -7473,8 +7717,6 @@ static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
        return 0;
 }
 
-/* 5705 needs a special version of the TSO firmware.  */
-
 /* tp->lock is held. */
 static int tg3_load_tso_firmware(struct tg3 *tp)
 {
@@ -7483,7 +7725,9 @@ static int tg3_load_tso_firmware(struct tg3 *tp)
        unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
        int err, i;
 
-       if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
+       if (tg3_flag(tp, HW_TSO_1) ||
+           tg3_flag(tp, HW_TSO_2) ||
+           tg3_flag(tp, HW_TSO_3))
                return 0;
 
        fw_data = (void *)tp->fw->data;
@@ -7552,7 +7796,7 @@ static int tg3_set_mac_addr(struct net_device *dev, void *p)
        if (!netif_running(dev))
                return 0;
 
-       if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
+       if (tg3_flag(tp, ENABLE_ASF)) {
                u32 addr0_high, addr0_low, addr1_high, addr1_low;
 
                addr0_high = tr32(MAC_ADDR_0_HIGH);
@@ -7587,7 +7831,7 @@ static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
                      (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
                       maxlen_flags);
 
-       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
+       if (!tg3_flag(tp, 5705_PLUS))
                tg3_write_mem(tp,
                              (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
                              nic_addr);
@@ -7598,7 +7842,7 @@ static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
 {
        int i;
 
-       if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
+       if (!tg3_flag(tp, ENABLE_TSS)) {
                tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
                tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
                tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
@@ -7608,7 +7852,7 @@ static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
                tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
        }
 
-       if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
+       if (!tg3_flag(tp, ENABLE_RSS)) {
                tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
                tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
                tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
@@ -7618,7 +7862,7 @@ static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
                tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
        }
 
-       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
+       if (!tg3_flag(tp, 5705_PLUS)) {
                u32 val = ec->stats_block_coalesce_usecs;
 
                tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
@@ -7640,7 +7884,7 @@ static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
                reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
                tw32(reg, ec->rx_max_coalesced_frames_irq);
 
-               if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
+               if (tg3_flag(tp, ENABLE_TSS)) {
                        reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
                        tw32(reg, ec->tx_coalesce_usecs);
                        reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
@@ -7655,7 +7899,7 @@ static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
                tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
                tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
 
-               if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
+               if (tg3_flag(tp, ENABLE_TSS)) {
                        tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
                        tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
                        tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
@@ -7671,10 +7915,9 @@ static void tg3_rings_reset(struct tg3 *tp)
        struct tg3_napi *tnapi = &tp->napi[0];
 
        /* Disable all transmit rings but the first. */
-       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
+       if (!tg3_flag(tp, 5705_PLUS))
                limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
-       else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-                GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
+       else if (tg3_flag(tp, 5717_PLUS))
                limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
        else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
                limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
@@ -7688,10 +7931,9 @@ static void tg3_rings_reset(struct tg3 *tp)
 
 
        /* Disable all receive return rings but the first. */
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
+       if (tg3_flag(tp, 5717_PLUS))
                limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
-       else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
+       else if (!tg3_flag(tp, 5705_PLUS))
                limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
        else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
                 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
@@ -7706,18 +7948,24 @@ static void tg3_rings_reset(struct tg3 *tp)
 
        /* Disable interrupts */
        tw32_mailbox_f(tp->napi[0].int_mbox, 1);
+       tp->napi[0].chk_msi_cnt = 0;
+       tp->napi[0].last_rx_cons = 0;
+       tp->napi[0].last_tx_cons = 0;
 
        /* Zero mailbox registers. */
-       if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
+       if (tg3_flag(tp, SUPPORT_MSIX)) {
                for (i = 1; i < tp->irq_max; i++) {
                        tp->napi[i].tx_prod = 0;
                        tp->napi[i].tx_cons = 0;
-                       if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
+                       if (tg3_flag(tp, ENABLE_TSS))
                                tw32_mailbox(tp->napi[i].prodmbox, 0);
                        tw32_rx_mbox(tp->napi[i].consmbox, 0);
                        tw32_mailbox_f(tp->napi[i].int_mbox, 1);
+                       tp->napi[0].chk_msi_cnt = 0;
+                       tp->napi[i].last_rx_cons = 0;
+                       tp->napi[i].last_tx_cons = 0;
                }
-               if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
+               if (!tg3_flag(tp, ENABLE_TSS))
                        tw32_mailbox(tp->napi[0].prodmbox, 0);
        } else {
                tp->napi[0].tx_prod = 0;
@@ -7727,7 +7975,7 @@ static void tg3_rings_reset(struct tg3 *tp)
        }
 
        /* Make sure the NIC-based send BD rings are disabled. */
-       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
+       if (!tg3_flag(tp, 5705_PLUS)) {
                u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
                for (i = 0; i < 16; i++)
                        tw32_tx_mbox(mbox + i * 8, 0);
@@ -7787,6 +8035,47 @@ static void tg3_rings_reset(struct tg3 *tp)
        }
 }
 
+static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
+{
+       u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
+
+       if (!tg3_flag(tp, 5750_PLUS) ||
+           tg3_flag(tp, 5780_CLASS) ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+               bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
+       else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
+                GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
+               bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
+       else
+               bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
+
+       nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
+       host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
+
+       val = min(nic_rep_thresh, host_rep_thresh);
+       tw32(RCVBDI_STD_THRESH, val);
+
+       if (tg3_flag(tp, 57765_PLUS))
+               tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
+
+       if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
+               return;
+
+       if (!tg3_flag(tp, 5705_PLUS))
+               bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
+       else
+               bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717;
+
+       host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
+
+       val = min(bdcache_maxcnt / 2, host_rep_thresh);
+       tw32(RCVBDI_JUMBO_THRESH, val);
+
+       if (tg3_flag(tp, 57765_PLUS))
+               tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
+}
+
 /* tp->lock is held. */
 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
 {
@@ -7800,7 +8089,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
 
        tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
 
-       if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
+       if (tg3_flag(tp, INIT_COMPLETE))
                tg3_abort_hw(tp, 1);
 
        /* Enable MAC control of LPI */
@@ -7820,7 +8109,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
                        val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
 
-               if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
+               if (tg3_flag(tp, ENABLE_APE))
                        val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
 
                tw32_f(TG3_CPMU_EEE_MODE, val);
@@ -7879,7 +8168,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
        }
 
-       if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
+       if (tg3_flag(tp, L1PLLPD_EN)) {
                u32 grc_mode = tr32(GRC_MODE);
 
                /* Access the lower 1K of PL PCIE block registers. */
@@ -7909,6 +8198,22 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                        tw32(GRC_MODE, grc_mode);
                }
 
+               if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
+                       u32 grc_mode = tr32(GRC_MODE);
+
+                       /* Access the lower 1K of DL PCIE block registers. */
+                       val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
+                       tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
+
+                       val = tr32(TG3_PCIE_TLDLPL_PORT +
+                                  TG3_PCIE_DL_LO_FTSMAX);
+                       val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
+                       tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
+                            val | TG3_PCIE_DL_LO_FTSMAX_VAL);
+
+                       tw32(GRC_MODE, grc_mode);
+               }
+
                val = tr32(TG3_CPMU_LSPD_10MB_CLK);
                val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
                val |= CPMU_LSPD_10MB_MACCLK_6_25;
@@ -7920,20 +8225,20 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
         * other revision.  But do not set this on PCI Express
         * chips and don't even touch the clocks if the CPMU is present.
         */
-       if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
-               if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
+       if (!tg3_flag(tp, CPMU_PRESENT)) {
+               if (!tg3_flag(tp, PCI_EXPRESS))
                        tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
                tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
        }
 
        if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
-           (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
+           tg3_flag(tp, PCIX_MODE)) {
                val = tr32(TG3PCI_PCISTATE);
                val |= PCISTATE_RETRY_SAME_DMA;
                tw32(TG3PCI_PCISTATE, val);
        }
 
-       if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
+       if (tg3_flag(tp, ENABLE_APE)) {
                /* Allow reads and writes to the
                 * APE register and memory space.
                 */
@@ -7960,11 +8265,14 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        if (err)
                return err;
 
-       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
+       if (tg3_flag(tp, 57765_PLUS)) {
                val = tr32(TG3PCI_DMA_RW_CTRL) &
                      ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
                if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
                        val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
+                   GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
+                       val |= DMA_RWCTRL_TAGGED_STAT_WA;
                tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
        } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
                   GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
@@ -7999,7 +8307,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        tw32(GRC_MISC_CFG, val);
 
        /* Initialize MBUF/DESC pool. */
-       if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
+       if (tg3_flag(tp, 5750_PLUS)) {
                /* Do nothing.  */
        } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
                tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
@@ -8009,7 +8317,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                        tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
                tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
                tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
-       } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
+       } else if (tg3_flag(tp, TSO_CAPABLE)) {
                int fw_len;
 
                fw_len = tp->fw_len;
@@ -8043,6 +8351,10 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
                val |= BUFMGR_MODE_NO_TX_UNDERRUN;
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+           tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
+           tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
+               val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
        tw32(BUFMGR_MODE, val);
        for (i = 0; i < 2000; i++) {
                if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
@@ -8054,21 +8366,10 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                return -ENODEV;
        }
 
-       /* Setup replenish threshold. */
-       val = tp->rx_pending / 8;
-       if (val == 0)
-               val = 1;
-       else if (val > tp->rx_std_max_post)
-               val = tp->rx_std_max_post;
-       else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
-               if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
-                       tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
+       if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
+               tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
 
-               if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
-                       val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
-       }
-
-       tw32(RCVBDI_STD_THRESH, val);
+       tg3_setup_rxbd_thresholds(tp);
 
        /* Initialize TG3_BDINFO's at:
         *  RCVDBDI_STD_BD:     standard eth size rx ring
@@ -8091,34 +8392,31 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
             ((u64) tpr->rx_std_mapping >> 32));
        tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
             ((u64) tpr->rx_std_mapping & 0xffffffff));
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
-           GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
+       if (!tg3_flag(tp, 5717_PLUS))
                tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
                     NIC_SRAM_RX_BUFFER_DESC);
 
        /* Disable the mini ring */
-       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
+       if (!tg3_flag(tp, 5705_PLUS))
                tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
                     BDINFO_FLAGS_DISABLED);
 
        /* Program the jumbo buffer descriptor ring control
         * blocks on those devices that have them.
         */
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
-           ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
-           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))) {
-               /* Setup replenish threshold. */
-               tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
+       if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
+           (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
 
-               if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
+               if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
                        tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
                             ((u64) tpr->rx_jmb_mapping >> 32));
                        tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
                             ((u64) tpr->rx_jmb_mapping & 0xffffffff));
+                       val = TG3_RX_JMB_RING_SIZE(tp) <<
+                             BDINFO_FLAGS_MAXLEN_SHIFT;
                        tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
-                            (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
-                            BDINFO_FLAGS_USE_EXT_RECV);
-                       if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
+                            val | BDINFO_FLAGS_USE_EXT_RECV);
+                       if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
                            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
                                tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
                                     NIC_SRAM_RX_JUMBO_BUFFER_DESC);
@@ -8127,32 +8425,27 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                             BDINFO_FLAGS_DISABLED);
                }
 
-               if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
+               if (tg3_flag(tp, 57765_PLUS)) {
                        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
-                               val = RX_STD_MAX_SIZE_5705;
+                               val = TG3_RX_STD_MAX_SIZE_5700;
                        else
-                               val = RX_STD_MAX_SIZE_5717;
+                               val = TG3_RX_STD_MAX_SIZE_5717;
                        val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
                        val |= (TG3_RX_STD_DMA_SZ << 2);
                } else
                        val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
        } else
-               val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
+               val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
 
        tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
 
        tpr->rx_std_prod_idx = tp->rx_pending;
        tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
 
-       tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
-                         tp->rx_jumbo_pending : 0;
+       tpr->rx_jmb_prod_idx =
+               tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
        tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
 
-       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
-               tw32(STD_REPLENISH_LWM, 32);
-               tw32(JMB_REPLENISH_LWM, 16);
-       }
-
        tg3_rings_reset(tp);
 
        /* Initialize MAC address and backoff seed. */
@@ -8165,10 +8458,16 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        /* The slot time is changed by tg3_setup_phy if we
         * run at gigabit with half duplex.
         */
-       tw32(MAC_TX_LENGTHS,
-            (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
-            (6 << TX_LENGTHS_IPG_SHIFT) |
-            (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
+       val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
+             (6 << TX_LENGTHS_IPG_SHIFT) |
+             (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
+               val |= tr32(MAC_TX_LENGTHS) &
+                      (TX_LENGTHS_JMB_FRM_LEN_MSK |
+                       TX_LENGTHS_CNT_DWN_VAL_MSK);
+
+       tw32(MAC_TX_LENGTHS, val);
 
        /* Receive rules. */
        tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
@@ -8195,33 +8494,39 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
            tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
-               if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
+               if (tg3_flag(tp, TSO_CAPABLE) &&
                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
                        rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
                } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
-                          !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
+                          !tg3_flag(tp, IS_5788)) {
                        rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
                }
        }
 
-       if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
+       if (tg3_flag(tp, PCI_EXPRESS))
                rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
 
-       if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
+       if (tg3_flag(tp, HW_TSO_1) ||
+           tg3_flag(tp, HW_TSO_2) ||
+           tg3_flag(tp, HW_TSO_3))
                rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
 
-       if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
+       if (tg3_flag(tp, 57765_PLUS) ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
                rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
 
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
+               rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
+
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
-           (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
+           tg3_flag(tp, 57765_PLUS)) {
                val = tr32(TG3_RDMA_RSRVCTRL_REG);
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
+                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
                        val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
                                 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
                                 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
@@ -8233,7 +8538,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                     val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
        }
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
                val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
                tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
                     TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
@@ -8241,12 +8547,12 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        }
 
        /* Receive/send statistics. */
-       if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
+       if (tg3_flag(tp, 5750_PLUS)) {
                val = tr32(RCVLPC_STATS_ENABLE);
                val &= ~RCVLPC_STATSENAB_DACK_FIX;
                tw32(RCVLPC_STATS_ENABLE, val);
        } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
-                  (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
+                  tg3_flag(tp, TSO_CAPABLE)) {
                val = tr32(RCVLPC_STATS_ENABLE);
                val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
                tw32(RCVLPC_STATS_ENABLE, val);
@@ -8269,7 +8575,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
 
        __tg3_set_coalesce(tp, &tp->coal);
 
-       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
+       if (!tg3_flag(tp, 5705_PLUS)) {
                /* Status/statistics block address.  See tg3_timer,
                 * the tg3_periodic_fetch_stats call there, and
                 * tg3_get_stats to see how this works for 5705/5750 chips.
@@ -8295,7 +8601,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
 
        tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
        tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
-       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
+       if (!tg3_flag(tp, 5705_PLUS))
                tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
 
        if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
@@ -8305,13 +8611,12 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                udelay(10);
        }
 
-       if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
-               tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
-       else
-               tp->mac_mode = 0;
        tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
-               MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
-       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
+                       MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
+                       MAC_MODE_FHDE_ENABLE;
+       if (tg3_flag(tp, ENABLE_APE))
+               tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
+       if (!tg3_flag(tp, 5705_PLUS) &&
            !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
                tp->mac_mode |= MAC_MODE_LINK_POLARITY;
@@ -8319,12 +8624,12 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        udelay(40);
 
        /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
-        * If TG3_FLG2_IS_NIC is zero, we should read the
+        * If TG3_FLAG_IS_NIC is zero, we should read the
         * register to preserve the GPIO settings for LOMs. The GPIOs,
         * whether used as inputs or outputs, are set by boot code after
         * reset.
         */
-       if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
+       if (!tg3_flag(tp, IS_NIC)) {
                u32 gpio_mask;
 
                gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
@@ -8342,21 +8647,20 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
 
                /* GPIO1 must be driven high for eeprom write protect */
-               if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
+               if (tg3_flag(tp, EEPROM_WRITE_PROT))
                        tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
                                               GRC_LCLCTRL_GPIO_OUTPUT1);
        }
        tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
        udelay(100);
 
-       if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
-               tp->irq_cnt > 1) {
+       if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) {
                val = tr32(MSGINT_MODE);
                val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
                tw32(MSGINT_MODE, val);
        }
 
-       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
+       if (!tg3_flag(tp, 5705_PLUS)) {
                tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
                udelay(40);
        }
@@ -8369,18 +8673,18 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
            tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
-               if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
+               if (tg3_flag(tp, TSO_CAPABLE) &&
                    (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
                     tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
                        /* nothing */
                } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
-                          !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
+                          !tg3_flag(tp, IS_5788)) {
                        val |= WDMAC_MODE_RX_ACCEL;
                }
        }
 
        /* Enable host coalescing bug fix */
-       if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
+       if (tg3_flag(tp, 5755_PLUS))
                val |= WDMAC_MODE_STATUS_TAG_FIX;
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
@@ -8389,7 +8693,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        tw32_f(WDMAC_MODE, val);
        udelay(40);
 
-       if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
+       if (tg3_flag(tp, PCIX_MODE)) {
                u16 pcix_cmd;
 
                pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
@@ -8409,7 +8713,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        udelay(40);
 
        tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
-       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
+       if (!tg3_flag(tp, 5705_PLUS))
                tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
@@ -8421,15 +8725,16 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
        tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
        val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
+       if (tg3_flag(tp, LRG_PROD_RING_CAP))
                val |= RCVDBDI_MODE_LRG_RING_SZ;
        tw32(RCVDBDI_MODE, val);
        tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
-       if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
+       if (tg3_flag(tp, HW_TSO_1) ||
+           tg3_flag(tp, HW_TSO_2) ||
+           tg3_flag(tp, HW_TSO_3))
                tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
        val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
-       if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
+       if (tg3_flag(tp, ENABLE_TSS))
                val |= SNDBDI_MODE_MULTI_TXQ_EN;
        tw32(SNDBDI_MODE, val);
        tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
@@ -8440,29 +8745,46 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                        return err;
        }
 
-       if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
+       if (tg3_flag(tp, TSO_CAPABLE)) {
                err = tg3_load_tso_firmware(tp);
                if (err)
                        return err;
        }
 
        tp->tx_mode = TX_MODE_ENABLE;
-       if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
+
+       if (tg3_flag(tp, 5755_PLUS) ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
                tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
+               val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
+               tp->tx_mode &= ~val;
+               tp->tx_mode |= tr32(MAC_TX_MODE) & val;
+       }
+
        tw32_f(MAC_TX_MODE, tp->tx_mode);
        udelay(100);
 
-       if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
+       if (tg3_flag(tp, ENABLE_RSS)) {
+               int i = 0;
                u32 reg = MAC_RSS_INDIR_TBL_0;
-               u8 *ent = (u8 *)&val;
 
-               /* Setup the indirection table */
-               for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
-                       int idx = i % sizeof(val);
+               if (tp->irq_cnt == 2) {
+                       for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i += 8) {
+                               tw32(reg, 0x0);
+                               reg += 4;
+                       }
+               } else {
+                       u32 val;
 
-                       ent[idx] = i % (tp->irq_cnt - 1);
-                       if (idx == sizeof(val) - 1) {
+                       while (i < TG3_RSS_INDIR_TBL_SIZE) {
+                               val = i % (tp->irq_cnt - 1);
+                               i++;
+                               for (; i % 8; i++) {
+                                       val <<= 4;
+                                       val |= (i % (tp->irq_cnt - 1));
+                               }
                                tw32(reg, val);
                                reg += 4;
                        }
@@ -8482,10 +8804,10 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        }
 
        tp->rx_mode = RX_MODE_ENABLE;
-       if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
+       if (tg3_flag(tp, 5755_PLUS))
                tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
 
-       if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
+       if (tg3_flag(tp, ENABLE_RSS))
                tp->rx_mode |= RX_MODE_RSS_ENABLE |
                               RX_MODE_RSS_ITBL_HASH_BITS_7 |
                               RX_MODE_RSS_IPV6_HASH_EN |
@@ -8532,11 +8854,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
            (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
                /* Use hardware link auto-negotiation */
-               tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
+               tg3_flag_set(tp, HW_AUTONEG);
        }
 
        if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
-           (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
                u32 tmp;
 
                tmp = tr32(SERDES_RX_CTRL);
@@ -8546,7 +8868,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
        }
 
-       if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
+       if (!tg3_flag(tp, USE_PHYLIB)) {
                if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
                        tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
                        tp->link_config.speed = tp->link_config.orig_speed;
@@ -8579,12 +8901,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
        tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
 
-       if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
-           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
+       if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
                limit = 8;
        else
                limit = 16;
-       if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
+       if (tg3_flag(tp, ENABLE_ASF))
                limit -= 4;
        switch (limit) {
        case 16:
@@ -8622,7 +8943,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                break;
        }
 
-       if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
+       if (tg3_flag(tp, ENABLE_APE))
                /* Write our heartbeat update interval to APE. */
                tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
                                APE_HOST_HEARTBEAT_INT_DISABLE);
@@ -8688,10 +9009,48 @@ static void tg3_periodic_fetch_stats(struct tg3 *tp)
        TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
 
        TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
-       TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
+           tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 &&
+           tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) {
+               TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
+       } else {
+               u32 val = tr32(HOSTCC_FLOW_ATTN);
+               val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
+               if (val) {
+                       tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
+                       sp->rx_discards.low += val;
+                       if (sp->rx_discards.low < val)
+                               sp->rx_discards.high += 1;
+               }
+               sp->mbuf_lwm_thresh_hit = sp->rx_discards;
+       }
        TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
 }
 
+static void tg3_chk_missed_msi(struct tg3 *tp)
+{
+       u32 i;
+
+       for (i = 0; i < tp->irq_cnt; i++) {
+               struct tg3_napi *tnapi = &tp->napi[i];
+
+               if (tg3_has_work(tnapi)) {
+                       if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
+                           tnapi->last_tx_cons == tnapi->tx_cons) {
+                               if (tnapi->chk_msi_cnt < 1) {
+                                       tnapi->chk_msi_cnt++;
+                                       return;
+                               }
+                               tw32_mailbox(tnapi->int_mbox,
+                                            tnapi->last_tag << 24);
+                       }
+               }
+               tnapi->chk_msi_cnt = 0;
+               tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
+               tnapi->last_tx_cons = tnapi->tx_cons;
+       }
+}
+
 static void tg3_timer(unsigned long __opaque)
 {
        struct tg3 *tp = (struct tg3 *) __opaque;
@@ -8701,7 +9060,11 @@ static void tg3_timer(unsigned long __opaque)
 
        spin_lock(&tp->lock);
 
-       if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
+               tg3_chk_missed_msi(tp);
+
+       if (!tg3_flag(tp, TAGGED_STATUS)) {
                /* All of this garbage is because when using non-tagged
                 * IRQ status the mailbox/status_block protocol the chip
                 * uses with the cpu is race prone.
@@ -8715,7 +9078,7 @@ static void tg3_timer(unsigned long __opaque)
                }
 
                if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
-                       tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
+                       tg3_flag_set(tp, RESTART_TIMER);
                        spin_unlock(&tp->lock);
                        schedule_work(&tp->reset_task);
                        return;
@@ -8724,16 +9087,13 @@ static void tg3_timer(unsigned long __opaque)
 
        /* This part only runs once per second. */
        if (!--tp->timer_counter) {
-               if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
+               if (tg3_flag(tp, 5705_PLUS))
                        tg3_periodic_fetch_stats(tp);
 
-               if (tp->setlpicnt && !--tp->setlpicnt) {
-                       u32 val = tr32(TG3_CPMU_EEE_MODE);
-                       tw32(TG3_CPMU_EEE_MODE,
-                            val | TG3_CPMU_EEEMD_LPI_ENABLE);
-               }
+               if (tp->setlpicnt && !--tp->setlpicnt)
+                       tg3_phy_eee_enable(tp);
 
-               if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
+               if (tg3_flag(tp, USE_LINKCHG_REG)) {
                        u32 mac_stat;
                        int phy_event;
 
@@ -8748,7 +9108,7 @@ static void tg3_timer(unsigned long __opaque)
 
                        if (phy_event)
                                tg3_setup_phy(tp, 0);
-               } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
+               } else if (tg3_flag(tp, POLL_SERDES)) {
                        u32 mac_stat = tr32(MAC_STATUS);
                        int need_setup = 0;
 
@@ -8773,7 +9133,7 @@ static void tg3_timer(unsigned long __opaque)
                                tg3_setup_phy(tp, 0);
                        }
                } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
-                          (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
+                          tg3_flag(tp, 5780_CLASS)) {
                        tg3_serdes_parallel_detect(tp);
                }
 
@@ -8798,8 +9158,7 @@ static void tg3_timer(unsigned long __opaque)
         * resets.
         */
        if (!--tp->asf_counter) {
-               if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
-                   !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
+               if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
                        tg3_wait_for_event_ack(tp);
 
                        tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
@@ -8835,16 +9194,16 @@ static int tg3_request_irq(struct tg3 *tp, int irq_num)
                name[IFNAMSIZ-1] = 0;
        }
 
-       if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
+       if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
                fn = tg3_msi;
-               if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
+               if (tg3_flag(tp, 1SHOT_MSI))
                        fn = tg3_msi_1shot;
-               flags = IRQF_SAMPLE_RANDOM;
+               flags = 0;
        } else {
                fn = tg3_interrupt;
-               if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
+               if (tg3_flag(tp, TAGGED_STATUS))
                        fn = tg3_interrupt_tagged;
-               flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
+               flags = IRQF_SHARED;
        }
 
        return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
@@ -8868,8 +9227,7 @@ static int tg3_test_interrupt(struct tg3 *tp)
         * Turn off MSI one shot mode.  Otherwise this test has no
         * observable way to know whether the interrupt was delivered.
         */
-       if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
-           (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
+       if (tg3_flag(tp, 57765_PLUS)) {
                val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
                tw32(MSGINT_MODE, val);
        }
@@ -8897,6 +9255,10 @@ static int tg3_test_interrupt(struct tg3 *tp)
                        break;
                }
 
+               if (tg3_flag(tp, 57765_PLUS) &&
+                   tnapi->hw_status->status_tag != tnapi->last_tag)
+                       tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
+
                msleep(10);
        }
 
@@ -8911,8 +9273,7 @@ static int tg3_test_interrupt(struct tg3 *tp)
 
        if (intr_ok) {
                /* Reenable MSI one shot mode. */
-               if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
-                   (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
+               if (tg3_flag(tp, 57765_PLUS)) {
                        val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
                        tw32(MSGINT_MODE, val);
                }
@@ -8930,7 +9291,7 @@ static int tg3_test_msi(struct tg3 *tp)
        int err;
        u16 pci_cmd;
 
-       if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
+       if (!tg3_flag(tp, USING_MSI))
                return 0;
 
        /* Turn off SERR reporting in case MSI terminates with Master
@@ -8960,7 +9321,7 @@ static int tg3_test_msi(struct tg3 *tp)
 
        pci_disable_msi(tp->pdev);
 
-       tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
+       tg3_flag_clear(tp, USING_MSI);
        tp->napi[0].irq_vec = tp->pdev->irq;
 
        err = tg3_request_irq(tp, 0);
@@ -9057,9 +9418,11 @@ static bool tg3_enable_msix(struct tg3 *tp)
        }
 
        if (tp->irq_cnt > 1) {
-               tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
-                       tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
+               tg3_flag_set(tp, ENABLE_RSS);
+
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
+                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
+                       tg3_flag_set(tp, ENABLE_TSS);
                        netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
                }
        }
@@ -9069,8 +9432,8 @@ static bool tg3_enable_msix(struct tg3 *tp)
 
 static void tg3_ints_init(struct tg3 *tp)
 {
-       if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
-           !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
+       if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
+           !tg3_flag(tp, TAGGED_STATUS)) {
                /* All MSI supporting chips should support tagged
                 * status.  Assert that this is the case.
                 */
@@ -9079,21 +9442,19 @@ static void tg3_ints_init(struct tg3 *tp)
                goto defcfg;
        }
 
-       if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
-               tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
-       else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
-                pci_enable_msi(tp->pdev) == 0)
-               tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
+       if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
+               tg3_flag_set(tp, USING_MSIX);
+       else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
+               tg3_flag_set(tp, USING_MSI);
 
-       if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
+       if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
                u32 msi_mode = tr32(MSGINT_MODE);
-               if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
-                   tp->irq_cnt > 1)
+               if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
                        msi_mode |= MSGINT_MODE_MULTIVEC_EN;
                tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
        }
 defcfg:
-       if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
+       if (!tg3_flag(tp, USING_MSIX)) {
                tp->irq_cnt = 1;
                tp->napi[0].irq_vec = tp->pdev->irq;
                netif_set_real_num_tx_queues(tp->dev, 1);
@@ -9103,12 +9464,14 @@ defcfg:
 
 static void tg3_ints_fini(struct tg3 *tp)
 {
-       if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
+       if (tg3_flag(tp, USING_MSIX))
                pci_disable_msix(tp->pdev);
-       else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
+       else if (tg3_flag(tp, USING_MSI))
                pci_disable_msi(tp->pdev);
-       tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
-       tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
+       tg3_flag_clear(tp, USING_MSI);
+       tg3_flag_clear(tp, USING_MSIX);
+       tg3_flag_clear(tp, ENABLE_RSS);
+       tg3_flag_clear(tp, ENABLE_TSS);
 }
 
 static int tg3_open(struct net_device *dev)
@@ -9123,10 +9486,10 @@ static int tg3_open(struct net_device *dev)
                                return err;
                } else if (err) {
                        netdev_warn(tp->dev, "TSO capability disabled\n");
-                       tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
-               } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
+                       tg3_flag_clear(tp, TSO_CAPABLE);
+               } else if (!tg3_flag(tp, TSO_CAPABLE)) {
                        netdev_notice(tp->dev, "TSO capability restored\n");
-                       tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
+                       tg3_flag_set(tp, TSO_CAPABLE);
                }
        }
 
@@ -9139,7 +9502,7 @@ static int tg3_open(struct net_device *dev)
        tg3_full_lock(tp, 0);
 
        tg3_disable_ints(tp);
-       tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
+       tg3_flag_clear(tp, INIT_COMPLETE);
 
        tg3_full_unlock(tp);
 
@@ -9180,7 +9543,9 @@ static int tg3_open(struct net_device *dev)
                tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
                tg3_free_rings(tp);
        } else {
-               if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
+               if (tg3_flag(tp, TAGGED_STATUS) &&
+                       GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
+                       GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765)
                        tp->timer_offset = HZ;
                else
                        tp->timer_offset = HZ / 10;
@@ -9202,7 +9567,7 @@ static int tg3_open(struct net_device *dev)
        if (err)
                goto err_out3;
 
-       if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
+       if (tg3_flag(tp, USING_MSI)) {
                err = tg3_test_msi(tp);
 
                if (err) {
@@ -9214,8 +9579,7 @@ static int tg3_open(struct net_device *dev)
                        goto err_out2;
                }
 
-               if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
-                   (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
+               if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
                        u32 val = tr32(PCIE_TRANSACTION_CFG);
 
                        tw32(PCIE_TRANSACTION_CFG,
@@ -9228,13 +9592,20 @@ static int tg3_open(struct net_device *dev)
        tg3_full_lock(tp, 0);
 
        add_timer(&tp->timer);
-       tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
+       tg3_flag_set(tp, INIT_COMPLETE);
        tg3_enable_ints(tp);
 
        tg3_full_unlock(tp);
 
        netif_tx_start_all_queues(dev);
 
+       /*
+        * Reset loopback feature if it was turned on while the device was down
+        * make sure that it's installed properly now.
+        */
+       if (dev->features & NETIF_F_LOOPBACK)
+               tg3_set_loopback(dev, dev->features);
+
        return 0;
 
 err_out3:
@@ -9250,6 +9621,8 @@ err_out2:
 
 err_out1:
        tg3_ints_fini(tp);
+       tg3_frob_aux_power(tp, false);
+       pci_set_power_state(tp->pdev, PCI_D3hot);
        return err;
 }
 
@@ -9277,7 +9650,7 @@ static int tg3_close(struct net_device *dev)
 
        tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
        tg3_free_rings(tp);
-       tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
+       tg3_flag_clear(tp, INIT_COMPLETE);
 
        tg3_full_unlock(tp);
 
@@ -9424,6 +9797,8 @@ static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
        ESTAT_ADD(nic_avoided_irqs);
        ESTAT_ADD(nic_tx_threshold_hit);
 
+       ESTAT_ADD(mbuf_lwm_thresh_hit);
+
        return estats;
 }
 
@@ -9534,7 +9909,7 @@ static void __tg3_set_rx_mode(struct net_device *dev)
        /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
         * flag clear.
         */
-       if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
+       if (!tg3_flag(tp, ENABLE_ASF))
                rx_mode |= RX_MODE_KEEP_VLAN_TAG;
 #endif
 
@@ -9588,82 +9963,26 @@ static void tg3_set_rx_mode(struct net_device *dev)
        tg3_full_unlock(tp);
 }
 
-#define TG3_REGDUMP_LEN                (32 * 1024)
-
 static int tg3_get_regs_len(struct net_device *dev)
 {
-       return TG3_REGDUMP_LEN;
+       return TG3_REG_BLK_SIZE;
 }
 
 static void tg3_get_regs(struct net_device *dev,
                struct ethtool_regs *regs, void *_p)
 {
-       u32 *p = _p;
        struct tg3 *tp = netdev_priv(dev);
-       u8 *orig_p = _p;
-       int i;
 
        regs->version = 0;
 
-       memset(p, 0, TG3_REGDUMP_LEN);
+       memset(_p, 0, TG3_REG_BLK_SIZE);
 
        if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
                return;
 
        tg3_full_lock(tp, 0);
 
-#define __GET_REG32(reg)       (*(p)++ = tr32(reg))
-#define GET_REG32_LOOP(base, len)              \
-do {   p = (u32 *)(orig_p + (base));           \
-       for (i = 0; i < len; i += 4)            \
-               __GET_REG32((base) + i);        \
-} while (0)
-#define GET_REG32_1(reg)                       \
-do {   p = (u32 *)(orig_p + (reg));            \
-       __GET_REG32((reg));                     \
-} while (0)
-
-       GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
-       GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
-       GET_REG32_LOOP(MAC_MODE, 0x4f0);
-       GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
-       GET_REG32_1(SNDDATAC_MODE);
-       GET_REG32_LOOP(SNDBDS_MODE, 0x80);
-       GET_REG32_LOOP(SNDBDI_MODE, 0x48);
-       GET_REG32_1(SNDBDC_MODE);
-       GET_REG32_LOOP(RCVLPC_MODE, 0x20);
-       GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
-       GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
-       GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
-       GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
-       GET_REG32_1(RCVDCC_MODE);
-       GET_REG32_LOOP(RCVBDI_MODE, 0x20);
-       GET_REG32_LOOP(RCVCC_MODE, 0x14);
-       GET_REG32_LOOP(RCVLSC_MODE, 0x08);
-       GET_REG32_1(MBFREE_MODE);
-       GET_REG32_LOOP(HOSTCC_MODE, 0x100);
-       GET_REG32_LOOP(MEMARB_MODE, 0x10);
-       GET_REG32_LOOP(BUFMGR_MODE, 0x58);
-       GET_REG32_LOOP(RDMAC_MODE, 0x08);
-       GET_REG32_LOOP(WDMAC_MODE, 0x08);
-       GET_REG32_1(RX_CPU_MODE);
-       GET_REG32_1(RX_CPU_STATE);
-       GET_REG32_1(RX_CPU_PGMCTR);
-       GET_REG32_1(RX_CPU_HWBKPT);
-       GET_REG32_1(TX_CPU_MODE);
-       GET_REG32_1(TX_CPU_STATE);
-       GET_REG32_1(TX_CPU_PGMCTR);
-       GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
-       GET_REG32_LOOP(FTQ_RESET, 0x120);
-       GET_REG32_LOOP(MSGINT_MODE, 0x0c);
-       GET_REG32_1(DMAC_MODE);
-       GET_REG32_LOOP(GRC_MODE, 0x4c);
-       if (tp->tg3_flags & TG3_FLAG_NVRAM)
-               GET_REG32_LOOP(NVRAM_CMD, 0x24);
-
-#undef __GET_REG32
-#undef GET_REG32_LOOP
-#undef GET_REG32_1
+       tg3_dump_legacy_regs(tp, (u32 *)_p);
 
        tg3_full_unlock(tp);
 }
@@ -9683,7 +10002,7 @@ static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
        u32 i, offset, len, b_offset, b_count;
        __be32 val;
 
-       if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
+       if (tg3_flag(tp, NO_NVRAM))
                return -EINVAL;
 
        if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
@@ -9712,7 +10031,7 @@ static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
                eeprom->len += b_count;
        }
 
-       /* read bytes upto the last 4 byte boundary */
+       /* read bytes up to the last 4 byte boundary */
        pd = &data[eeprom->len];
        for (i = 0; i < (len - (len & 3)); i += 4) {
                ret = tg3_nvram_read_be32(tp, offset + i, &val);
@@ -9751,7 +10070,7 @@ static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
        if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
                return -EAGAIN;
 
-       if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
+       if (tg3_flag(tp, NO_NVRAM) ||
            eeprom->magic != TG3_EEPROM_MAGIC)
                return -EINVAL;
 
@@ -9803,7 +10122,7 @@ static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
        struct tg3 *tp = netdev_priv(dev);
 
-       if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
+       if (tg3_flag(tp, USE_PHYLIB)) {
                struct phy_device *phydev;
                if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
                        return -EAGAIN;
@@ -9830,11 +10149,23 @@ static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
        }
 
        cmd->advertising = tp->link_config.advertising;
+       if (tg3_flag(tp, PAUSE_AUTONEG)) {
+               if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
+                       if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
+                               cmd->advertising |= ADVERTISED_Pause;
+                       } else {
+                               cmd->advertising |= ADVERTISED_Pause |
+                                                   ADVERTISED_Asym_Pause;
+                       }
+               } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
+                       cmd->advertising |= ADVERTISED_Asym_Pause;
+               }
+       }
        if (netif_running(dev)) {
-               cmd->speed = tp->link_config.active_speed;
+               ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
                cmd->duplex = tp->link_config.active_duplex;
        } else {
-               cmd->speed = SPEED_INVALID;
+               ethtool_cmd_speed_set(cmd, SPEED_INVALID);
                cmd->duplex = DUPLEX_INVALID;
        }
        cmd->phy_address = tp->phy_addr;
@@ -9848,8 +10179,9 @@ static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
        struct tg3 *tp = netdev_priv(dev);
+       u32 speed = ethtool_cmd_speed(cmd);
 
-       if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
+       if (tg3_flag(tp, USE_PHYLIB)) {
                struct phy_device *phydev;
                if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
                        return -EAGAIN;
@@ -9897,14 +10229,14 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
                cmd->advertising &= mask;
        } else {
                if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
-                       if (cmd->speed != SPEED_1000)
+                       if (speed != SPEED_1000)
                                return -EINVAL;
 
                        if (cmd->duplex != DUPLEX_FULL)
                                return -EINVAL;
                } else {
-                       if (cmd->speed != SPEED_100 &&
-                           cmd->speed != SPEED_10)
+                       if (speed != SPEED_100 &&
+                           speed != SPEED_10)
                                return -EINVAL;
                }
        }
@@ -9919,7 +10251,7 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
                tp->link_config.duplex = DUPLEX_INVALID;
        } else {
                tp->link_config.advertising = 0;
-               tp->link_config.speed = cmd->speed;
+               tp->link_config.speed = speed;
                tp->link_config.duplex = cmd->duplex;
        }
 
@@ -9949,14 +10281,12 @@ static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 {
        struct tg3 *tp = netdev_priv(dev);
 
-       if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
-           device_can_wakeup(&tp->pdev->dev))
+       if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
                wol->supported = WAKE_MAGIC;
        else
                wol->supported = 0;
        wol->wolopts = 0;
-       if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
-           device_can_wakeup(&tp->pdev->dev))
+       if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
                wol->wolopts = WAKE_MAGIC;
        memset(&wol->sopass, 0, sizeof(wol->sopass));
 }
@@ -9969,19 +10299,18 @@ static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
        if (wol->wolopts & ~WAKE_MAGIC)
                return -EINVAL;
        if ((wol->wolopts & WAKE_MAGIC) &&
-           !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
+           !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
                return -EINVAL;
 
        device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
 
        spin_lock_bh(&tp->lock);
        if (device_may_wakeup(dp))
-               tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
+               tg3_flag_set(tp, WOL_ENABLE);
        else
-               tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
+               tg3_flag_clear(tp, WOL_ENABLE);
        spin_unlock_bh(&tp->lock);
 
-
        return 0;
 }
 
@@ -9997,33 +10326,6 @@ static void tg3_set_msglevel(struct net_device *dev, u32 value)
        tp->msg_enable = value;
 }
 
-static int tg3_set_tso(struct net_device *dev, u32 value)
-{
-       struct tg3 *tp = netdev_priv(dev);
-
-       if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
-               if (value)
-                       return -EINVAL;
-               return 0;
-       }
-       if ((dev->features & NETIF_F_IPV6_CSUM) &&
-           ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
-            (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
-               if (value) {
-                       dev->features |= NETIF_F_TSO6;
-                       if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
-                           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
-                           (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
-                            GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
-                           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
-                           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
-                               dev->features |= NETIF_F_TSO_ECN;
-               } else
-                       dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
-       }
-       return ethtool_op_set_tso(dev, value);
-}
-
 static int tg3_nway_reset(struct net_device *dev)
 {
        struct tg3 *tp = netdev_priv(dev);
@@ -10035,7 +10337,7 @@ static int tg3_nway_reset(struct net_device *dev)
        if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
                return -EINVAL;
 
-       if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
+       if (tg3_flag(tp, USE_PHYLIB)) {
                if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
                        return -EAGAIN;
                r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
@@ -10064,7 +10366,7 @@ static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *
 
        ering->rx_max_pending = tp->rx_std_ring_mask;
        ering->rx_mini_max_pending = 0;
-       if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
+       if (tg3_flag(tp, JUMBO_RING_ENABLE))
                ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
        else
                ering->rx_jumbo_max_pending = 0;
@@ -10073,7 +10375,7 @@ static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *
 
        ering->rx_pending = tp->rx_pending;
        ering->rx_mini_pending = 0;
-       if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
+       if (tg3_flag(tp, JUMBO_RING_ENABLE))
                ering->rx_jumbo_pending = tp->rx_jumbo_pending;
        else
                ering->rx_jumbo_pending = 0;
@@ -10090,7 +10392,7 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e
            (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
            (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
            (ering->tx_pending <= MAX_SKB_FRAGS) ||
-           ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
+           (tg3_flag(tp, TSO_BUG) &&
             (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
                return -EINVAL;
 
@@ -10104,7 +10406,7 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e
 
        tp->rx_pending = ering->rx_pending;
 
-       if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
+       if (tg3_flag(tp, MAX_RXPEND_64) &&
            tp->rx_pending > 63)
                tp->rx_pending = 63;
        tp->rx_jumbo_pending = ering->rx_jumbo_pending;
@@ -10131,7 +10433,7 @@ static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam
 {
        struct tg3 *tp = netdev_priv(dev);
 
-       epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
+       epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
 
        if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
                epause->rx_pause = 1;
@@ -10149,7 +10451,7 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam
        struct tg3 *tp = netdev_priv(dev);
        int err = 0;
 
-       if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
+       if (tg3_flag(tp, USE_PHYLIB)) {
                u32 newadv;
                struct phy_device *phydev;
 
@@ -10177,9 +10479,9 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam
                        newadv = 0;
 
                if (epause->autoneg)
-                       tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
+                       tg3_flag_set(tp, PAUSE_AUTONEG);
                else
-                       tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
+                       tg3_flag_clear(tp, PAUSE_AUTONEG);
 
                if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
                        u32 oldadv = phydev->advertising &
@@ -10221,9 +10523,9 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam
                tg3_full_lock(tp, irq_sync);
 
                if (epause->autoneg)
-                       tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
+                       tg3_flag_set(tp, PAUSE_AUTONEG);
                else
-                       tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
+                       tg3_flag_clear(tp, PAUSE_AUTONEG);
                if (epause->rx_pause)
                        tp->link_config.flowctrl |= FLOW_CTRL_RX;
                else
@@ -10246,50 +10548,6 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam
        return err;
 }
 
-static u32 tg3_get_rx_csum(struct net_device *dev)
-{
-       struct tg3 *tp = netdev_priv(dev);
-       return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
-}
-
-static int tg3_set_rx_csum(struct net_device *dev, u32 data)
-{
-       struct tg3 *tp = netdev_priv(dev);
-
-       if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
-               if (data != 0)
-                       return -EINVAL;
-               return 0;
-       }
-
-       spin_lock_bh(&tp->lock);
-       if (data)
-               tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
-       else
-               tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
-       spin_unlock_bh(&tp->lock);
-
-       return 0;
-}
-
-static int tg3_set_tx_csum(struct net_device *dev, u32 data)
-{
-       struct tg3 *tp = netdev_priv(dev);
-
-       if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
-               if (data != 0)
-                       return -EINVAL;
-               return 0;
-       }
-
-       if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
-               ethtool_op_set_tx_ipv6_csum(dev, data);
-       else
-               ethtool_op_set_tx_csum(dev, data);
-
-       return 0;
-}
-
 static int tg3_get_sset_count(struct net_device *dev, int sset)
 {
        switch (sset) {
@@ -10317,35 +10575,38 @@ static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
        }
 }
 
-static int tg3_phys_id(struct net_device *dev, u32 data)
+static int tg3_set_phys_id(struct net_device *dev,
+                           enum ethtool_phys_id_state state)
 {
        struct tg3 *tp = netdev_priv(dev);
-       int i;
 
        if (!netif_running(tp->dev))
                return -EAGAIN;
 
-       if (data == 0)
-               data = UINT_MAX / 2;
-
-       for (i = 0; i < (data * 2); i++) {
-               if ((i % 2) == 0)
-                       tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
-                                          LED_CTRL_1000MBPS_ON |
-                                          LED_CTRL_100MBPS_ON |
-                                          LED_CTRL_10MBPS_ON |
-                                          LED_CTRL_TRAFFIC_OVERRIDE |
-                                          LED_CTRL_TRAFFIC_BLINK |
-                                          LED_CTRL_TRAFFIC_LED);
+       switch (state) {
+       case ETHTOOL_ID_ACTIVE:
+               return 1;       /* cycle on/off once per second */
+
+       case ETHTOOL_ID_ON:
+               tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
+                    LED_CTRL_1000MBPS_ON |
+                    LED_CTRL_100MBPS_ON |
+                    LED_CTRL_10MBPS_ON |
+                    LED_CTRL_TRAFFIC_OVERRIDE |
+                    LED_CTRL_TRAFFIC_BLINK |
+                    LED_CTRL_TRAFFIC_LED);
+               break;
 
-               else
-                       tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
-                                          LED_CTRL_TRAFFIC_OVERRIDE);
+       case ETHTOOL_ID_OFF:
+               tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
+                    LED_CTRL_TRAFFIC_OVERRIDE);
+               break;
 
-               if (msleep_interruptible(500))
-                       break;
+       case ETHTOOL_ID_INACTIVE:
+               tw32(MAC_LED_CTRL, tp->led_ctrl);
+               break;
        }
-       tw32(MAC_LED_CTRL, tp->led_ctrl);
+
        return 0;
 }
 
@@ -10356,20 +10617,99 @@ static void tg3_get_ethtool_stats(struct net_device *dev,
        memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
 }
 
+static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
+{
+       int i;
+       __be32 *buf;
+       u32 offset = 0, len = 0;
+       u32 magic, val;
+
+       if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
+               return NULL;
+
+       if (magic == TG3_EEPROM_MAGIC) {
+               for (offset = TG3_NVM_DIR_START;
+                    offset < TG3_NVM_DIR_END;
+                    offset += TG3_NVM_DIRENT_SIZE) {
+                       if (tg3_nvram_read(tp, offset, &val))
+                               return NULL;
+
+                       if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
+                           TG3_NVM_DIRTYPE_EXTVPD)
+                               break;
+               }
+
+               if (offset != TG3_NVM_DIR_END) {
+                       len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
+                       if (tg3_nvram_read(tp, offset + 4, &offset))
+                               return NULL;
+
+                       offset = tg3_nvram_logical_addr(tp, offset);
+               }
+       }
+
+       if (!offset || !len) {
+               offset = TG3_NVM_VPD_OFF;
+               len = TG3_NVM_VPD_LEN;
+       }
+
+       buf = kmalloc(len, GFP_KERNEL);
+       if (buf == NULL)
+               return NULL;
+
+       if (magic == TG3_EEPROM_MAGIC) {
+               for (i = 0; i < len; i += 4) {
+                       /* The data is in little-endian format in NVRAM.
+                        * Use the big-endian read routines to preserve
+                        * the byte order as it exists in NVRAM.
+                        */
+                       if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
+                               goto error;
+               }
+       } else {
+               u8 *ptr;
+               ssize_t cnt;
+               unsigned int pos = 0;
+
+               ptr = (u8 *)&buf[0];
+               for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
+                       cnt = pci_read_vpd(tp->pdev, pos,
+                                          len - pos, ptr);
+                       if (cnt == -ETIMEDOUT || cnt == -EINTR)
+                               cnt = 0;
+                       else if (cnt < 0)
+                               goto error;
+               }
+               if (pos != len)
+                       goto error;
+       }
+
+       *vpdlen = len;
+
+       return buf;
+
+error:
+       kfree(buf);
+       return NULL;
+}
+
 #define NVRAM_TEST_SIZE 0x100
 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE  0x14
 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE  0x18
 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE  0x1c
+#define NVRAM_SELFBOOT_FORMAT1_4_SIZE  0x20
+#define NVRAM_SELFBOOT_FORMAT1_5_SIZE  0x24
+#define NVRAM_SELFBOOT_FORMAT1_6_SIZE  0x50
 #define NVRAM_SELFBOOT_HW_SIZE 0x20
 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
 
 static int tg3_test_nvram(struct tg3 *tp)
 {
-       u32 csum, magic;
+       u32 csum, magic, len;
        __be32 *buf;
        int i, j, k, err = 0, size;
 
-       if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
+       if (tg3_flag(tp, NO_NVRAM))
                return 0;
 
        if (tg3_nvram_read(tp, 0, &magic) != 0)
@@ -10390,8 +10730,17 @@ static int tg3_test_nvram(struct tg3 *tp)
                        case TG3_EEPROM_SB_REVISION_3:
                                size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
                                break;
+                       case TG3_EEPROM_SB_REVISION_4:
+                               size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
+                               break;
+                       case TG3_EEPROM_SB_REVISION_5:
+                               size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
+                               break;
+                       case TG3_EEPROM_SB_REVISION_6:
+                               size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
+                               break;
                        default:
-                               return 0;
+                               return -EIO;
                        }
                } else
                        return 0;
@@ -10495,23 +10844,19 @@ static int tg3_test_nvram(struct tg3 *tp)
        if (csum != le32_to_cpu(buf[0xfc/4]))
                goto out;
 
-       for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
-               /* The data is in little-endian format in NVRAM.
-                * Use the big-endian read routines to preserve
-                * the byte order as it exists in NVRAM.
-                */
-               if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &buf[i/4]))
-                       goto out;
-       }
+       kfree(buf);
 
-       i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN,
-                            PCI_VPD_LRDT_RO_DATA);
+       buf = tg3_vpd_readblock(tp, &len);
+       if (!buf)
+               return -ENOMEM;
+
+       i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
        if (i > 0) {
                j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
                if (j < 0)
                        goto out;
 
-               if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN)
+               if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
                        goto out;
 
                i += PCI_VPD_LRDT_TAG_SIZE;
@@ -10714,9 +11059,9 @@ static int tg3_test_registers(struct tg3 *tp)
        };
 
        is_5705 = is_5750 = 0;
-       if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
+       if (tg3_flag(tp, 5705_PLUS)) {
                is_5705 = 1;
-               if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
+               if (tg3_flag(tp, 5750_PLUS))
                        is_5750 = 1;
        }
 
@@ -10727,7 +11072,7 @@ static int tg3_test_registers(struct tg3 *tp)
                if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
                        continue;
 
-               if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
+               if (tg3_flag(tp, IS_5788) &&
                    (reg_tbl[i].flags & TG3_FL_NOT_5788))
                        continue;
 
@@ -10850,16 +11195,15 @@ static int tg3_test_memory(struct tg3 *tp)
        int err = 0;
        int i;
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
+       if (tg3_flag(tp, 5717_PLUS))
                mem_tbl = mem_tbl_5717;
        else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
                mem_tbl = mem_tbl_57765;
-       else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
+       else if (tg3_flag(tp, 5755_PLUS))
                mem_tbl = mem_tbl_5755;
        else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
                mem_tbl = mem_tbl_5906;
-       else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
+       else if (tg3_flag(tp, 5705_PLUS))
                mem_tbl = mem_tbl_5705;
        else
                mem_tbl = mem_tbl_570x;
@@ -10875,11 +11219,36 @@ static int tg3_test_memory(struct tg3 *tp)
 
 #define TG3_MAC_LOOPBACK       0
 #define TG3_PHY_LOOPBACK       1
+#define TG3_TSO_LOOPBACK       2
+
+#define TG3_TSO_MSS            500
+
+#define TG3_TSO_IP_HDR_LEN     20
+#define TG3_TSO_TCP_HDR_LEN    20
+#define TG3_TSO_TCP_OPT_LEN    12
+
+static const u8 tg3_tso_header[] = {
+0x08, 0x00,
+0x45, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x40, 0x00,
+0x40, 0x06, 0x00, 0x00,
+0x0a, 0x00, 0x00, 0x01,
+0x0a, 0x00, 0x00, 0x02,
+0x0d, 0x00, 0xe0, 0x00,
+0x00, 0x00, 0x01, 0x00,
+0x00, 0x00, 0x02, 0x00,
+0x80, 0x10, 0x10, 0x00,
+0x14, 0x09, 0x00, 0x00,
+0x01, 0x01, 0x08, 0x0a,
+0x11, 0x11, 0x11, 0x11,
+0x11, 0x11, 0x11, 0x11,
+};
 
-static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
+static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, int loopback_mode)
 {
        u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
-       u32 desc_idx, coal_now;
+       u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
+       u32 budget;
        struct sk_buff *skb, *rx_skb;
        u8 *tx_data;
        dma_addr_t map;
@@ -10891,9 +11260,9 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
        tnapi = &tp->napi[0];
        rnapi = &tp->napi[0];
        if (tp->irq_cnt > 1) {
-               if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
+               if (tg3_flag(tp, ENABLE_RSS))
                        rnapi = &tp->napi[1];
-               if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
+               if (tg3_flag(tp, ENABLE_TSS))
                        tnapi = &tp->napi[1];
        }
        coal_now = tnapi->coal_now | rnapi->coal_now;
@@ -10905,22 +11274,20 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
                 * all newer ASIC revisions.
                 */
                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
-                   (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
+                   tg3_flag(tp, CPMU_PRESENT))
                        return 0;
 
                mac_mode = tp->mac_mode &
                           ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
                mac_mode |= MAC_MODE_PORT_INT_LPBACK;
-               if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
+               if (!tg3_flag(tp, 5705_PLUS))
                        mac_mode |= MAC_MODE_LINK_POLARITY;
                if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
                        mac_mode |= MAC_MODE_PORT_MODE_MII;
                else
                        mac_mode |= MAC_MODE_PORT_MODE_GMII;
                tw32(MAC_MODE, mac_mode);
-       } else if (loopback_mode == TG3_PHY_LOOPBACK) {
-               u32 val;
-
+       } else {
                if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
                        tg3_phy_fet_toggle_apd(tp, false);
                        val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
@@ -10968,13 +11335,11 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
                                break;
                        mdelay(1);
                }
-       } else {
-               return -EINVAL;
        }
 
        err = -EIO;
 
-       tx_len = 1514;
+       tx_len = pktsz;
        skb = netdev_alloc_skb(tp->dev, tx_len);
        if (!skb)
                return -ENOMEM;
@@ -10983,9 +11348,58 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
        memcpy(tx_data, tp->dev->dev_addr, 6);
        memset(tx_data + 6, 0x0, 8);
 
-       tw32(MAC_RX_MTU_SIZE, tx_len + 4);
+       tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
+
+       if (loopback_mode == TG3_TSO_LOOPBACK) {
+               struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
+
+               u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
+                             TG3_TSO_TCP_OPT_LEN;
+
+               memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
+                      sizeof(tg3_tso_header));
+               mss = TG3_TSO_MSS;
+
+               val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
+               num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
+
+               /* Set the total length field in the IP header */
+               iph->tot_len = htons((u16)(mss + hdr_len));
+
+               base_flags = (TXD_FLAG_CPU_PRE_DMA |
+                             TXD_FLAG_CPU_POST_DMA);
 
-       for (i = 14; i < tx_len; i++)
+               if (tg3_flag(tp, HW_TSO_1) ||
+                   tg3_flag(tp, HW_TSO_2) ||
+                   tg3_flag(tp, HW_TSO_3)) {
+                       struct tcphdr *th;
+                       val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
+                       th = (struct tcphdr *)&tx_data[val];
+                       th->check = 0;
+               } else
+                       base_flags |= TXD_FLAG_TCPUDP_CSUM;
+
+               if (tg3_flag(tp, HW_TSO_3)) {
+                       mss |= (hdr_len & 0xc) << 12;
+                       if (hdr_len & 0x10)
+                               base_flags |= 0x00000010;
+                       base_flags |= (hdr_len & 0x3e0) << 5;
+               } else if (tg3_flag(tp, HW_TSO_2))
+                       mss |= hdr_len << 9;
+               else if (tg3_flag(tp, HW_TSO_1) ||
+                        GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
+                       mss |= (TG3_TSO_TCP_OPT_LEN << 9);
+               } else {
+                       base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
+               }
+
+               data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
+       } else {
+               num_pkts = 1;
+               data_off = ETH_HLEN;
+       }
+
+       for (i = data_off; i < tx_len; i++)
                tx_data[i] = (u8) (i & 0xff);
 
        map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
@@ -10994,6 +11408,10 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
                return -EIO;
        }
 
+       val = tnapi->tx_prod;
+       tnapi->tx_buffers[val].skb = skb;
+       dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
+
        tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
               rnapi->coal_now);
 
@@ -11001,12 +11419,15 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
 
        rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
 
-       num_pkts = 0;
-
-       tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
+       budget = tg3_tx_avail(tnapi);
+       if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
+                           base_flags | TXD_FLAG_END, mss, 0)) {
+               tnapi->tx_buffers[val].skb = NULL;
+               dev_kfree_skb(skb);
+               return -EIO;
+       }
 
        tnapi->tx_prod++;
-       num_pkts++;
 
        tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
        tr32_mailbox(tnapi->prodmbox);
@@ -11027,7 +11448,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
                        break;
        }
 
-       pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
+       tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, 0);
        dev_kfree_skb(skb);
 
        if (tx_idx != tnapi->tx_prod)
@@ -11036,29 +11457,56 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
        if (rx_idx != rx_start_idx + num_pkts)
                goto out;
 
-       desc = &rnapi->rx_rcb[rx_start_idx];
-       desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
-       opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
-       if (opaque_key != RXD_OPAQUE_RING_STD)
-               goto out;
+       val = data_off;
+       while (rx_idx != rx_start_idx) {
+               desc = &rnapi->rx_rcb[rx_start_idx++];
+               desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
+               opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
 
-       if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
-           (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
-               goto out;
+               if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
+                   (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
+                       goto out;
 
-       rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
-       if (rx_len != tx_len)
-               goto out;
+               rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
+                        - ETH_FCS_LEN;
 
-       rx_skb = tpr->rx_std_buffers[desc_idx].skb;
+               if (loopback_mode != TG3_TSO_LOOPBACK) {
+                       if (rx_len != tx_len)
+                               goto out;
 
-       map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
-       pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
+                       if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
+                               if (opaque_key != RXD_OPAQUE_RING_STD)
+                                       goto out;
+                       } else {
+                               if (opaque_key != RXD_OPAQUE_RING_JUMBO)
+                                       goto out;
+                       }
+               } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
+                          (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
+                           >> RXD_TCPCSUM_SHIFT != 0xffff) {
+                       goto out;
+               }
 
-       for (i = 14; i < tx_len; i++) {
-               if (*(rx_skb->data + i) != (u8) (i & 0xff))
+               if (opaque_key == RXD_OPAQUE_RING_STD) {
+                       rx_skb = tpr->rx_std_buffers[desc_idx].skb;
+                       map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
+                                            mapping);
+               } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
+                       rx_skb = tpr->rx_jmb_buffers[desc_idx].skb;
+                       map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
+                                            mapping);
+               } else
                        goto out;
+
+               pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
+                                           PCI_DMA_FROMDEVICE);
+
+               for (i = data_off; i < rx_len; i++, val++) {
+                       if (*(rx_skb->data + i) != (u8) (val & 0xff))
+                               goto out;
+               }
        }
+
        err = 0;
 
        /* tg3_free_rings will unmap and free the rx_skb */
@@ -11066,10 +11514,13 @@ out:
        return err;
 }
 
-#define TG3_MAC_LOOPBACK_FAILED                1
-#define TG3_PHY_LOOPBACK_FAILED                2
-#define TG3_LOOPBACK_FAILED            (TG3_MAC_LOOPBACK_FAILED |      \
-                                        TG3_PHY_LOOPBACK_FAILED)
+#define TG3_STD_LOOPBACK_FAILED                1
+#define TG3_JMB_LOOPBACK_FAILED                2
+#define TG3_TSO_LOOPBACK_FAILED                4
+
+#define TG3_MAC_LOOPBACK_SHIFT         0
+#define TG3_PHY_LOOPBACK_SHIFT         4
+#define TG3_LOOPBACK_FAILED            0x00000077
 
 static int tg3_test_loopback(struct tg3 *tp)
 {
@@ -11088,11 +11539,20 @@ static int tg3_test_loopback(struct tg3 *tp)
                goto done;
        }
 
+       if (tg3_flag(tp, ENABLE_RSS)) {
+               int i;
+
+               /* Reroute all rx packets to the 1st queue */
+               for (i = MAC_RSS_INDIR_TBL_0;
+                    i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
+                       tw32(i, 0x0);
+       }
+
        /* Turn off gphy autopowerdown. */
        if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
                tg3_phy_toggle_apd(tp, false);
 
-       if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
+       if (tg3_flag(tp, CPMU_PRESENT)) {
                int i;
                u32 status;
 
@@ -11118,10 +11578,14 @@ static int tg3_test_loopback(struct tg3 *tp)
                                  CPMU_CTRL_LINK_AWARE_MODE));
        }
 
-       if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
-               err |= TG3_MAC_LOOPBACK_FAILED;
+       if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_MAC_LOOPBACK))
+               err |= TG3_STD_LOOPBACK_FAILED << TG3_MAC_LOOPBACK_SHIFT;
 
-       if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
+       if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
+           tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_MAC_LOOPBACK))
+               err |= TG3_JMB_LOOPBACK_FAILED << TG3_MAC_LOOPBACK_SHIFT;
+
+       if (tg3_flag(tp, CPMU_PRESENT)) {
                tw32(TG3_CPMU_CTRL, cpmuctrl);
 
                /* Release the mutex */
@@ -11129,9 +11593,18 @@ static int tg3_test_loopback(struct tg3 *tp)
        }
 
        if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
-           !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
-               if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
-                       err |= TG3_PHY_LOOPBACK_FAILED;
+           !tg3_flag(tp, USE_PHYLIB)) {
+               if (tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_PHY_LOOPBACK))
+                       err |= TG3_STD_LOOPBACK_FAILED <<
+                              TG3_PHY_LOOPBACK_SHIFT;
+               if (tg3_flag(tp, TSO_CAPABLE) &&
+                   tg3_run_loopback(tp, ETH_FRAME_LEN, TG3_TSO_LOOPBACK))
+                       err |= TG3_TSO_LOOPBACK_FAILED <<
+                              TG3_PHY_LOOPBACK_SHIFT;
+               if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
+                   tg3_run_loopback(tp, 9000 + ETH_HLEN, TG3_PHY_LOOPBACK))
+                       err |= TG3_JMB_LOOPBACK_FAILED <<
+                              TG3_PHY_LOOPBACK_SHIFT;
        }
 
        /* Re-enable gphy autopowerdown. */
@@ -11149,8 +11622,12 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
 {
        struct tg3 *tp = netdev_priv(dev);
 
-       if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
-               tg3_power_up(tp);
+       if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
+           tg3_power_up(tp)) {
+               etest->flags |= ETH_TEST_FL_FAILED;
+               memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
+               return;
+       }
 
        memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
 
@@ -11176,7 +11653,7 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
                tg3_halt(tp, RESET_KIND_SUSPEND, 1);
                err = tg3_nvram_lock(tp);
                tg3_halt_cpu(tp, RX_CPU_BASE);
-               if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
+               if (!tg3_flag(tp, 5705_PLUS))
                        tg3_halt_cpu(tp, TX_CPU_BASE);
                if (!err)
                        tg3_nvram_unlock(tp);
@@ -11206,7 +11683,7 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
 
                tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
                if (netif_running(dev)) {
-                       tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
+                       tg3_flag_set(tp, INIT_COMPLETE);
                        err2 = tg3_restart_hw(tp, 1);
                        if (!err2)
                                tg3_netif_start(tp);
@@ -11228,7 +11705,7 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
        struct tg3 *tp = netdev_priv(dev);
        int err;
 
-       if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
+       if (tg3_flag(tp, USE_PHYLIB)) {
                struct phy_device *phydev;
                if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
                        return -EAGAIN;
@@ -11247,9 +11724,7 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
                if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
                        break;                  /* We have no PHY */
 
-               if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) ||
-                   ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
-                    !netif_running(dev)))
+               if (!netif_running(dev))
                        return -EAGAIN;
 
                spin_lock_bh(&tp->lock);
@@ -11265,9 +11740,7 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
                if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
                        break;                  /* We have no PHY */
 
-               if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) ||
-                   ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
-                    !netif_running(dev)))
+               if (!netif_running(dev))
                        return -EAGAIN;
 
                spin_lock_bh(&tp->lock);
@@ -11297,7 +11770,7 @@ static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
        u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
        u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
 
-       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
+       if (!tg3_flag(tp, 5705_PLUS)) {
                max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
                max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
                max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
@@ -11364,14 +11837,9 @@ static const struct ethtool_ops tg3_ethtool_ops = {
        .set_ringparam          = tg3_set_ringparam,
        .get_pauseparam         = tg3_get_pauseparam,
        .set_pauseparam         = tg3_set_pauseparam,
-       .get_rx_csum            = tg3_get_rx_csum,
-       .set_rx_csum            = tg3_set_rx_csum,
-       .set_tx_csum            = tg3_set_tx_csum,
-       .set_sg                 = ethtool_op_set_sg,
-       .set_tso                = tg3_set_tso,
        .self_test              = tg3_self_test,
        .get_strings            = tg3_get_strings,
-       .phys_id                = tg3_phys_id,
+       .set_phys_id            = tg3_set_phys_id,
        .get_ethtool_stats      = tg3_get_ethtool_stats,
        .get_coalesce           = tg3_get_coalesce,
        .set_coalesce           = tg3_set_coalesce,
@@ -11416,8 +11884,7 @@ static void __devinit tg3_get_nvram_size(struct tg3 *tp)
 {
        u32 val;
 
-       if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
-           tg3_nvram_read(tp, 0, &val) != 0)
+       if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
                return;
 
        /* Selfboot format */
@@ -11452,19 +11919,19 @@ static void __devinit tg3_get_nvram_info(struct tg3 *tp)
 
        nvcfg1 = tr32(NVRAM_CFG1);
        if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
-               tp->tg3_flags2 |= TG3_FLG2_FLASH;
+               tg3_flag_set(tp, FLASH);
        } else {
                nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
                tw32(NVRAM_CFG1, nvcfg1);
        }
 
-       if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
-           (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+           tg3_flag(tp, 5780_CLASS)) {
                switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
                case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
                        tp->nvram_jedecnum = JEDEC_ATMEL;
                        tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
-                       tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+                       tg3_flag_set(tp, NVRAM_BUFFERED);
                        break;
                case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
                        tp->nvram_jedecnum = JEDEC_ATMEL;
@@ -11473,12 +11940,12 @@ static void __devinit tg3_get_nvram_info(struct tg3 *tp)
                case FLASH_VENDOR_ATMEL_EEPROM:
                        tp->nvram_jedecnum = JEDEC_ATMEL;
                        tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
-                       tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+                       tg3_flag_set(tp, NVRAM_BUFFERED);
                        break;
                case FLASH_VENDOR_ST:
                        tp->nvram_jedecnum = JEDEC_ST;
                        tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
-                       tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+                       tg3_flag_set(tp, NVRAM_BUFFERED);
                        break;
                case FLASH_VENDOR_SAIFUN:
                        tp->nvram_jedecnum = JEDEC_SAIFUN;
@@ -11493,7 +11960,7 @@ static void __devinit tg3_get_nvram_info(struct tg3 *tp)
        } else {
                tp->nvram_jedecnum = JEDEC_ATMEL;
                tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
-               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
        }
 }
 
@@ -11532,29 +11999,29 @@ static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
 
        /* NVRAM protection for TPM */
        if (nvcfg1 & (1 << 27))
-               tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
+               tg3_flag_set(tp, PROTECTED_NVRAM);
 
        switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
        case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
        case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
                tp->nvram_jedecnum = JEDEC_ATMEL;
-               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
                break;
        case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
                tp->nvram_jedecnum = JEDEC_ATMEL;
-               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
-               tp->tg3_flags2 |= TG3_FLG2_FLASH;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
+               tg3_flag_set(tp, FLASH);
                break;
        case FLASH_5752VENDOR_ST_M45PE10:
        case FLASH_5752VENDOR_ST_M45PE20:
        case FLASH_5752VENDOR_ST_M45PE40:
                tp->nvram_jedecnum = JEDEC_ST;
-               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
-               tp->tg3_flags2 |= TG3_FLG2_FLASH;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
+               tg3_flag_set(tp, FLASH);
                break;
        }
 
-       if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
+       if (tg3_flag(tp, FLASH)) {
                tg3_nvram_get_pagesize(tp, nvcfg1);
        } else {
                /* For eeprom, set pagesize to maximum eeprom size */
@@ -11573,7 +12040,7 @@ static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
 
        /* NVRAM protection for TPM */
        if (nvcfg1 & (1 << 27)) {
-               tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
+               tg3_flag_set(tp, PROTECTED_NVRAM);
                protect = 1;
        }
 
@@ -11584,8 +12051,8 @@ static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
        case FLASH_5755VENDOR_ATMEL_FLASH_3:
        case FLASH_5755VENDOR_ATMEL_FLASH_5:
                tp->nvram_jedecnum = JEDEC_ATMEL;
-               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
-               tp->tg3_flags2 |= TG3_FLG2_FLASH;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
+               tg3_flag_set(tp, FLASH);
                tp->nvram_pagesize = 264;
                if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
                    nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
@@ -11602,8 +12069,8 @@ static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
        case FLASH_5752VENDOR_ST_M45PE20:
        case FLASH_5752VENDOR_ST_M45PE40:
                tp->nvram_jedecnum = JEDEC_ST;
-               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
-               tp->tg3_flags2 |= TG3_FLG2_FLASH;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
+               tg3_flag_set(tp, FLASH);
                tp->nvram_pagesize = 256;
                if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
                        tp->nvram_size = (protect ?
@@ -11633,7 +12100,7 @@ static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
        case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
        case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
                tp->nvram_jedecnum = JEDEC_ATMEL;
-               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
                tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
 
                nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
@@ -11644,16 +12111,16 @@ static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
        case FLASH_5755VENDOR_ATMEL_FLASH_2:
        case FLASH_5755VENDOR_ATMEL_FLASH_3:
                tp->nvram_jedecnum = JEDEC_ATMEL;
-               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
-               tp->tg3_flags2 |= TG3_FLG2_FLASH;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
+               tg3_flag_set(tp, FLASH);
                tp->nvram_pagesize = 264;
                break;
        case FLASH_5752VENDOR_ST_M45PE10:
        case FLASH_5752VENDOR_ST_M45PE20:
        case FLASH_5752VENDOR_ST_M45PE40:
                tp->nvram_jedecnum = JEDEC_ST;
-               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
-               tp->tg3_flags2 |= TG3_FLG2_FLASH;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
+               tg3_flag_set(tp, FLASH);
                tp->nvram_pagesize = 256;
                break;
        }
@@ -11667,7 +12134,7 @@ static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
 
        /* NVRAM protection for TPM */
        if (nvcfg1 & (1 << 27)) {
-               tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
+               tg3_flag_set(tp, PROTECTED_NVRAM);
                protect = 1;
        }
 
@@ -11682,9 +12149,9 @@ static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
        case FLASH_5761VENDOR_ATMEL_MDB081D:
        case FLASH_5761VENDOR_ATMEL_MDB161D:
                tp->nvram_jedecnum = JEDEC_ATMEL;
-               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
-               tp->tg3_flags2 |= TG3_FLG2_FLASH;
-               tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
+               tg3_flag_set(tp, FLASH);
+               tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
                tp->nvram_pagesize = 256;
                break;
        case FLASH_5761VENDOR_ST_A_M45PE20:
@@ -11696,8 +12163,8 @@ static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
        case FLASH_5761VENDOR_ST_M_M45PE80:
        case FLASH_5761VENDOR_ST_M_M45PE16:
                tp->nvram_jedecnum = JEDEC_ST;
-               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
-               tp->tg3_flags2 |= TG3_FLG2_FLASH;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
+               tg3_flag_set(tp, FLASH);
                tp->nvram_pagesize = 256;
                break;
        }
@@ -11737,7 +12204,7 @@ static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
 {
        tp->nvram_jedecnum = JEDEC_ATMEL;
-       tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+       tg3_flag_set(tp, NVRAM_BUFFERED);
        tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
 }
 
@@ -11751,7 +12218,7 @@ static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
        case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
        case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
                tp->nvram_jedecnum = JEDEC_ATMEL;
-               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
                tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
 
                nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
@@ -11765,8 +12232,8 @@ static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
        case FLASH_57780VENDOR_ATMEL_AT45DB041D:
        case FLASH_57780VENDOR_ATMEL_AT45DB041B:
                tp->nvram_jedecnum = JEDEC_ATMEL;
-               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
-               tp->tg3_flags2 |= TG3_FLG2_FLASH;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
+               tg3_flag_set(tp, FLASH);
 
                switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
                case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
@@ -11788,8 +12255,8 @@ static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
        case FLASH_5752VENDOR_ST_M45PE20:
        case FLASH_5752VENDOR_ST_M45PE40:
                tp->nvram_jedecnum = JEDEC_ST;
-               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
-               tp->tg3_flags2 |= TG3_FLG2_FLASH;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
+               tg3_flag_set(tp, FLASH);
 
                switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
                case FLASH_5752VENDOR_ST_M45PE10:
@@ -11804,13 +12271,13 @@ static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
                }
                break;
        default:
-               tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
+               tg3_flag_set(tp, NO_NVRAM);
                return;
        }
 
        tg3_nvram_get_pagesize(tp, nvcfg1);
        if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
-               tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
+               tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
 }
 
 
@@ -11824,7 +12291,7 @@ static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
        case FLASH_5717VENDOR_ATMEL_EEPROM:
        case FLASH_5717VENDOR_MICRO_EEPROM:
                tp->nvram_jedecnum = JEDEC_ATMEL;
-               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
                tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
 
                nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
@@ -11838,11 +12305,13 @@ static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
        case FLASH_5717VENDOR_ATMEL_ADB021D:
        case FLASH_5717VENDOR_ATMEL_45USPT:
                tp->nvram_jedecnum = JEDEC_ATMEL;
-               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
-               tp->tg3_flags2 |= TG3_FLG2_FLASH;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
+               tg3_flag_set(tp, FLASH);
 
                switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
                case FLASH_5717VENDOR_ATMEL_MDB021D:
+                       /* Detect size with tg3_nvram_get_size() */
+                       break;
                case FLASH_5717VENDOR_ATMEL_ADB021B:
                case FLASH_5717VENDOR_ATMEL_ADB021D:
                        tp->nvram_size = TG3_NVRAM_SIZE_256KB;
@@ -11863,13 +12332,15 @@ static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
        case FLASH_5717VENDOR_ST_25USPT:
        case FLASH_5717VENDOR_ST_45USPT:
                tp->nvram_jedecnum = JEDEC_ST;
-               tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
-               tp->tg3_flags2 |= TG3_FLG2_FLASH;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
+               tg3_flag_set(tp, FLASH);
 
                switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
                case FLASH_5717VENDOR_ST_M_M25PE20:
-               case FLASH_5717VENDOR_ST_A_M25PE20:
                case FLASH_5717VENDOR_ST_M_M45PE20:
+                       /* Detect size with tg3_nvram_get_size() */
+                       break;
+               case FLASH_5717VENDOR_ST_A_M25PE20:
                case FLASH_5717VENDOR_ST_A_M45PE20:
                        tp->nvram_size = TG3_NVRAM_SIZE_256KB;
                        break;
@@ -11879,13 +12350,125 @@ static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
                }
                break;
        default:
-               tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
+               tg3_flag_set(tp, NO_NVRAM);
                return;
        }
 
        tg3_nvram_get_pagesize(tp, nvcfg1);
        if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
-               tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
+               tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
+}
+
+static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
+{
+       u32 nvcfg1, nvmpinstrp;
+
+       nvcfg1 = tr32(NVRAM_CFG1);
+       nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
+
+       switch (nvmpinstrp) {
+       case FLASH_5720_EEPROM_HD:
+       case FLASH_5720_EEPROM_LD:
+               tp->nvram_jedecnum = JEDEC_ATMEL;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
+
+               nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
+               tw32(NVRAM_CFG1, nvcfg1);
+               if (nvmpinstrp == FLASH_5720_EEPROM_HD)
+                       tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
+               else
+                       tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
+               return;
+       case FLASH_5720VENDOR_M_ATMEL_DB011D:
+       case FLASH_5720VENDOR_A_ATMEL_DB011B:
+       case FLASH_5720VENDOR_A_ATMEL_DB011D:
+       case FLASH_5720VENDOR_M_ATMEL_DB021D:
+       case FLASH_5720VENDOR_A_ATMEL_DB021B:
+       case FLASH_5720VENDOR_A_ATMEL_DB021D:
+       case FLASH_5720VENDOR_M_ATMEL_DB041D:
+       case FLASH_5720VENDOR_A_ATMEL_DB041B:
+       case FLASH_5720VENDOR_A_ATMEL_DB041D:
+       case FLASH_5720VENDOR_M_ATMEL_DB081D:
+       case FLASH_5720VENDOR_A_ATMEL_DB081D:
+       case FLASH_5720VENDOR_ATMEL_45USPT:
+               tp->nvram_jedecnum = JEDEC_ATMEL;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
+               tg3_flag_set(tp, FLASH);
+
+               switch (nvmpinstrp) {
+               case FLASH_5720VENDOR_M_ATMEL_DB021D:
+               case FLASH_5720VENDOR_A_ATMEL_DB021B:
+               case FLASH_5720VENDOR_A_ATMEL_DB021D:
+                       tp->nvram_size = TG3_NVRAM_SIZE_256KB;
+                       break;
+               case FLASH_5720VENDOR_M_ATMEL_DB041D:
+               case FLASH_5720VENDOR_A_ATMEL_DB041B:
+               case FLASH_5720VENDOR_A_ATMEL_DB041D:
+                       tp->nvram_size = TG3_NVRAM_SIZE_512KB;
+                       break;
+               case FLASH_5720VENDOR_M_ATMEL_DB081D:
+               case FLASH_5720VENDOR_A_ATMEL_DB081D:
+                       tp->nvram_size = TG3_NVRAM_SIZE_1MB;
+                       break;
+               default:
+                       tp->nvram_size = TG3_NVRAM_SIZE_128KB;
+                       break;
+               }
+               break;
+       case FLASH_5720VENDOR_M_ST_M25PE10:
+       case FLASH_5720VENDOR_M_ST_M45PE10:
+       case FLASH_5720VENDOR_A_ST_M25PE10:
+       case FLASH_5720VENDOR_A_ST_M45PE10:
+       case FLASH_5720VENDOR_M_ST_M25PE20:
+       case FLASH_5720VENDOR_M_ST_M45PE20:
+       case FLASH_5720VENDOR_A_ST_M25PE20:
+       case FLASH_5720VENDOR_A_ST_M45PE20:
+       case FLASH_5720VENDOR_M_ST_M25PE40:
+       case FLASH_5720VENDOR_M_ST_M45PE40:
+       case FLASH_5720VENDOR_A_ST_M25PE40:
+       case FLASH_5720VENDOR_A_ST_M45PE40:
+       case FLASH_5720VENDOR_M_ST_M25PE80:
+       case FLASH_5720VENDOR_M_ST_M45PE80:
+       case FLASH_5720VENDOR_A_ST_M25PE80:
+       case FLASH_5720VENDOR_A_ST_M45PE80:
+       case FLASH_5720VENDOR_ST_25USPT:
+       case FLASH_5720VENDOR_ST_45USPT:
+               tp->nvram_jedecnum = JEDEC_ST;
+               tg3_flag_set(tp, NVRAM_BUFFERED);
+               tg3_flag_set(tp, FLASH);
+
+               switch (nvmpinstrp) {
+               case FLASH_5720VENDOR_M_ST_M25PE20:
+               case FLASH_5720VENDOR_M_ST_M45PE20:
+               case FLASH_5720VENDOR_A_ST_M25PE20:
+               case FLASH_5720VENDOR_A_ST_M45PE20:
+                       tp->nvram_size = TG3_NVRAM_SIZE_256KB;
+                       break;
+               case FLASH_5720VENDOR_M_ST_M25PE40:
+               case FLASH_5720VENDOR_M_ST_M45PE40:
+               case FLASH_5720VENDOR_A_ST_M25PE40:
+               case FLASH_5720VENDOR_A_ST_M45PE40:
+                       tp->nvram_size = TG3_NVRAM_SIZE_512KB;
+                       break;
+               case FLASH_5720VENDOR_M_ST_M25PE80:
+               case FLASH_5720VENDOR_M_ST_M45PE80:
+               case FLASH_5720VENDOR_A_ST_M25PE80:
+               case FLASH_5720VENDOR_A_ST_M45PE80:
+                       tp->nvram_size = TG3_NVRAM_SIZE_1MB;
+                       break;
+               default:
+                       tp->nvram_size = TG3_NVRAM_SIZE_128KB;
+                       break;
+               }
+               break;
+       default:
+               tg3_flag_set(tp, NO_NVRAM);
+               return;
+       }
+
+       tg3_nvram_get_pagesize(tp, nvcfg1);
+       if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
+               tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
 }
 
 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
@@ -11905,7 +12488,7 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
-               tp->tg3_flags |= TG3_FLAG_NVRAM;
+               tg3_flag_set(tp, NVRAM);
 
                if (tg3_nvram_lock(tp)) {
                        netdev_warn(tp->dev,
@@ -11935,6 +12518,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
                else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
                        tg3_get_5717_nvram_info(tp);
+               else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
+                       tg3_get_5720_nvram_info(tp);
                else
                        tg3_get_nvram_info(tp);
 
@@ -11945,7 +12530,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
                tg3_nvram_unlock(tp);
 
        } else {
-               tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
+               tg3_flag_clear(tp, NVRAM);
+               tg3_flag_clear(tp, NVRAM_BUFFERED);
 
                tg3_get_eeprom_size(tp);
        }
@@ -12128,7 +12714,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
                        nvram_cmd |= NVRAM_CMD_LAST;
 
                if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
-                   !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
+                   !tg3_flag(tp, 5755_PLUS) &&
                    (tp->nvram_jedecnum == JEDEC_ST) &&
                    (nvram_cmd & NVRAM_CMD_FIRST)) {
 
@@ -12138,7 +12724,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
 
                                break;
                }
-               if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
+               if (!tg3_flag(tp, FLASH)) {
                        /* We always do complete word writes to eeprom. */
                        nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
                }
@@ -12154,13 +12740,13 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
 {
        int ret;
 
-       if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
+       if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
                tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
                       ~GRC_LCLCTRL_GPIO_OUTPUT1);
                udelay(40);
        }
 
-       if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
+       if (!tg3_flag(tp, NVRAM)) {
                ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
        } else {
                u32 grc_mode;
@@ -12170,16 +12756,13 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
                        return ret;
 
                tg3_enable_nvram_access(tp);
-               if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
-                   !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
+               if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
                        tw32(NVRAM_WRITE1, 0x406);
 
                grc_mode = tr32(GRC_MODE);
                tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
 
-               if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
-                       !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
-
+               if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
                        ret = tg3_nvram_write_block_buffered(tp, offset, len,
                                buf);
                } else {
@@ -12194,7 +12777,7 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
                tg3_nvram_unlock(tp);
        }
 
-       if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
+       if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
                tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
                udelay(40);
        }
@@ -12288,47 +12871,27 @@ static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
 {
        u32 val;
-       u16 pmcsr;
-
-       /* On some early chips the SRAM cannot be accessed in D3hot state,
-        * so need make sure we're in D0.
-        */
-       pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
-       pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
-       pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
-       msleep(1);
-
-       /* Make sure register accesses (indirect or otherwise)
-        * will function correctly.
-        */
-       pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
-                              tp->misc_host_ctrl);
-
-       /* The memory arbiter has to be enabled in order for SRAM accesses
-        * to succeed.  Normally on powerup the tg3 chip firmware will make
-        * sure it is enabled, but other entities such as system netboot
-        * code might disable it.
-        */
-       val = tr32(MEMARB_MODE);
-       tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
 
        tp->phy_id = TG3_PHY_ID_INVALID;
        tp->led_ctrl = LED_CTRL_MODE_PHY_1;
 
        /* Assume an onboard device and WOL capable by default.  */
-       tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
+       tg3_flag_set(tp, EEPROM_WRITE_PROT);
+       tg3_flag_set(tp, WOL_CAP);
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
                if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
-                       tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
-                       tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
+                       tg3_flag_clear(tp, EEPROM_WRITE_PROT);
+                       tg3_flag_set(tp, IS_NIC);
                }
                val = tr32(VCPU_CFGSHDW);
                if (val & VCPU_CFGSHDW_ASPM_DBNC)
-                       tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
+                       tg3_flag_set(tp, ASPM_WORKAROUND);
                if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
-                   (val & VCPU_CFGSHDW_WOL_MAGPKT))
-                       tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
+                   (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
+                       tg3_flag_set(tp, WOL_ENABLE);
+                       device_set_wakeup_enable(&tp->pdev->dev, true);
+               }
                goto done;
        }
 
@@ -12343,9 +12906,9 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
 
                tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
                ver >>= NIC_SRAM_DATA_VER_SHIFT;
-               if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
-                   (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
-                   (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
+                   GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
+                   GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 &&
                    (ver > 0) && (ver < 0x100))
                        tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
 
@@ -12369,13 +12932,13 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
 
                tp->phy_id = eeprom_phy_id;
                if (eeprom_phy_serdes) {
-                       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
+                       if (!tg3_flag(tp, 5705_PLUS))
                                tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
                        else
                                tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
                }
 
-               if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
+               if (tg3_flag(tp, 5750_PLUS))
                        led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
                                    SHASTA_EXT_LED_MODE_MASK);
                else
@@ -12435,34 +12998,36 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
                        tp->led_ctrl = LED_CTRL_MODE_PHY_1;
 
                if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
-                       tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
+                       tg3_flag_set(tp, EEPROM_WRITE_PROT);
                        if ((tp->pdev->subsystem_vendor ==
                             PCI_VENDOR_ID_ARIMA) &&
                            (tp->pdev->subsystem_device == 0x205a ||
                             tp->pdev->subsystem_device == 0x2063))
-                               tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
+                               tg3_flag_clear(tp, EEPROM_WRITE_PROT);
                } else {
-                       tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
-                       tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
+                       tg3_flag_clear(tp, EEPROM_WRITE_PROT);
+                       tg3_flag_set(tp, IS_NIC);
                }
 
                if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
-                       tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
-                       if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
-                               tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
+                       tg3_flag_set(tp, ENABLE_ASF);
+                       if (tg3_flag(tp, 5750_PLUS))
+                               tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
                }
 
                if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
-                       (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
-                       tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
+                   tg3_flag(tp, 5750_PLUS))
+                       tg3_flag_set(tp, ENABLE_APE);
 
                if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
                    !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
-                       tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
+                       tg3_flag_clear(tp, WOL_CAP);
 
-               if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
-                   (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
-                       tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
+               if (tg3_flag(tp, WOL_CAP) &&
+                   (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
+        &