drivers/net: Convert unbounded kzalloc calls to kcalloc
[linux-2.6.git] / drivers / net / tg3.c
index 0fa7688..bc3af78 100644 (file)
@@ -18,6 +18,7 @@
 
 #include <linux/module.h>
 #include <linux/moduleparam.h>
+#include <linux/stringify.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/compiler.h>
 #include "tg3.h"
 
 #define DRV_MODULE_NAME                "tg3"
-#define DRV_MODULE_VERSION     "3.108"
-#define DRV_MODULE_RELDATE     "February 17, 2010"
+#define TG3_MAJ_NUM                    3
+#define TG3_MIN_NUM                    113
+#define DRV_MODULE_VERSION     \
+       __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
+#define DRV_MODULE_RELDATE     "August 2, 2010"
 
 #define TG3_DEF_MAC_MODE       0
 #define TG3_DEF_RX_MODE                0
 #define TG3_DEF_RX_RING_PENDING                200
 #define TG3_RX_JUMBO_RING_SIZE         256
 #define TG3_DEF_RX_JUMBO_RING_PENDING  100
-#define TG3_RSS_INDIR_TBL_SIZE 128
+#define TG3_RSS_INDIR_TBL_SIZE         128
 
 /* Do not place this n-ring entries value into the tp struct itself,
  * we really want to expose these constants to GCC so that modulo et
                                 TG3_TX_RING_SIZE)
 #define NEXT_TX(N)             (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 
+#define TG3_RX_DMA_ALIGN               16
+#define TG3_RX_HEADROOM                        ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
+
 #define TG3_DMA_BYTE_ENAB              64
 
 #define TG3_RX_STD_DMA_SZ              1536
 #define TG3_RX_JMB_BUFF_RING_SIZE \
        (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 
+/* Due to a hardware bug, the 5701 can only DMA to memory addresses
+ * that are at least dword aligned when used in PCIX mode.  The driver
+ * works around this bug by double copying the packet.  This workaround
+ * is built into the normal double copy length check for efficiency.
+ *
+ * However, the double copy is only necessary on those architectures
+ * where unaligned memory accesses are inefficient.  For those architectures
+ * where unaligned memory accesses incur little penalty, we can reintegrate
+ * the 5701 in the normal rx path.  Doing so saves a device structure
+ * dereference by hardcoding the double copy threshold in place.
+ */
+#define TG3_RX_COPY_THRESHOLD          256
+#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
+       #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
+#else
+       #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
+#endif
+
 /* minimum number of free TX descriptors required to wake up TX process */
 #define TG3_TX_WAKEUP_THRESH(tnapi)            ((tnapi)->tx_pending / 4)
 
 
 #define TG3_NUM_TEST           6
 
+#define TG3_FW_UPDATE_TIMEOUT_SEC      5
+
 #define FIRMWARE_TG3           "tigon/tg3.bin"
 #define FIRMWARE_TG3TSO                "tigon/tg3_tso.bin"
 #define FIRMWARE_TG3TSO5       "tigon/tg3_tso5.bin"
@@ -167,8 +194,6 @@ MODULE_FIRMWARE(FIRMWARE_TG3);
 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 
-#define TG3_RSS_MIN_NUM_MSIX_VECS      2
-
 static int tg3_debug = -1;     /* -1 == use TG3_DEF_MSG_ENABLE as value */
 module_param(tg3_debug, int, 0);
 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
@@ -196,12 +221,9 @@ static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
-       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
-       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
-       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
@@ -249,6 +271,7 @@ static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
+       {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
        {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
        {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
        {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
@@ -360,7 +383,7 @@ static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 
 static u32 tg3_read32(struct tg3 *tp, u32 off)
 {
-       return (readl(tp->regs + off));
+       return readl(tp->regs + off);
 }
 
 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
@@ -370,7 +393,7 @@ static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 
 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 {
-       return (readl(tp->aperegs + off));
+       return readl(tp->aperegs + off);
 }
 
 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
@@ -488,7 +511,7 @@ static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 
 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 {
-       return (readl(tp->regs + off + GRCMBOX_BASE));
+       return readl(tp->regs + off + GRCMBOX_BASE);
 }
 
 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
@@ -496,16 +519,16 @@ static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
        writel(val, tp->regs + off + GRCMBOX_BASE);
 }
 
-#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
+#define tw32_mailbox(reg, val)         tp->write32_mbox(tp, reg, val)
 #define tw32_mailbox_f(reg, val)       tw32_mailbox_flush(tp, (reg), (val))
-#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
-#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
-#define tr32_mailbox(reg)      tp->read32_mbox(tp, reg)
+#define tw32_rx_mbox(reg, val)         tp->write32_rx_mbox(tp, reg, val)
+#define tw32_tx_mbox(reg, val)         tp->write32_tx_mbox(tp, reg, val)
+#define tr32_mailbox(reg)              tp->read32_mbox(tp, reg)
 
-#define tw32(reg,val)          tp->write32(tp, reg, val)
-#define tw32_f(reg,val)                _tw32_flush(tp,(reg),(val), 0)
-#define tw32_wait_f(reg,val,us)        _tw32_flush(tp,(reg),(val), (us))
-#define tr32(reg)              tp->read32(tp, reg)
+#define tw32(reg, val)                 tp->write32(tp, reg, val)
+#define tw32_f(reg, val)               _tw32_flush(tp, (reg), (val), 0)
+#define tw32_wait_f(reg, val, us)      _tw32_flush(tp, (reg), (val), (us))
+#define tr32(reg)                      tp->read32(tp, reg)
 
 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 {
@@ -562,37 +585,50 @@ static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 static void tg3_ape_lock_init(struct tg3 *tp)
 {
        int i;
+       u32 regbase;
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
+               regbase = TG3_APE_LOCK_GRANT;
+       else
+               regbase = TG3_APE_PER_LOCK_GRANT;
 
        /* Make sure the driver hasn't any stale locks. */
        for (i = 0; i < 8; i++)
-               tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
-                               APE_LOCK_GRANT_DRIVER);
+               tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 }
 
 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 {
        int i, off;
        int ret = 0;
-       u32 status;
+       u32 status, req, gnt;
 
        if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
                return 0;
 
        switch (locknum) {
-               case TG3_APE_LOCK_GRC:
-               case TG3_APE_LOCK_MEM:
-                       break;
-               default:
-                       return -EINVAL;
+       case TG3_APE_LOCK_GRC:
+       case TG3_APE_LOCK_MEM:
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
+               req = TG3_APE_LOCK_REQ;
+               gnt = TG3_APE_LOCK_GRANT;
+       } else {
+               req = TG3_APE_PER_LOCK_REQ;
+               gnt = TG3_APE_PER_LOCK_GRANT;
        }
 
        off = 4 * locknum;
 
-       tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
+       tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 
        /* Wait for up to 1 millisecond to acquire lock. */
        for (i = 0; i < 100; i++) {
-               status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
+               status = tg3_ape_read32(tp, gnt + off);
                if (status == APE_LOCK_GRANT_DRIVER)
                        break;
                udelay(10);
@@ -600,7 +636,7 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum)
 
        if (status != APE_LOCK_GRANT_DRIVER) {
                /* Revoke the lock request. */
-               tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
+               tg3_ape_write32(tp, gnt + off,
                                APE_LOCK_GRANT_DRIVER);
 
                ret = -EBUSY;
@@ -611,21 +647,25 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum)
 
 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 {
-       int off;
+       u32 gnt;
 
        if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
                return;
 
        switch (locknum) {
-               case TG3_APE_LOCK_GRC:
-               case TG3_APE_LOCK_MEM:
-                       break;
-               default:
-                       return;
+       case TG3_APE_LOCK_GRC:
+       case TG3_APE_LOCK_MEM:
+               break;
+       default:
+               return;
        }
 
-       off = 4 * locknum;
-       tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
+               gnt = TG3_APE_LOCK_GRANT;
+       else
+               gnt = TG3_APE_PER_LOCK_GRANT;
+
+       tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 }
 
 static void tg3_disable_ints(struct tg3 *tp)
@@ -651,6 +691,7 @@ static void tg3_enable_ints(struct tg3 *tp)
        tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
        for (i = 0; i < tp->irq_cnt; i++) {
                struct tg3_napi *tnapi = &tp->napi[i];
+
                tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
                if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
                        tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
@@ -838,7 +879,7 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
        unsigned int loops;
        int ret;
 
-       if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
+       if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
            (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
                return 0;
 
@@ -1045,14 +1086,11 @@ static int tg3_mdio_init(struct tg3 *tp)
        u32 reg;
        struct phy_device *phydev;
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
-               u32 funcnum, is_serdes;
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
+               u32 is_serdes;
 
-               funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
-               if (funcnum)
-                       tp->phy_addr = 2;
-               else
-                       tp->phy_addr = 1;
+               tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
 
                if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
                        is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
@@ -1098,7 +1136,7 @@ static int tg3_mdio_init(struct tg3 *tp)
 
        i = mdiobus_register(tp->mdio_bus);
        if (i) {
-               netdev_warn(tp->dev, "mdiobus_reg failed (0x%x)\n", i);
+               dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
                mdiobus_free(tp->mdio_bus);
                return i;
        }
@@ -1106,7 +1144,7 @@ static int tg3_mdio_init(struct tg3 *tp)
        phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 
        if (!phydev || !phydev->drv) {
-               netdev_warn(tp->dev, "No PHY devices\n");
+               dev_warn(&tp->pdev->dev, "No PHY devices\n");
                mdiobus_unregister(tp->mdio_bus);
                mdiobus_free(tp->mdio_bus);
                return -ENODEV;
@@ -1137,7 +1175,7 @@ static int tg3_mdio_init(struct tg3 *tp)
        case PHY_ID_BCMAC131:
                phydev->interface = PHY_INTERFACE_MODE_MII;
                phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
-               tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
+               tp->phy_flags |= TG3_PHYFLG_IS_FET;
                break;
        }
 
@@ -1230,7 +1268,7 @@ static void tg3_ump_link_report(struct tg3 *tp)
        tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
 
        val = 0;
-       if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
+       if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
                if (!tg3_readphy(tp, MII_CTRL1000, &reg))
                        val = reg << 16;
                if (!tg3_readphy(tp, MII_STAT1000, &reg))
@@ -1338,7 +1376,7 @@ static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
 
        if (autoneg == AUTONEG_ENABLE &&
            (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
-               if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
+               if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
                        flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
                else
                        flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
@@ -1437,7 +1475,7 @@ static void tg3_adjust_link(struct net_device *dev)
            phydev->speed != tp->link_config.active_speed ||
            phydev->duplex != tp->link_config.active_duplex ||
            oldflowctrl != tp->link_config.active_flowctrl)
-           linkmesg = 1;
+               linkmesg = 1;
 
        tp->link_config.active_speed = phydev->speed;
        tp->link_config.active_duplex = phydev->duplex;
@@ -1452,7 +1490,7 @@ static int tg3_phy_init(struct tg3 *tp)
 {
        struct phy_device *phydev;
 
-       if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
+       if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
                return 0;
 
        /* Bring the PHY back to a known state. */
@@ -1464,7 +1502,7 @@ static int tg3_phy_init(struct tg3 *tp)
        phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
                             phydev->dev_flags, phydev->interface);
        if (IS_ERR(phydev)) {
-               netdev_err(tp->dev, "Could not attach to PHY\n");
+               dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
                return PTR_ERR(phydev);
        }
 
@@ -1472,7 +1510,7 @@ static int tg3_phy_init(struct tg3 *tp)
        switch (phydev->interface) {
        case PHY_INTERFACE_MODE_GMII:
        case PHY_INTERFACE_MODE_RGMII:
-               if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
+               if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
                        phydev->supported &= (PHY_GBIT_FEATURES |
                                              SUPPORTED_Pause |
                                              SUPPORTED_Asym_Pause);
@@ -1489,7 +1527,7 @@ static int tg3_phy_init(struct tg3 *tp)
                return -EINVAL;
        }
 
-       tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
+       tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
 
        phydev->advertising = phydev->supported;
 
@@ -1500,13 +1538,13 @@ static void tg3_phy_start(struct tg3 *tp)
 {
        struct phy_device *phydev;
 
-       if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
+       if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
                return;
 
        phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 
-       if (tp->link_config.phy_is_low_power) {
-               tp->link_config.phy_is_low_power = 0;
+       if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
+               tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
                phydev->speed = tp->link_config.orig_speed;
                phydev->duplex = tp->link_config.orig_duplex;
                phydev->autoneg = tp->link_config.orig_autoneg;
@@ -1520,7 +1558,7 @@ static void tg3_phy_start(struct tg3 *tp)
 
 static void tg3_phy_stop(struct tg3 *tp)
 {
-       if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
+       if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
                return;
 
        phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
@@ -1528,16 +1566,21 @@ static void tg3_phy_stop(struct tg3 *tp)
 
 static void tg3_phy_fini(struct tg3 *tp)
 {
-       if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
+       if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
                phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
-               tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
+               tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
        }
 }
 
-static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
+static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
 {
-       tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
-       tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
+       int err;
+
+       err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
+       if (!err)
+               err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
+
+       return err;
 }
 
 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
@@ -1565,11 +1608,12 @@ static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
        u32 reg;
 
        if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
-               (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
-            (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
+           ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
+            (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
                return;
 
-       if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
+       if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
                tg3_phy_fet_toggle_apd(tp, enable);
                return;
        }
@@ -1600,10 +1644,10 @@ static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
        u32 phy;
 
        if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
-           (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
+           (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
                return;
 
-       if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
+       if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
                u32 ephy;
 
                if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
@@ -1639,7 +1683,7 @@ static void tg3_phy_set_wirespeed(struct tg3 *tp)
 {
        u32 val;
 
-       if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
+       if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
                return;
 
        if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
@@ -1698,7 +1742,7 @@ static int tg3_wait_macro_done(struct tg3 *tp)
        while (limit--) {
                u32 tmp32;
 
-               if (!tg3_readphy(tp, 0x16, &tmp32)) {
+               if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
                        if ((tmp32 & 0x1000) == 0)
                                break;
                }
@@ -1724,13 +1768,13 @@ static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 
                tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
                             (chan * 0x2000) | 0x0200);
-               tg3_writephy(tp, 0x16, 0x0002);
+               tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
 
                for (i = 0; i < 6; i++)
                        tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
                                     test_pat[chan][i]);
 
-               tg3_writephy(tp, 0x16, 0x0202);
+               tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
                if (tg3_wait_macro_done(tp)) {
                        *resetp = 1;
                        return -EBUSY;
@@ -1738,13 +1782,13 @@ static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 
                tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
                             (chan * 0x2000) | 0x0200);
-               tg3_writephy(tp, 0x16, 0x0082);
+               tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
                if (tg3_wait_macro_done(tp)) {
                        *resetp = 1;
                        return -EBUSY;
                }
 
-               tg3_writephy(tp, 0x16, 0x0802);
+               tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
                if (tg3_wait_macro_done(tp)) {
                        *resetp = 1;
                        return -EBUSY;
@@ -1784,10 +1828,10 @@ static int tg3_phy_reset_chanpat(struct tg3 *tp)
 
                tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
                             (chan * 0x2000) | 0x0200);
-               tg3_writephy(tp, 0x16, 0x0002);
+               tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
                for (i = 0; i < 6; i++)
                        tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
-               tg3_writephy(tp, 0x16, 0x0202);
+               tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
                if (tg3_wait_macro_done(tp))
                        return -EBUSY;
        }
@@ -1833,8 +1877,7 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
                tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 
                /* Block the PHY control access.  */
-               tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
-               tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
+               tg3_phydsp_write(tp, 0x8005, 0x0800);
 
                err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
                if (!err)
@@ -1845,18 +1888,16 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
        if (err)
                return err;
 
-       tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
-       tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
+       tg3_phydsp_write(tp, 0x8005, 0x0000);
 
        tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
-       tg3_writephy(tp, 0x16, 0x0000);
+       tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
                /* Set Extended packet length bit for jumbo frames */
                tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
-       }
-       else {
+       } else {
                tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
        }
 
@@ -1941,44 +1982,39 @@ static int tg3_phy_reset(struct tg3 *tp)
                }
        }
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
-           (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
+       if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
+           (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
                return 0;
 
        tg3_phy_apply_otp(tp);
 
-       if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
+       if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
                tg3_phy_toggle_apd(tp, true);
        else
                tg3_phy_toggle_apd(tp, false);
 
 out:
-       if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
+       if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
                tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
-               tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
-               tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
-               tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
-               tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
+               tg3_phydsp_write(tp, 0x201f, 0x2aaa);
+               tg3_phydsp_write(tp, 0x000a, 0x0323);
                tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
        }
-       if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
-               tg3_writephy(tp, 0x1c, 0x8d68);
-               tg3_writephy(tp, 0x1c, 0x8d68);
+       if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
+               tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
+               tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
        }
-       if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
+       if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
                tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
-               tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
-               tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
-               tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
-               tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
-               tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
-               tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
+               tg3_phydsp_write(tp, 0x000a, 0x310b);
+               tg3_phydsp_write(tp, 0x201f, 0x9506);
+               tg3_phydsp_write(tp, 0x401f, 0x14e2);
                tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
-       }
-       else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
+       } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
                tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
                tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
-               if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
+               if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
                        tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
                        tg3_writephy(tp, MII_TG3_TEST1,
                                     MII_TG3_TEST1_TRIM_EN | 0x4);
@@ -2007,8 +2043,8 @@ out:
                u32 phy_reg;
 
                if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
-                   tg3_writephy(tp, MII_TG3_EXT_CTRL,
-                                phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
+                       tg3_writephy(tp, MII_TG3_EXT_CTRL,
+                                    phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
        }
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
@@ -2027,6 +2063,7 @@ static void tg3_frob_aux_power(struct tg3 *tp)
 
        /* The GPIOs do something completely different on 57765. */
        if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
                return;
 
@@ -2162,7 +2199,7 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
 {
        u32 val;
 
-       if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
+       if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
                        u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
                        u32 serdes_cfg = tr32(MAC_SERDES_CFG);
@@ -2181,7 +2218,7 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
                tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
                udelay(40);
                return;
-       } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
+       } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
                u32 phytest;
                if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
                        u32 phy;
@@ -2218,7 +2255,7 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
            (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
-            (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
+            (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
                return;
 
        if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
@@ -2521,14 +2558,14 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
 
        if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
                do_low_power = false;
-               if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
-                   !tp->link_config.phy_is_low_power) {
+               if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
+                   !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
                        struct phy_device *phydev;
                        u32 phyid, advertising;
 
                        phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 
-                       tp->link_config.phy_is_low_power = 1;
+                       tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
 
                        tp->link_config.orig_speed = phydev->speed;
                        tp->link_config.orig_duplex = phydev->duplex;
@@ -2567,14 +2604,14 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
        } else {
                do_low_power = true;
 
-               if (tp->link_config.phy_is_low_power == 0) {
-                       tp->link_config.phy_is_low_power = 1;
+               if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
+                       tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
                        tp->link_config.orig_speed = tp->link_config.speed;
                        tp->link_config.orig_duplex = tp->link_config.duplex;
                        tp->link_config.orig_autoneg = tp->link_config.autoneg;
                }
 
-               if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
+               if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
                        tp->link_config.speed = SPEED_10;
                        tp->link_config.duplex = DUPLEX_HALF;
                        tp->link_config.autoneg = AUTONEG_ENABLE;
@@ -2607,13 +2644,13 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
        if (device_should_wake) {
                u32 mac_mode;
 
-               if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
+               if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
                        if (do_low_power) {
                                tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
                                udelay(40);
                        }
 
-                       if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
+                       if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
                                mac_mode = MAC_MODE_PORT_MODE_GMII;
                        else
                                mac_mode = MAC_MODE_PORT_MODE_MII;
@@ -2781,7 +2818,7 @@ static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8
                break;
 
        default:
-               if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
+               if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
                        *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
                                 SPEED_10;
                        *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
@@ -2799,7 +2836,7 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
        u32 new_adv;
        int i;
 
-       if (tp->link_config.phy_is_low_power) {
+       if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
                /* Entering low power mode.  Disable gigabit and
                 * 100baseT advertisements.
                 */
@@ -2812,7 +2849,7 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
 
                tg3_writephy(tp, MII_ADVERTISE, new_adv);
        } else if (tp->link_config.speed == SPEED_INVALID) {
-               if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
+               if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
                        tp->link_config.advertising &=
                                ~(ADVERTISED_1000baseT_Half |
                                  ADVERTISED_1000baseT_Full);
@@ -2838,7 +2875,7 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
                                new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
                        if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
                                new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
-                       if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
+                       if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
                            (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
                                new_adv |= (MII_TG3_CTRL_AS_MASTER |
@@ -2940,20 +2977,11 @@ static int tg3_init_5401phy_dsp(struct tg3 *tp)
        /* Set Extended packet length bit */
        err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
 
-       err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
-       err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
-
-       err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
-       err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
-
-       err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
-       err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
-
-       err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
-       err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
-
-       err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
-       err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
+       err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
+       err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
+       err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
+       err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
+       err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
 
        udelay(40);
 
@@ -2978,7 +3006,7 @@ static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
 
        if ((adv_reg & all_mask) != all_mask)
                return 0;
-       if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
+       if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
                u32 tg3_ctrl;
 
                all_mask = 0;
@@ -3106,18 +3134,18 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
                   tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
                /* 5701 {A0,B0} CRC bug workaround */
                tg3_writephy(tp, 0x15, 0x0a75);
-               tg3_writephy(tp, 0x1c, 0x8c68);
-               tg3_writephy(tp, 0x1c, 0x8d68);
-               tg3_writephy(tp, 0x1c, 0x8c68);
+               tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
+               tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
+               tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
        }
 
        /* Clear pending interrupts... */
        tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
        tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
 
-       if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
+       if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
                tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
-       else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
+       else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
                tg3_writephy(tp, MII_TG3_IMASK, ~0);
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
@@ -3133,7 +3161,7 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
        current_speed = SPEED_INVALID;
        current_duplex = DUPLEX_INVALID;
 
-       if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
+       if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
                u32 val;
 
                tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
@@ -3209,7 +3237,7 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
        }
 
 relink:
-       if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
+       if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
                u32 tmp;
 
                tg3_phy_copper_begin(tp);
@@ -3227,7 +3255,7 @@ relink:
                        tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
                else
                        tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
-       } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
+       } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
                tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
        else
                tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
@@ -3425,7 +3453,7 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
        ap->rxconfig = rx_cfg_reg;
        ret = ANEG_OK;
 
-       switch(ap->state) {
+       switch (ap->state) {
        case ANEG_STATE_UNKNOWN:
                if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
                        ap->state = ANEG_STATE_AN_ENABLE;
@@ -3463,11 +3491,10 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
                /* fallthru */
        case ANEG_STATE_RESTART:
                delta = ap->cur_time - ap->link_time;
-               if (delta > ANEG_STATE_SETTLE_TIME) {
+               if (delta > ANEG_STATE_SETTLE_TIME)
                        ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
-               } else {
+               else
                        ret = ANEG_TIMER_ENAB;
-               }
                break;
 
        case ANEG_STATE_DISABLE_LINK_OK:
@@ -3491,9 +3518,8 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
                break;
 
        case ANEG_STATE_ABILITY_DETECT:
-               if (ap->ability_match != 0 && ap->rxconfig != 0) {
+               if (ap->ability_match != 0 && ap->rxconfig != 0)
                        ap->state = ANEG_STATE_ACK_DETECT_INIT;
-               }
                break;
 
        case ANEG_STATE_ACK_DETECT_INIT:
@@ -3780,7 +3806,7 @@ static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
                expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
 
        if (sg_dig_ctrl != expected_sg_dig_ctrl) {
-               if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
+               if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
                    tp->serdes_counter &&
                    ((mac_status & (MAC_STATUS_PCS_SYNCED |
                                    MAC_STATUS_RCVD_CFG)) ==
@@ -3797,7 +3823,7 @@ restart_autoneg:
                tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
 
                tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
-               tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
+               tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
        } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
                                 MAC_STATUS_SIGNAL_DET)) {
                sg_dig_status = tr32(SG_DIG_STATUS);
@@ -3820,7 +3846,7 @@ restart_autoneg:
                        tg3_setup_flow_control(tp, local_adv, remote_adv);
                        current_link_up = 1;
                        tp->serdes_counter = 0;
-                       tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
+                       tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
                } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
                        if (tp->serdes_counter)
                                tp->serdes_counter--;
@@ -3847,8 +3873,8 @@ restart_autoneg:
                                    !(mac_status & MAC_STATUS_RCVD_CFG)) {
                                        tg3_setup_flow_control(tp, 0, 0);
                                        current_link_up = 1;
-                                       tp->tg3_flags2 |=
-                                               TG3_FLG2_PARALLEL_DETECT;
+                                       tp->phy_flags |=
+                                               TG3_PHYFLG_PARALLEL_DETECT;
                                        tp->serdes_counter =
                                                SERDES_PARALLEL_DET_TIMEOUT;
                                } else
@@ -3857,7 +3883,7 @@ restart_autoneg:
                }
        } else {
                tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
-               tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
+               tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
        }
 
 out:
@@ -4074,7 +4100,7 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
        err |= tg3_readphy(tp, MII_BMCR, &bmcr);
 
        if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
-           (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
+           (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
                /* do nothing, just check for link up at the end */
        } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
                u32 adv, new_adv;
@@ -4099,7 +4125,7 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
 
                        tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
                        tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
-                       tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
+                       tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
 
                        return err;
                }
@@ -4144,7 +4170,7 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
                                else
                                        bmsr &= ~BMSR_LSTATUS;
                        }
-                       tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
+                       tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
                }
        }
 
@@ -4171,9 +4197,11 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
                                        current_duplex = DUPLEX_FULL;
                                else
                                        current_duplex = DUPLEX_HALF;
-                       }
-                       else
+                       } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
+                               /* Link is up via parallel detect */
+                       } else {
                                current_link_up = 0;
+                       }
                }
        }
 
@@ -4197,7 +4225,7 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
                        netif_carrier_on(tp->dev);
                else {
                        netif_carrier_off(tp->dev);
-                       tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
+                       tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
                }
                tg3_link_report(tp);
        }
@@ -4211,6 +4239,7 @@ static void tg3_serdes_parallel_detect(struct tg3 *tp)
                tp->serdes_counter--;
                return;
        }
+
        if (!netif_carrier_ok(tp->dev) &&
            (tp->link_config.autoneg == AUTONEG_ENABLE)) {
                u32 bmcr;
@@ -4220,13 +4249,14 @@ static void tg3_serdes_parallel_detect(struct tg3 *tp)
                        u32 phy1, phy2;
 
                        /* Select shadow register 0x1f */
-                       tg3_writephy(tp, 0x1c, 0x7c00);
-                       tg3_readphy(tp, 0x1c, &phy1);
+                       tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
+                       tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
 
                        /* Select expansion interrupt status register */
-                       tg3_writephy(tp, 0x17, 0x0f01);
-                       tg3_readphy(tp, 0x15, &phy2);
-                       tg3_readphy(tp, 0x15, &phy2);
+                       tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
+                                        MII_TG3_DSP_EXP1_INT_STAT);
+                       tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
+                       tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
 
                        if ((phy1 & 0x10) && !(phy2 & 0x20)) {
                                /* We have signal detect and not receiving
@@ -4237,18 +4267,18 @@ static void tg3_serdes_parallel_detect(struct tg3 *tp)
                                bmcr &= ~BMCR_ANENABLE;
                                bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
                                tg3_writephy(tp, MII_BMCR, bmcr);
-                               tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
+                               tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
                        }
                }
-       }
-       else if (netif_carrier_ok(tp->dev) &&
-                (tp->link_config.autoneg == AUTONEG_ENABLE) &&
-                (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
+       } else if (netif_carrier_ok(tp->dev) &&
+                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
+                  (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
                u32 phy2;
 
                /* Select expansion interrupt status register */
-               tg3_writephy(tp, 0x17, 0x0f01);
-               tg3_readphy(tp, 0x15, &phy2);
+               tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
+                                MII_TG3_DSP_EXP1_INT_STAT);
+               tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
                if (phy2 & 0x20) {
                        u32 bmcr;
 
@@ -4256,7 +4286,7 @@ static void tg3_serdes_parallel_detect(struct tg3 *tp)
                        tg3_readphy(tp, MII_BMCR, &bmcr);
                        tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
 
-                       tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
+                       tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
 
                }
        }
@@ -4266,13 +4296,12 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
 {
        int err;
 
-       if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
+       if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
                err = tg3_setup_fiber_phy(tp, force_reset);
-       } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
+       else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
                err = tg3_setup_fiber_mii_phy(tp, force_reset);
-       } else {
+       else
                err = tg3_setup_copper_phy(tp, force_reset);
-       }
 
        if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
                u32 val, scale;
@@ -4335,8 +4364,11 @@ static void tg3_tx_recover(struct tg3 *tp)
        BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
               tp->write32_tx_mbox == tg3_write_indirect_mbox);
 
-       netdev_warn(tp->dev, "The system may be re-ordering memory-mapped I/O cycles to the network device, attempting to recover\n"
-                   "Please report the problem to the driver maintainer and include system chipset information.\n");
+       netdev_warn(tp->dev,
+                   "The system may be re-ordering memory-mapped I/O "
+                   "cycles to the network device, attempting to recover. "
+                   "Please report the problem to the driver maintainer "
+                   "and include system chipset information.\n");
 
        spin_lock(&tp->lock);
        tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
@@ -4345,7 +4377,8 @@ static void tg3_tx_recover(struct tg3 *tp)
 
 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
 {
-       smp_mb();
+       /* Tell compiler to fetch tx indices from memory. */
+       barrier();
        return tnapi->tx_pending -
               ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
 }
@@ -4378,7 +4411,7 @@ static void tg3_tx(struct tg3_napi *tnapi)
                }
 
                pci_unmap_single(tp->pdev,
-                                pci_unmap_addr(ri, mapping),
+                                dma_unmap_addr(ri, mapping),
                                 skb_headlen(skb),
                                 PCI_DMA_TODEVICE);
 
@@ -4392,7 +4425,7 @@ static void tg3_tx(struct tg3_napi *tnapi)
                                tx_bug = 1;
 
                        pci_unmap_page(tp->pdev,
-                                      pci_unmap_addr(ri, mapping),
+                                      dma_unmap_addr(ri, mapping),
                                       skb_shinfo(skb)->frags[i].size,
                                       PCI_DMA_TODEVICE);
                        sw_idx = NEXT_TX(sw_idx);
@@ -4430,7 +4463,7 @@ static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
        if (!ri->skb)
                return;
 
-       pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
+       pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
                         map_sz, PCI_DMA_FROMDEVICE);
        dev_kfree_skb_any(ri->skb);
        ri->skb = NULL;
@@ -4496,7 +4529,7 @@ static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
        }
 
        map->skb = skb;
-       pci_unmap_addr_set(map, mapping, mapping);
+       dma_unmap_addr_set(map, mapping, mapping);
 
        desc->addr_hi = ((u64)mapping >> 32);
        desc->addr_lo = ((u64)mapping & 0xffffffff);
@@ -4516,8 +4549,8 @@ static void tg3_recycle_rx(struct tg3_napi *tnapi,
        struct tg3 *tp = tnapi->tp;
        struct tg3_rx_buffer_desc *src_desc, *dest_desc;
        struct ring_info *src_map, *dest_map;
-       int dest_idx;
        struct tg3_rx_prodring_set *spr = &tp->prodring[0];
+       int dest_idx;
 
        switch (opaque_key) {
        case RXD_OPAQUE_RING_STD:
@@ -4541,8 +4574,8 @@ static void tg3_recycle_rx(struct tg3_napi *tnapi,
        }
 
        dest_map->skb = src_map->skb;
-       pci_unmap_addr_set(dest_map, mapping,
-                          pci_unmap_addr(src_map, mapping));
+       dma_unmap_addr_set(dest_map, mapping,
+                          dma_unmap_addr(src_map, mapping));
        dest_desc->addr_hi = src_desc->addr_hi;
        dest_desc->addr_lo = src_desc->addr_lo;
 
@@ -4605,18 +4638,20 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget)
                struct sk_buff *skb;
                dma_addr_t dma_addr;
                u32 opaque_key, desc_idx, *post_ptr;
+               bool hw_vlan __maybe_unused = false;
+               u16 vtag __maybe_unused = 0;
 
                desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
                opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
                if (opaque_key == RXD_OPAQUE_RING_STD) {
                        ri = &tp->prodring[0].rx_std_buffers[desc_idx];
-                       dma_addr = pci_unmap_addr(ri, mapping);
+                       dma_addr = dma_unmap_addr(ri, mapping);
                        skb = ri->skb;
                        post_ptr = &std_prod_idx;
                        rx_std_posted++;
                } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
                        ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
-                       dma_addr = pci_unmap_addr(ri, mapping);
+                       dma_addr = dma_unmap_addr(ri, mapping);
                        skb = ri->skb;
                        post_ptr = &jmb_prod_idx;
                } else
@@ -4638,12 +4673,7 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget)
                len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
                      ETH_FCS_LEN;
 
-               if (len > RX_COPY_THRESHOLD &&
-                   tp->rx_offset == NET_IP_ALIGN) {
-                   /* rx_offset will likely not equal NET_IP_ALIGN
-                    * if this is a 5701 card running in PCI-X mode
-                    * [see tg3_get_invariants()]
-                    */
+               if (len > TG3_RX_COPY_THRESH(tp)) {
                        int skb_size;
 
                        skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
@@ -4668,12 +4698,12 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget)
                        tg3_recycle_rx(tnapi, tpr, opaque_key,
                                       desc_idx, *post_ptr);
 
-                       copy_skb = netdev_alloc_skb(tp->dev,
-                                                   len + TG3_RAW_IP_ALIGN);
+                       copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
+                                                   TG3_RAW_IP_ALIGN);
                        if (copy_skb == NULL)
                                goto drop_it_no_recycle;
 
-                       skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
+                       skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
                        skb_put(copy_skb, len);
                        pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
                        skb_copy_from_linear_data(skb, copy_skb->data, len);
@@ -4699,12 +4729,29 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget)
                        goto next_pkt;
                }
 
+               if (desc->type_flags & RXD_FLAG_VLAN &&
+                   !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
+                       vtag = desc->err_vlan & RXD_VLAN_MASK;
 #if TG3_VLAN_TAG_USED
-               if (tp->vlgrp != NULL &&
-                   desc->type_flags & RXD_FLAG_VLAN) {
-                       vlan_gro_receive(&tnapi->napi, tp->vlgrp,
-                                        desc->err_vlan & RXD_VLAN_MASK, skb);
-               } else
+                       if (tp->vlgrp)
+                               hw_vlan = true;
+                       else
+#endif
+                       {
+                               struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
+                                                   __skb_push(skb, VLAN_HLEN);
+
+                               memmove(ve, skb->data + VLAN_HLEN,
+                                       ETH_ALEN * 2);
+                               ve->h_vlan_proto = htons(ETH_P_8021Q);
+                               ve->h_vlan_TCI = htons(vtag);
+                       }
+               }
+
+#if TG3_VLAN_TAG_USED
+               if (hw_vlan)
+                       vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
+               else
 #endif
                        napi_gro_receive(&tnapi->napi, skb);
 
@@ -4978,7 +5025,7 @@ static int tg3_poll_msix(struct napi_struct *napi, int budget)
                if (unlikely(work_done >= budget))
                        break;
 
-               /* tp->last_tag is used in tg3_restart_ints() below
+               /* tp->last_tag is used in tg3_int_reenable() below
                 * to tell the hw how much work has been processed,
                 * so we must read it before checking for more work.
                 */
@@ -4987,8 +5034,8 @@ static int tg3_poll_msix(struct napi_struct *napi, int budget)
                rmb();
 
                /* check for RX/TX work to do */
-               if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
-                   *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
+               if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
+                          *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
                        napi_complete(napi);
                        /* Reenable interrupts. */
                        tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
@@ -5260,7 +5307,8 @@ static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
 
        err = tg3_init_hw(tp, reset_phy);
        if (err) {
-               netdev_err(tp->dev, "Failed to re-initialize device, aborting\n");
+               netdev_err(tp->dev,
+                          "Failed to re-initialize device, aborting\n");
                tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
                tg3_full_unlock(tp);
                del_timer_sync(&tp->timer);
@@ -5279,7 +5327,7 @@ static void tg3_poll_controller(struct net_device *dev)
        struct tg3 *tp = netdev_priv(dev);
 
        for (i = 0; i < tp->irq_cnt; i++)
-               tg3_interrupt(tp->napi[i].irq_vec, dev);
+               tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
 }
 #endif
 
@@ -5437,12 +5485,12 @@ static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
                        len = skb_shinfo(skb)->frags[i-1].size;
 
                pci_unmap_single(tp->pdev,
-                                pci_unmap_addr(&tnapi->tx_buffers[entry],
+                                dma_unmap_addr(&tnapi->tx_buffers[entry],
                                                mapping),
                                 len, PCI_DMA_TODEVICE);
                if (i == 0) {
                        tnapi->tx_buffers[entry].skb = new_skb;
-                       pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
+                       dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
                                           new_addr);
                } else {
                        tnapi->tx_buffers[entry].skb = NULL;
@@ -5492,7 +5540,6 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
        struct netdev_queue *txq;
        unsigned int i, last;
 
-
        txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
        tnapi = &tp->napi[skb_get_queue_mapping(skb)];
        if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
@@ -5508,15 +5555,16 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
                        netif_tx_stop_queue(txq);
 
                        /* This is a hard error, log it. */
-                       netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
+                       netdev_err(dev,
+                                  "BUG! Tx Ring full when queue awake!\n");
                }
                return NETDEV_TX_BUSY;
        }
 
        entry = tnapi->tx_prod;
        base_flags = 0;
-       mss = 0;
-       if ((mss = skb_shinfo(skb)->gso_size) != 0) {
+       mss = skb_shinfo(skb)->gso_size;
+       if (mss) {
                int tcp_opt_len, ip_tcp_len;
                u32 hdrlen;
 
@@ -5552,9 +5600,10 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
 
                tcp_hdr(skb)->check = 0;
 
-       }
-       else if (skb->ip_summed == CHECKSUM_PARTIAL)
+       } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
                base_flags |= TXD_FLAG_TCPUDP_CSUM;
+       }
+
 #if TG3_VLAN_TAG_USED
        if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
                base_flags |= (TXD_FLAG_VLAN |
@@ -5571,7 +5620,7 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
        }
 
        tnapi->tx_buffers[entry].skb = skb;
-       pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
+       dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
 
        if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
            !mss && skb->len > ETH_DATA_LEN)
@@ -5597,7 +5646,7 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
                                goto dma_error;
 
                        tnapi->tx_buffers[entry].skb = NULL;
-                       pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
+                       dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
                                           mapping);
 
                        tg3_set_txd(tnapi, entry, mapping, len,
@@ -5613,6 +5662,13 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
        tnapi->tx_prod = entry;
        if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
                netif_tx_stop_queue(txq);
+
+               /* netif_tx_stop_queue() must be done before checking
+                * checking tx index in tg3_tx_avail() below, because in
+                * tg3_tx(), we update tx index before checking for
+                * netif_tx_queue_stopped().
+                */
+               smp_mb();
                if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
                        netif_tx_wake_queue(txq);
        }
@@ -5627,7 +5683,7 @@ dma_error:
        entry = tnapi->tx_prod;
        tnapi->tx_buffers[entry].skb = NULL;
        pci_unmap_single(tp->pdev,
-                        pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
+                        dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
                         skb_headlen(skb),
                         PCI_DMA_TODEVICE);
        for (i = 0; i <= last; i++) {
@@ -5635,7 +5691,7 @@ dma_error:
                entry = NEXT_TX(entry);
 
                pci_unmap_page(tp->pdev,
-                              pci_unmap_addr(&tnapi->tx_buffers[entry],
+                              dma_unmap_addr(&tnapi->tx_buffers[entry],
                                              mapping),
                               frag->size, PCI_DMA_TODEVICE);
        }
@@ -5658,6 +5714,13 @@ static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
        /* Estimate the number of fragments in the worst case */
        if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
                netif_stop_queue(tp->dev);
+
+               /* netif_tx_stop_queue() must be done before checking
+                * checking tx index in tg3_tx_avail() below, because in
+                * tg3_tx(), we update tx index before checking for
+                * netif_tx_queue_stopped().
+                */
+               smp_mb();
                if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
                        return NETDEV_TX_BUSY;
 
@@ -5695,7 +5758,6 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
        struct netdev_queue *txq;
        unsigned int i, last;
 
-
        txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
        tnapi = &tp->napi[skb_get_queue_mapping(skb)];
        if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
@@ -5711,7 +5773,8 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
                        netif_tx_stop_queue(txq);
 
                        /* This is a hard error, log it. */
-                       netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
+                       netdev_err(dev,
+                                  "BUG! Tx Ring full when queue awake!\n");
                }
                return NETDEV_TX_BUSY;
        }
@@ -5721,9 +5784,10 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
        if (skb->ip_summed == CHECKSUM_PARTIAL)
                base_flags |= TXD_FLAG_TCPUDP_CSUM;
 
-       if ((mss = skb_shinfo(skb)->gso_size) != 0) {
+       mss = skb_shinfo(skb)->gso_size;
+       if (mss) {
                struct iphdr *iph;
-               u32 tcp_opt_len, ip_tcp_len, hdr_len;
+               u32 tcp_opt_len, hdr_len;
 
                if (skb_header_cloned(skb) &&
                    pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
@@ -5731,20 +5795,28 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
                        goto out_unlock;
                }
 
+               iph = ip_hdr(skb);
                tcp_opt_len = tcp_optlen(skb);
-               ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
 
-               hdr_len = ip_tcp_len + tcp_opt_len;
+               if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
+                       hdr_len = skb_headlen(skb) - ETH_HLEN;
+               } else {
+                       u32 ip_tcp_len;
+
+                       ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
+                       hdr_len = ip_tcp_len + tcp_opt_len;
+
+                       iph->check = 0;
+                       iph->tot_len = htons(mss + hdr_len);
+               }
+
                if (unlikely((ETH_HLEN + hdr_len) > 80) &&
                             (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
-                       return (tg3_tso_bug(tp, skb));
+                       return tg3_tso_bug(tp, skb);
 
                base_flags |= (TXD_FLAG_CPU_PRE_DMA |
                               TXD_FLAG_CPU_POST_DMA);
 
-               iph = ip_hdr(skb);
-               iph->check = 0;
-               iph->tot_len = htons(mss + hdr_len);
                if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
                        tcp_hdr(skb)->check = 0;
                        base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
@@ -5797,7 +5869,7 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
        }
 
        tnapi->tx_buffers[entry].skb = skb;
-       pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
+       dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
 
        would_hit_hwbug = 0;
 
@@ -5833,7 +5905,7 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
                                               len, PCI_DMA_TODEVICE);
 
                        tnapi->tx_buffers[entry].skb = NULL;
-                       pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
+                       dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
                                           mapping);
                        if (pci_dma_mapping_error(tp->pdev, mapping))
                                goto dma_error;
@@ -5884,6 +5956,13 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
        tnapi->tx_prod = entry;
        if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
                netif_tx_stop_queue(txq);
+
+               /* netif_tx_stop_queue() must be done before checking
+                * checking tx index in tg3_tx_avail() below, because in
+                * tg3_tx(), we update tx index before checking for
+                * netif_tx_queue_stopped().
+                */
+               smp_mb();
                if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
                        netif_tx_wake_queue(txq);
        }
@@ -5898,7 +5977,7 @@ dma_error:
        entry = tnapi->tx_prod;
        tnapi->tx_buffers[entry].skb = NULL;
        pci_unmap_single(tp->pdev,
-                        pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
+                        dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
                         skb_headlen(skb),
                         PCI_DMA_TODEVICE);
        for (i = 0; i <= last; i++) {
@@ -5906,7 +5985,7 @@ dma_error:
                entry = NEXT_TX(entry);
 
                pci_unmap_page(tp->pdev,
-                              pci_unmap_addr(&tnapi->tx_buffers[entry],
+                              dma_unmap_addr(&tnapi->tx_buffers[entry],
                                              mapping),
                               frag->size, PCI_DMA_TODEVICE);
        }
@@ -5924,9 +6003,9 @@ static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
                if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
                        tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
                        ethtool_op_set_tso(dev, 0);
-               }
-               else
+               } else {
                        tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
+               }
        } else {
                if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
                        tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
@@ -6007,7 +6086,7 @@ static void tg3_rx_prodring_free(struct tg3 *tp,
        }
 }
 
-/* Initialize tx/rx rings for packet processing.
+/* Initialize rx rings for packet processing.
  *
  * The chip has been shut down and the driver detached from
  * the networking, so no interrupts or new tx packets will
@@ -6058,8 +6137,10 @@ static int tg3_rx_prodring_alloc(struct tg3 *tp,
        /* Now allocate fresh SKBs for each rx ring. */
        for (i = 0; i < tp->rx_pending; i++) {
                if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
-                       netdev_warn(tp->dev, "Using a smaller RX standard ring, only %d out of %d buffers were allocated successfully\n",
-                                   i, tp->rx_pending);
+                       netdev_warn(tp->dev,
+                                   "Using a smaller RX standard ring. Only "
+                                   "%d out of %d buffers were allocated "
+                                   "successfully\n", i, tp->rx_pending);
                        if (i == 0)
                                goto initfail;
                        tp->rx_pending = i;
@@ -6088,8 +6169,10 @@ static int tg3_rx_prodring_alloc(struct tg3 *tp,
 
        for (i = 0; i < tp->rx_jumbo_pending; i++) {
                if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
-                       netdev_warn(tp->dev, "Using a smaller RX jumbo ring, only %d out of %d buffers were allocated successfully\n",
-                                   i, tp->rx_jumbo_pending);
+                       netdev_warn(tp->dev,
+                                   "Using a smaller RX jumbo ring. Only %d "
+                                   "out of %d buffers were allocated "
+                                   "successfully\n", i, tp->rx_jumbo_pending);
                        if (i == 0)
                                goto initfail;
                        tp->rx_jumbo_pending = i;
@@ -6170,6 +6253,8 @@ static void tg3_free_rings(struct tg3 *tp)
        for (j = 0; j < tp->irq_cnt; j++) {
                struct tg3_napi *tnapi = &tp->napi[j];
 
+               tg3_rx_prodring_free(tp, &tp->prodring[j]);
+
                if (!tnapi->tx_buffers)
                        continue;
 
@@ -6187,7 +6272,7 @@ static void tg3_free_rings(struct tg3 *tp)
                        }
 
                        pci_unmap_single(tp->pdev,
-                                        pci_unmap_addr(txp, mapping),
+                                        dma_unmap_addr(txp, mapping),
                                         skb_headlen(skb),
                                         PCI_DMA_TODEVICE);
                        txp->skb = NULL;
@@ -6197,7 +6282,7 @@ static void tg3_free_rings(struct tg3 *tp)
                        for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
                                txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
                                pci_unmap_page(tp->pdev,
-                                              pci_unmap_addr(txp, mapping),
+                                              dma_unmap_addr(txp, mapping),
                                               skb_shinfo(skb)->frags[k].size,
                                               PCI_DMA_TODEVICE);
                                i++;
@@ -6205,8 +6290,6 @@ static void tg3_free_rings(struct tg3 *tp)
 
                        dev_kfree_skb_any(skb);
                }
-
-               tg3_rx_prodring_free(tp, &tp->prodring[j]);
        }
 }
 
@@ -6433,8 +6516,9 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int
        }
 
        if (i == MAX_WAIT_CNT && !silent) {
-               pr_err("tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
-                      ofs, enable_bit);
+               dev_err(&tp->pdev->dev,
+                       "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
+                       ofs, enable_bit);
                return -ENODEV;
        }
 
@@ -6480,8 +6564,9 @@ static int tg3_abort_hw(struct tg3 *tp, int silent)
                        break;
        }
        if (i >= MAX_WAIT_CNT) {
-               netdev_err(tp->dev, "%s timed out, TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
-                          __func__, tr32(MAC_TX_MODE));
+               dev_err(&tp->pdev->dev,
+                       "%s timed out, TX_MODE_ENABLE will not clear "
+                       "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
                err |= -ENODEV;
        }
 
@@ -6551,35 +6636,35 @@ static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
                return;
 
        switch (kind) {
-               case RESET_KIND_INIT:
-                       tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
-                                       APE_HOST_SEG_SIG_MAGIC);
-                       tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
-                                       APE_HOST_SEG_LEN_MAGIC);
-                       apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
-                       tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
-                       tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
-                                       APE_HOST_DRIVER_ID_MAGIC);
-                       tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
-                                       APE_HOST_BEHAV_NO_PHYLOCK);
-
-                       event = APE_EVENT_STATUS_STATE_START;
-                       break;
-               case RESET_KIND_SHUTDOWN:
-                       /* With the interface we are currently using,
-                        * APE does not track driver state.  Wiping
-                        * out the HOST SEGMENT SIGNATURE forces
-                        * the APE to assume OS absent status.
-                        */
-                       tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
+       case RESET_KIND_INIT:
+               tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
+                               APE_HOST_SEG_SIG_MAGIC);
+               tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
+                               APE_HOST_SEG_LEN_MAGIC);
+               apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
+               tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
+               tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
+                       APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
+               tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
+                               APE_HOST_BEHAV_NO_PHYLOCK);
+
+               event = APE_EVENT_STATUS_STATE_START;
+               break;
+       case RESET_KIND_SHUTDOWN:
+               /* With the interface we are currently using,
+                * APE does not track driver state.  Wiping
+                * out the HOST SEGMENT SIGNATURE forces
+                * the APE to assume OS absent status.
+                */
+               tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
 
-                       event = APE_EVENT_STATUS_STATE_UNLOAD;
-                       break;
-               case RESET_KIND_SUSPEND:
-                       event = APE_EVENT_STATUS_STATE_SUSPEND;
-                       break;
-               default:
-                       return;
+               event = APE_EVENT_STATUS_STATE_UNLOAD;
+               break;
+       case RESET_KIND_SUSPEND:
+               event = APE_EVENT_STATUS_STATE_SUSPEND;
+               break;
+       default:
+               return;
        }
 
        event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
@@ -6738,7 +6823,8 @@ static void tg3_restore_pci_state(struct tg3 *tp)
        /* Allow reads and writes to the APE register and memory space. */
        if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
                val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
-                      PCISTATE_ALLOW_APE_SHMEM_WR;
+                      PCISTATE_ALLOW_APE_SHMEM_WR |
+                      PCISTATE_ALLOW_APE_PSPACE_WR;
        pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
 
        pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
@@ -6853,9 +6939,13 @@ static int tg3_chip_reset(struct tg3 *tp)
        val = GRC_MISC_CFG_CORECLK_RESET;
 
        if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
-               if (tr32(0x7e2c) == 0x60) {
-                       tw32(0x7e2c, 0x20);
-               }
+               /* Force PCIe 1.0a mode */
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
+                   !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
+                   tr32(TG3_PCIE_PHY_TSTCTL) ==
+                   (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
+                       tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
+
                if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
                        tw32(GRC_MISC_CFG, (1 << 29));
                        val |= (1 << 29);
@@ -6868,8 +6958,11 @@ static int tg3_chip_reset(struct tg3 *tp)
                     tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
        }
 
-       if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
+       /* Manage gphy power for all CPMU absent PCIe devices. */
+       if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
+           !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
                val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
+
        tw32(GRC_MISC_CFG, val);
 
        /* restore 5701 hardware bug workaround write method */
@@ -6926,8 +7019,7 @@ static int tg3_chip_reset(struct tg3 *tp)
                 * Older PCIe devices only support the 128 byte
                 * MPS setting.  Enforce the restriction.
                 */
-               if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
-                   (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
+               if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
                        val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
                pci_write_config_word(tp->pdev,
                                      tp->pcie_cap + PCI_EXP_DEVCTL,
@@ -6974,10 +7066,10 @@ static int tg3_chip_reset(struct tg3 *tp)
                tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
        }
 
-       if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
+       if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
                tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
                tw32_f(MAC_MODE, tp->mac_mode);
-       } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
+       } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
                tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
                tw32_f(MAC_MODE, tp->mac_mode);
        } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
@@ -6997,35 +7089,10 @@ static int tg3_chip_reset(struct tg3 *tp)
 
        tg3_mdio_start(tp);
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
-               u8 phy_addr;
-
-               phy_addr = tp->phy_addr;
-               tp->phy_addr = TG3_PHY_PCIE_ADDR;
-
-               tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
-                            TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
-               val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
-                     TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
-                     TG3_PCIEPHY_TX0CTRL1_NB_EN;
-               tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
-               udelay(10);
-
-               tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
-                            TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
-               val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
-                     TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
-               tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
-               udelay(10);
-
-               tp->phy_addr = phy_addr;
-       }
-
        if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
            tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
-           GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
-           GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
+           !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
                val = tr32(0x7c00);
 
                tw32(0x7c00, val | (1 << 25));
@@ -7156,7 +7223,8 @@ static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_b
 
        if (cpu_base == TX_CPU_BASE &&
            (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
-               netdev_err(tp->dev, "%s: Trying to load TX cpu firmware which is 5705\n",
+               netdev_err(tp->dev,
+                          "%s: Trying to load TX cpu firmware which is 5705\n",
                           __func__);
                return -EINVAL;
        }
@@ -7236,7 +7304,8 @@ static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
                udelay(1000);
        }
        if (i >= 5) {
-               netdev_err(tp->dev, "tg3_load_firmware fails to set RX CPU PC, is %08x should be %08x\n",
+               netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
+                          "should be %08x\n", __func__,
                           tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
                return -ENODEV;
        }
@@ -7300,7 +7369,8 @@ static int tg3_load_tso_firmware(struct tg3 *tp)
                udelay(1000);
        }
        if (i >= 5) {
-               netdev_err(tp->dev, "%s fails to set CPU PC, is %08x should be %08x\n",
+               netdev_err(tp->dev,
+                          "%s fails to set CPU PC, is %08x should be %08x\n",
                           __func__, tr32(cpu_base + CPU_PC), info.fw_base);
                return -ENODEV;
        }
@@ -7380,7 +7450,7 @@ static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
                tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
        }
 
-       if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
+       if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
                tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
                tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
                tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
@@ -7457,7 +7527,8 @@ static void tg3_rings_reset(struct tg3 *tp)
 
 
        /* Disable all receive return rings but the first. */
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
                limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
        else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
                limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
@@ -7568,9 +7639,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
 
        tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
 
-       if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
+       if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
                tg3_abort_hw(tp, 1);
-       }
 
        if (reset_phy)
                tg3_phy_reset(tp);
@@ -7631,6 +7701,25 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                tw32(GRC_MODE, grc_mode);
        }
 
+       if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
+               u32 grc_mode = tr32(GRC_MODE);
+
+               /* Access the lower 1K of PL PCIE block registers. */
+               val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
+               tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
+
+               val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
+               tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
+                    val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
+
+               tw32(GRC_MODE, grc_mode);
+
+               val = tr32(TG3_CPMU_LSPD_10MB_CLK);
+               val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
+               val |= CPMU_LSPD_10MB_MACCLK_6_25;
+               tw32(TG3_CPMU_LSPD_10MB_CLK, val);
+       }
+
        /* This works around an issue with Athlon chipsets on
         * B3 tigon3 silicon.  This bit has no effect on any
         * other revision.  But do not set this on PCI Express
@@ -7655,7 +7744,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                 */
                val = tr32(TG3PCI_PCISTATE);
                val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
-                      PCISTATE_ALLOW_APE_SHMEM_WR;
+                      PCISTATE_ALLOW_APE_SHMEM_WR |
+                      PCISTATE_ALLOW_APE_PSPACE_WR;
                tw32(TG3PCI_PCISTATE, val);
        }
 
@@ -7675,10 +7765,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        if (err)
                return err;
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
+       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
                val = tr32(TG3PCI_DMA_RW_CTRL) &
                      ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
+               if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
+                       val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
                tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
        } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
                   GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
@@ -7723,8 +7814,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                        tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
                tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
                tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
-       }
-       else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
+       } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
                int fw_len;
 
                fw_len = tp->fw_len;
@@ -7803,7 +7893,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
             ((u64) tpr->rx_std_mapping >> 32));
        tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
             ((u64) tpr->rx_std_mapping & 0xffffffff));
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
+           GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
                tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
                     NIC_SRAM_RX_BUFFER_DESC);
 
@@ -7828,7 +7919,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                        tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
                             (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
                             BDINFO_FLAGS_USE_EXT_RECV);
-                       if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
+                       if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
+                           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
                                tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
                                     NIC_SRAM_RX_JUMBO_BUFFER_DESC);
                } else {
@@ -7836,12 +7928,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                             BDINFO_FLAGS_DISABLED);
                }
 
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
+               if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
                        val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
-                             (RX_STD_MAX_SIZE << 2);
+                             (TG3_RX_STD_DMA_SZ << 2);
                else
-                       val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
+                       val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
        } else
                val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
 
@@ -7854,8 +7945,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                          tp->rx_jumbo_pending : 0;
        tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
+       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
                tw32(STD_REPLENISH_LWM, 32);
                tw32(JMB_REPLENISH_LWM, 16);
        }
@@ -7890,7 +7980,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                      RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
                      RDMAC_MODE_LNGREAD_ENAB);
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
                rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
@@ -7982,8 +8073,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
                tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
 
-       if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
-               tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
+       if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
+               tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
                /* reset to prevent losing 1st rx packet intermittently */
                tw32_f(MAC_RX_MODE, RX_MODE_RESET);
                udelay(10);
@@ -7996,7 +8087,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
                MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
        if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
-           !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
+           !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
                tp->mac_mode |= MAC_MODE_LINK_POLARITY;
        tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
@@ -8129,6 +8220,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        }
 
        tp->tx_mode = TX_MODE_ENABLE;
+       if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
+               tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
        tw32_f(MAC_TX_MODE, tp->tx_mode);
        udelay(100);
 
@@ -8178,16 +8272,16 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        tw32(MAC_LED_CTRL, tp->led_ctrl);
 
        tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
-       if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
+       if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
                tw32_f(MAC_RX_MODE, RX_MODE_RESET);
                udelay(10);
        }
        tw32_f(MAC_RX_MODE, tp->rx_mode);
        udelay(10);
 
-       if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
+       if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
                if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
-                       !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
+                       !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
                        /* Set drive transmission level to 1.2V  */
                        /* only if the signal pre-emphasis bit is not set  */
                        val = tr32(MAC_SERDES_CFG);
@@ -8209,12 +8303,12 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
-           (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
+           (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
                /* Use hardware link auto-negotiation */
                tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
        }
 
-       if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
+       if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
            (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
                u32 tmp;
 
@@ -8226,8 +8320,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        }
 
        if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
-               if (tp->link_config.phy_is_low_power) {
-                       tp->link_config.phy_is_low_power = 0;
+               if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
+                       tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
                        tp->link_config.speed = tp->link_config.orig_speed;
                        tp->link_config.duplex = tp->link_config.orig_duplex;
                        tp->link_config.autoneg = tp->link_config.orig_autoneg;
@@ -8237,15 +8331,15 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                if (err)
                        return err;
 
-               if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
-                   !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
+               if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
+                   !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
                        u32 tmp;
 
                        /* Clear CRC stats. */
                        if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
                                tg3_writephy(tp, MII_TG3_TEST1,
                                             tmp | MII_TG3_TEST1_CRC_EN);
-                               tg3_readphy(tp, 0x14, &tmp);
+                               tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
                        }
                }
        }
@@ -8413,7 +8507,7 @@ static void tg3_timer(unsigned long __opaque)
                        mac_stat = tr32(MAC_STATUS);
 
                        phy_event = 0;
-                       if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
+                       if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
                                if (mac_stat & MAC_STATUS_MI_INTERRUPT)
                                        phy_event = 1;
                        } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
@@ -8429,7 +8523,7 @@ static void tg3_timer(unsigned long __opaque)
                            (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
                                need_setup = 1;
                        }
-                       if (! netif_carrier_ok(tp->dev) &&
+                       if (!netif_carrier_ok(tp->dev) &&
                            (mac_stat & (MAC_STATUS_PCS_SYNCED |
                                         MAC_STATUS_SIGNAL_DET))) {
                                need_setup = 1;
@@ -8445,8 +8539,10 @@ static void tg3_timer(unsigned long __opaque)
                                }
                                tg3_setup_phy(tp, 0);
                        }
-               } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
+               } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
+                          (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
                        tg3_serdes_parallel_detect(tp);
+               }
 
                tp->timer_counter = tp->timer_multiplier;
        }
@@ -8476,8 +8572,8 @@ static void tg3_timer(unsigned long __opaque)
                        tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
                                      FWCMD_NICDRV_ALIVE3);
                        tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
-                       /* 5 seconds timeout */
-                       tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
+                       tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
+                                     TG3_FW_UPDATE_TIMEOUT_SEC);
 
                        tg3_generate_fw_event(tp);
                }
@@ -8539,8 +8635,7 @@ static int tg3_test_interrupt(struct tg3 *tp)
         * Turn off MSI one shot mode.  Otherwise this test has no
         * observable way to know whether the interrupt was delivered.
         */
-       if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
+       if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
            (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
                val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
                tw32(MSGINT_MODE, val);
@@ -8583,8 +8678,7 @@ static int tg3_test_interrupt(struct tg3 *tp)
 
        if (intr_ok) {
                /* Reenable MSI one shot mode. */
-               if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
+               if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
                    (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
                        val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
                        tw32(MSGINT_MODE, val);
@@ -8625,14 +8719,16 @@ static int tg3_test_msi(struct tg3 *tp)
                return err;
 
        /* MSI test failed, go back to INTx mode */
-       netdev_warn(tp->dev, "No interrupt was generated using MSI, switching to INTx mode\n"
-                   "Please report this failure to the PCI maintainer and include system chipset information\n");
+       netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
+                   "to INTx mode. Please report this failure to the PCI "
+                   "maintainer and include system chipset information\n");
 
        free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
 
        pci_disable_msi(tp->pdev);
 
        tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
+       tp->napi[0].irq_vec = tp->pdev->irq;
 
        err = tg3_request_irq(tp, 0);
        if (err)
@@ -8707,9 +8803,9 @@ static bool tg3_enable_msix(struct tg3 *tp)
        }
 
        rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
-       if (rc != 0) {
-               if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
-                       return false;
+       if (rc < 0) {
+               return false;
+       } else if (rc != 0) {
                if (pci_enable_msix(tp->pdev, msix_ent, rc))
                        return false;
                netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
@@ -8717,16 +8813,19 @@ static bool tg3_enable_msix(struct tg3 *tp)
                tp->irq_cnt = rc;
        }
 
-       tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
-
        for (i = 0; i < tp->irq_max; i++)
                tp->napi[i].irq_vec = msix_ent[i].vector;
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
-               tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
-               tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
-       } else
-               tp->dev->real_num_tx_queues = 1;
+       tp->dev->real_num_tx_queues = 1;
+       if (tp->irq_cnt > 1) {
+               tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
+
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
+                       tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
+                       tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
+               }
+       }
 
        return true;
 }
@@ -8738,7 +8837,8 @@ static void tg3_ints_init(struct tg3 *tp)
                /* All MSI supporting chips should support tagged
                 * status.  Assert that this is the case.
                 */
-               netdev_warn(tp->dev, "MSI without TAGGED? Not using MSI\n");
+               netdev_warn(tp->dev,
+                           "MSI without TAGGED_STATUS? Not using MSI\n");
                goto defcfg;
        }
 
@@ -8769,7 +8869,7 @@ static void tg3_ints_fini(struct tg3 *tp)
        else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
                pci_disable_msi(tp->pdev);
        tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
-       tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
+       tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
 }
 
 static int tg3_open(struct net_device *dev)
@@ -8873,10 +8973,8 @@ static int tg3_open(struct net_device *dev)
                        goto err_out2;
                }
 
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
-                   GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
-                   (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
-                   (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
+               if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
+                   (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
                        u32 val = tr32(PCIE_TRANSACTION_CFG);
 
                        tw32(PCIE_TRANSACTION_CFG,
@@ -8913,237 +9011,8 @@ err_out1:
        return err;
 }
 
-#if 0
-/*static*/ void tg3_dump_state(struct tg3 *tp)
-{
-       u32 val32, val32_2, val32_3, val32_4, val32_5;
-       u16 val16;
-       int i;
-       struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
-
-       pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
-       pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
-       printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
-              val16, val32);
-
-       /* MAC block */
-       printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
-              tr32(MAC_MODE), tr32(MAC_STATUS));
-       printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
-              tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
-       printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
-              tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
-       printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
-              tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
-
-       /* Send data initiator control block */
-       printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
-              tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
-       printk("       SNDDATAI_STATSCTRL[%08x]\n",
-              tr32(SNDDATAI_STATSCTRL));
-
-       /* Send data completion control block */
-       printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
-
-       /* Send BD ring selector block */
-       printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
-              tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
-
-       /* Send BD initiator control block */
-       printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
-              tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
-
-       /* Send BD completion control block */
-       printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
-
-       /* Receive list placement control block */
-       printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
-              tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
-       printk("       RCVLPC_STATSCTRL[%08x]\n",
-              tr32(RCVLPC_STATSCTRL));
-
-       /* Receive data and receive BD initiator control block */
-       printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
-              tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
-
-       /* Receive data completion control block */
-       printk("DEBUG: RCVDCC_MODE[%08x]\n",
-              tr32(RCVDCC_MODE));
-
-       /* Receive BD initiator control block */
-       printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
-              tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
-
-       /* Receive BD completion control block */
-       printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
-              tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
-
-       /* Receive list selector control block */
-       printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
-              tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
-
-       /* Mbuf cluster free block */
-       printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
-              tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
-
-       /* Host coalescing control block */
-       printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
-              tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
-       printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
-              tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
-              tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
-       printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
-              tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
-              tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
-       printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
-              tr32(HOSTCC_STATS_BLK_NIC_ADDR));
-       printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
-              tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
-
-       /* Memory arbiter control block */
-       printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
-              tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
-
-       /* Buffer manager control block */
-       printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
-              tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
-       printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
-              tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
-       printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
-              "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
-              tr32(BUFMGR_DMA_DESC_POOL_ADDR),
-              tr32(BUFMGR_DMA_DESC_POOL_SIZE));
-
-       /* Read DMA control block */
-       printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
-              tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
-
-       /* Write DMA control block */
-       printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
-              tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
-
-       /* DMA completion block */
-       printk("DEBUG: DMAC_MODE[%08x]\n",
-              tr32(DMAC_MODE));
-
-       /* GRC block */
-       printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
-              tr32(GRC_MODE), tr32(GRC_MISC_CFG));
-       printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
-              tr32(GRC_LOCAL_CTRL));
-
-       /* TG3_BDINFOs */
-       printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
-              tr32(RCVDBDI_JUMBO_BD + 0x0),
-              tr32(RCVDBDI_JUMBO_BD + 0x4),
-              tr32(RCVDBDI_JUMBO_BD + 0x8),
-              tr32(RCVDBDI_JUMBO_BD + 0xc));
-       printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
-              tr32(RCVDBDI_STD_BD + 0x0),
-              tr32(RCVDBDI_STD_BD + 0x4),
-              tr32(RCVDBDI_STD_BD + 0x8),
-              tr32(RCVDBDI_STD_BD + 0xc));
-       printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
-              tr32(RCVDBDI_MINI_BD + 0x0),
-              tr32(RCVDBDI_MINI_BD + 0x4),
-              tr32(RCVDBDI_MINI_BD + 0x8),
-              tr32(RCVDBDI_MINI_BD + 0xc));
-
-       tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
-       tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
-       tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
-       tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
-       printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
-              val32, val32_2, val32_3, val32_4);
-
-       tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
-       tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
-       tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
-       tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
-       printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
-              val32, val32_2, val32_3, val32_4);
-
-       tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
-       tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
-       tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
-       tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
-       tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
-       printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
-              val32, val32_2, val32_3, val32_4, val32_5);
-
-       /* SW status block */
-       printk(KERN_DEBUG
-        "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
-              sblk->status,
-              sblk->status_tag,
-              sblk->rx_jumbo_consumer,
-              sblk->rx_consumer,
-              sblk->rx_mini_consumer,
-              sblk->idx[0].rx_producer,
-              sblk->idx[0].tx_consumer);
-
-       /* SW statistics block */
-       printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
-              ((u32 *)tp->hw_stats)[0],
-              ((u32 *)tp->hw_stats)[1],
-              ((u32 *)tp->hw_stats)[2],
-              ((u32 *)tp->hw_stats)[3]);
-
-       /* Mailboxes */
-       printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
-              tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
-              tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
-              tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
-              tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
-
-       /* NIC side send descriptors. */
-       for (i = 0; i < 6; i++) {
-               unsigned long txd;
-
-               txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
-                       + (i * sizeof(struct tg3_tx_buffer_desc));
-               printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
-                      i,
-                      readl(txd + 0x0), readl(txd + 0x4),
-                      readl(txd + 0x8), readl(txd + 0xc));
-       }
-
-       /* NIC side RX descriptors. */
-       for (i = 0; i < 6; i++) {
-               unsigned long rxd;
-
-               rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
-                       + (i * sizeof(struct tg3_rx_buffer_desc));
-               printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
-                      i,
-                      readl(rxd + 0x0), readl(rxd + 0x4),
-                      readl(rxd + 0x8), readl(rxd + 0xc));
-               rxd += (4 * sizeof(u32));
-               printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
-                      i,
-                      readl(rxd + 0x0), readl(rxd + 0x4),
-                      readl(rxd + 0x8), readl(rxd + 0xc));
-       }
-
-       for (i = 0; i < 6; i++) {
-               unsigned long rxd;
-
-               rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
-                       + (i * sizeof(struct tg3_rx_buffer_desc));
-               printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
-                      i,
-                      readl(rxd + 0x0), readl(rxd + 0x4),
-                      readl(rxd + 0x8), readl(rxd + 0xc));
-               rxd += (4 * sizeof(u32));
-               printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
-                      i,
-                      readl(rxd + 0x0), readl(rxd + 0x4),
-                      readl(rxd + 0x8), readl(rxd + 0xc));
-       }
-}
-#endif
-
-static struct net_device_stats *tg3_get_stats(struct net_device *);
+static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
+                                                struct rtnl_link_stats64 *);
 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
 
 static int tg3_close(struct net_device *dev)
@@ -9161,9 +9030,6 @@ static int tg3_close(struct net_device *dev)
        tg3_phy_stop(tp);
 
        tg3_full_lock(tp, 1);
-#if 0
-       tg3_dump_state(tp);
-#endif
 
        tg3_disable_ints(tp);
 
@@ -9180,8 +9046,8 @@ static int tg3_close(struct net_device *dev)
 
        tg3_ints_fini(tp);
 
-       memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
-              sizeof(tp->net_stats_prev));
+       tg3_get_stats64(tp->dev, &tp->net_stats_prev);
+
        memcpy(&tp->estats_prev, tg3_get_estats(tp),
               sizeof(tp->estats_prev));
 
@@ -9194,28 +9060,16 @@ static int tg3_close(struct net_device *dev)
        return 0;
 }
 
-static inline unsigned long get_stat64(tg3_stat64_t *val)
-{
-       unsigned long ret;
-
-#if (BITS_PER_LONG == 32)
-       ret = val->low;
-#else
-       ret = ((u64)val->high << 32) | ((u64)val->low);
-#endif
-       return ret;
-}
-
-static inline u64 get_estat64(tg3_stat64_t *val)
+static inline u64 get_stat64(tg3_stat64_t *val)
 {
        return ((u64)val->high << 32) | ((u64)val->low);
 }
 
-static unsigned long calc_crc_errors(struct tg3 *tp)
+static u64 calc_crc_errors(struct tg3 *tp)
 {
        struct tg3_hw_stats *hw_stats = tp->hw_stats;
 
-       if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
+       if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
            (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
                u32 val;
@@ -9224,7 +9078,7 @@ static unsigned long calc_crc_errors(struct tg3 *tp)
                if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
                        tg3_writephy(tp, MII_TG3_TEST1,
                                     val | MII_TG3_TEST1_CRC_EN);
-                       tg3_readphy(tp, 0x14, &val);
+                       tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
                } else
                        val = 0;
                spin_unlock_bh(&tp->lock);
@@ -9239,7 +9093,7 @@ static unsigned long calc_crc_errors(struct tg3 *tp)
 
 #define ESTAT_ADD(member) \
        estats->member =        old_estats->member + \
-                               get_estat64(&hw_stats->member)
+                               get_stat64(&hw_stats->member)
 
 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
 {
@@ -9329,11 +9183,11 @@ static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
        return estats;
 }
 
-static struct net_device_stats *tg3_get_stats(struct net_device *dev)
+static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
+                                                struct rtnl_link_stats64 *stats)
 {
        struct tg3 *tp = netdev_priv(dev);
-       struct net_device_stats *stats = &tp->net_stats;
-       struct net_device_stats *old_stats = &tp->net_stats_prev;
+       struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
        struct tg3_hw_stats *hw_stats = tp->hw_stats;
 
        if (!hw_stats)
@@ -9405,9 +9259,8 @@ static inline u32 calc_crc(unsigned char *buf, int len)
 
                        reg >>= 1;
 
-                       if (tmp) {
+                       if (tmp)
                                reg ^= 0xedb88320;
-                       }
                }
        }
 
@@ -9451,20 +9304,20 @@ static void __tg3_set_rx_mode(struct net_device *dev)
                rx_mode |= RX_MODE_PROMISC;
        } else if (dev->flags & IFF_ALLMULTI) {
                /* Accept all multicast. */
-               tg3_set_multi (tp, 1);
+               tg3_set_multi(tp, 1);
        } else if (netdev_mc_empty(dev)) {
                /* Reject all multicast. */
-               tg3_set_multi (tp, 0);
+               tg3_set_multi(tp, 0);
        } else {
                /* Accept one or more multicast(s). */
-               struct dev_mc_list *mclist;
+               struct netdev_hw_addr *ha;
                u32 mc_filter[4] = { 0, };
                u32 regidx;
                u32 bit;
                u32 crc;
 
-               netdev_for_each_mc_addr(mclist, dev) {
-                       crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
+               netdev_for_each_mc_addr(ha, dev) {
+                       crc = calc_crc(ha->addr, ETH_ALEN);
                        bit = ~crc & 0x7f;
                        regidx = (bit & 0x60) >> 5;
                        bit &= 0x1f;
@@ -9515,13 +9368,13 @@ static void tg3_get_regs(struct net_device *dev,
 
        memset(p, 0, TG3_REGDUMP_LEN);
 
-       if (tp->link_config.phy_is_low_power)
+       if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
                return;
 
        tg3_full_lock(tp, 0);
 
 #define __GET_REG32(reg)       (*(p)++ = tr32(reg))
-#define GET_REG32_LOOP(base,len)               \
+#define GET_REG32_LOOP(base, len)              \
 do {   p = (u32 *)(orig_p + (base));           \
        for (i = 0; i < len; i += 4)            \
                __GET_REG32((base) + i);        \
@@ -9594,7 +9447,7 @@ static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
        if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
                return -EINVAL;
 
-       if (tp->link_config.phy_is_low_power)
+       if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
                return -EAGAIN;
 
        offset = eeprom->offset;
@@ -9614,10 +9467,10 @@ static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
                ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
                if (ret)
                        return ret;
-               memcpy(data, ((char*)&val) + b_offset, b_count);
+               memcpy(data, ((char *)&val) + b_offset, b_count);
                len -= b_count;
                offset += b_count;
-               eeprom->len += b_count;
+               eeprom->len += b_count;
        }
 
        /* read bytes upto the last 4 byte boundary */
@@ -9656,7 +9509,7 @@ static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
        u8 *buf;
        __be32 start, end;
 
-       if (tp->link_config.phy_is_low_power)
+       if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
                return -EAGAIN;
 
        if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
@@ -9713,7 +9566,7 @@ static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 
        if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
                struct phy_device *phydev;
-               if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
+               if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
                        return -EAGAIN;
                phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
                return phy_ethtool_gset(phydev, cmd);
@@ -9721,11 +9574,11 @@ static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 
        cmd->supported = (SUPPORTED_Autoneg);
 
-       if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
+       if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
                cmd->supported |= (SUPPORTED_1000baseT_Half |
                                   SUPPORTED_1000baseT_Full);
 
-       if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
+       if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
                cmd->supported |= (SUPPORTED_100baseT_Half |
                                  SUPPORTED_100baseT_Full |
                                  SUPPORTED_10baseT_Half |
@@ -9756,7 +9609,7 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 
        if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
                struct phy_device *phydev;
-               if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
+               if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
                        return -EAGAIN;
                phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
                return phy_ethtool_sset(phydev, cmd);
@@ -9776,11 +9629,11 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
                           ADVERTISED_Pause |
                           ADVERTISED_Asym_Pause;
 
-               if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
+               if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
                        mask |= ADVERTISED_1000baseT_Half |
                                ADVERTISED_1000baseT_Full;
 
-               if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
+               if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
                        mask |= ADVERTISED_100baseT_Half |
                                ADVERTISED_100baseT_Full |
                                ADVERTISED_10baseT_Half |
@@ -9801,7 +9654,7 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 
                cmd->advertising &= mask;
        } else {
-               if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
+               if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
                        if (cmd->speed != SPEED_1000)
                                return -EINVAL;
 
@@ -9937,11 +9790,11 @@ static int tg3_nway_reset(struct net_device *dev)
        if (!netif_running(dev))
                return -EAGAIN;
 
-       if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
+       if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
                return -EINVAL;
 
        if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
-               if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
+               if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
                        return -EAGAIN;
                r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
        } else {
@@ -9952,7 +9805,7 @@ static int tg3_nway_reset(struct net_device *dev)
                tg3_readphy(tp, MII_BMCR, &bmcr);
                if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
                    ((bmcr & BMCR_ANENABLE) ||
-                    (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
+                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
                        tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
                                                   BMCR_ANENABLE);
                        r = 0;
@@ -10087,7 +9940,7 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam
                else
                        tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
 
-               if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
+               if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
                        u32 oldadv = phydev->advertising &
                                     (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
                        if (oldadv != newadv) {
@@ -10165,8 +10018,8 @@ static int tg3_set_rx_csum(struct net_device *dev, u32 data)
        if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
                if (data != 0)
                        return -EINVAL;
-               return 0;
-       }
+               return 0;
+       }
 
        spin_lock_bh(&tp->lock);
        if (data)
@@ -10185,8 +10038,8 @@ static int tg3_set_tx_csum(struct net_device *dev, u32 data)
        if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
                if (data != 0)
                        return -EINVAL;
-               return 0;
-       }
+               return 0;
+       }
 
        if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
                ethtool_op_set_tx_ipv6_csum(dev, data);
@@ -10196,7 +10049,7 @@ static int tg3_set_tx_csum(struct net_device *dev, u32 data)
        return 0;
 }
 
-static int tg3_get_sset_count (struct net_device *dev, int sset)
+static int tg3_get_sset_count(struct net_device *dev, int sset)
 {
        switch (sset) {
        case ETH_SS_TEST:
@@ -10208,7 +10061,7 @@ static int tg3_get_sset_count (struct net_device *dev, int sset)
        }
 }
 
-static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
+static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
 {
        switch (stringset) {
        case ETH_SS_STATS:
@@ -10255,7 +10108,7 @@ static int tg3_phys_id(struct net_device *dev, u32 data)
        return 0;
 }
 
-static void tg3_get_ethtool_stats (struct net_device *dev,
+static void tg3_get_ethtool_stats(struct net_device *dev,
                                   struct ethtool_stats *estats, u64 *tmp_stats)
 {
        struct tg3 *tp = netdev_priv(dev);
@@ -10361,8 +10214,7 @@ static int tg3_test_nvram(struct tg3 *tp)
                                for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
                                        parity[k++] = buf8[i] & msk;
                                i++;
-                       }
-                       else if (i == 16) {
+                       } else if (i == 16) {
                                int l;
                                u8 msk;
 
@@ -10417,7 +10269,7 @@ static int tg3_test_link(struct tg3 *tp)
        if (!netif_running(tp->dev))
                return -ENODEV;
 
-       if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
+       if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
                max = TG3_SERDES_TIMEOUT_SEC;
        else
                max = TG3_COPPER_TIMEOUT_SEC;
@@ -10460,7 +10312,7 @@ static int tg3_test_registers(struct tg3 *tp)
                { MAC_ADDR_0_HIGH, 0x0000,
                        0x00000000, 0x0000ffff },
                { MAC_ADDR_0_LOW, 0x0000,
-                       0x00000000, 0xffffffff },
+                       0x00000000, 0xffffffff },
                { MAC_RX_MTU_SIZE, 0x0000,
                        0x00000000, 0x0000ffff },
                { MAC_TX_MODE, 0x0000,
@@ -10648,7 +10500,8 @@ static int tg3_test_registers(struct tg3 *tp)
 
 out:
        if (netif_msg_hw(tp))
-               pr_err("Register test failed at offset %x\n", offset);
+               netdev_err(tp->dev,
+                          "Register test failed at offset %x\n", offset);
        tw32(offset, save_val);
        return -EIO;
 }
@@ -10719,7 +10572,8 @@ static int tg3_test_memory(struct tg3 *tp)
        int err = 0;
        int i;
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
                mem_tbl = mem_tbl_5717;
        else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
                mem_tbl = mem_tbl_57765;
@@ -10733,8 +10587,8 @@ static int tg3_test_memory(struct tg3 *tp)
                mem_tbl = mem_tbl_570x;
 
        for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
-               if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
-                   mem_tbl[i].len)) != 0)
+               err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
+               if (err)
                        break;
        }
 
@@ -10777,7 +10631,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
                           MAC_MODE_PORT_INT_LPBACK;
                if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
                        mac_mode |= MAC_MODE_LINK_POLARITY;
-               if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
+               if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
                        mac_mode |= MAC_MODE_PORT_MODE_MII;
                else
                        mac_mode |= MAC_MODE_PORT_MODE_GMII;
@@ -10785,7 +10639,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
        } else if (loopback_mode == TG3_PHY_LOOPBACK) {
                u32 val;
 
-               if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
+               if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
                        tg3_phy_fet_toggle_apd(tp, false);
                        val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
                } else
@@ -10797,7 +10651,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
                udelay(40);
 
                mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
-               if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
+               if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
                        tg3_writephy(tp, MII_TG3_FET_PTEST,
                                     MII_TG3_FET_PTEST_FRC_TX_LINK |
                                     MII_TG3_FET_PTEST_FRC_TX_LOCK);
@@ -10809,7 +10663,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
                        mac_mode |= MAC_MODE_PORT_MODE_GMII;
 
                /* reset to prevent losing 1st rx packet intermittently */
-               if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
+               if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
                        tw32_f(MAC_RX_MODE, RX_MODE_RESET);
                        udelay(10);
                        tw32_f(MAC_RX_MODE, tp->rx_mode);
@@ -10824,9 +10678,9 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
                                     MII_TG3_EXT_CTRL_LNK3_LED_MODE);
                }
                tw32(MAC_MODE, mac_mode);
-       }
-       else
+       } else {
                return -EINVAL;
+       }
 
        err = -EIO;
 
@@ -10908,7 +10762,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
 
        rx_skb = tpr->rx_std_buffers[desc_idx].skb;
 
-       map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
+       map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
        pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
 
        for (i = 14; i < tx_len; i++) {
@@ -10940,7 +10794,7 @@ static int tg3_test_loopback(struct tg3 *tp)
                return TG3_LOOPBACK_FAILED;
 
        /* Turn off gphy autopowerdown. */
-       if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
+       if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
                tg3_phy_toggle_apd(tp, false);
 
        if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
@@ -10977,14 +10831,14 @@ static int tg3_test_loopback(struct tg3 *tp)
                tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
        }
 
-       if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
+       if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
            !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
                if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
                        err |= TG3_PHY_LOOPBACK_FAILED;
        }
 
        /* Re-enable gphy autopowerdown. */
-       if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
+       if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
                tg3_phy_toggle_apd(tp, true);
 
        return err;
@@ -10995,7 +10849,7 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
 {
        struct tg3 *tp = netdev_priv(dev);
 
-       if (tp->link_config.phy_is_low_power)
+       if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
                tg3_set_power_state(tp, PCI_D0);
 
        memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
@@ -11027,7 +10881,7 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
                if (!err)
                        tg3_nvram_unlock(tp);
 
-               if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
+               if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
                        tg3_phy_reset(tp);
 
                if (tg3_test_registers(tp) != 0) {
@@ -11063,7 +10917,7 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
                if (irq_sync && !err2)
                        tg3_phy_start(tp);
        }
-       if (tp->link_config.phy_is_low_power)
+       if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
                tg3_set_power_state(tp, PCI_D3hot);
 
 }
@@ -11076,13 +10930,13 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 
        if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
                struct phy_device *phydev;
-               if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
+               if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
                        return -EAGAIN;
                phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
-               return phy_mii_ioctl(phydev, data, cmd);
+               return phy_mii_ioctl(phydev, ifr, cmd);
        }
 
-       switch(cmd) {
+       switch (cmd) {
        case SIOCGMIIPHY:
                data->phy_id = tp->phy_addr;
 
@@ -11090,10 +10944,10 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
        case SIOCGMIIREG: {
                u32 mii_regval;
 
-               if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
+               if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
                        break;                  /* We have no PHY */
 
-               if (tp->link_config.phy_is_low_power)
+               if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
                        return -EAGAIN;
 
                spin_lock_bh(&tp->lock);
@@ -11106,10 +10960,10 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
        }
 
        case SIOCSMIIREG:
-               if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
+               if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
                        break;                  /* We have no PHY */
 
-               if (tp->link_config.phy_is_low_power)
+               if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
                        return -EAGAIN;
 
                spin_lock_bh(&tp->lock);
@@ -11775,7 +11629,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
                tp->tg3_flags |= TG3_FLAG_NVRAM;
 
                if (tg3_nvram_lock(tp)) {
-                       netdev_warn(tp->dev, "Cannot get nvram lock, %s failed\n",
+                       netdev_warn(tp->dev,
+                                   "Cannot get nvram lock, %s failed\n",
                                    __func__);
                        return;
                }
@@ -11798,7 +11653,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
                else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
                        tg3_get_57780_nvram_info(tp);
-               else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
+               else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+                        GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
                        tg3_get_5717_nvram_info(tp);
                else
                        tg3_get_nvram_info(tp);
@@ -11894,7 +11750,7 @@ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
                if (ret)
                        break;
 
-               page_off = offset & pagemask;
+               page_off = offset & pagemask;
                size = pagesize;
                if (len < size)
                        size = len;
@@ -11922,7 +11778,7 @@ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
                nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
                        NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
 
-               if (tg3_nvram_exec_cmd(tp, nvram_cmd))
+               if (tg3_nvram_exec_cmd(tp, nvram_cmd))
                        break;
 
                /* Issue another write enable to start the write. */
@@ -11976,7 +11832,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
                memcpy(&data, buf + i, 4);
                tw32(NVRAM_WRDATA, be32_to_cpu(data));
 
-               page_off = offset % tp->nvram_pagesize;
+               page_off = offset % tp->nvram_pagesize;
 
                phy_addr = tg3_nvram_phys_addr(tp, offset);
 
@@ -11984,7 +11840,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
 
                nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
 
-               if ((page_off == 0) || (i == 0))
+               if (page_off == 0 || i == 0)
                        nvram_cmd |= NVRAM_CMD_FIRST;
                if (page_off == (tp->nvram_pagesize - 4))
                        nvram_cmd |= NVRAM_CMD_LAST;
@@ -12027,8 +11883,7 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
 
        if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
                ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
-       }
-       else {
+       } else {
                u32 grc_mode;
 
                ret = tg3_nvram_lock(tp);
@@ -12048,8 +11903,7 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
 
                        ret = tg3_nvram_write_block_buffered(tp, offset, len,
                                buf);
-               }
-               else {
+               } else {
                        ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
                                buf);
                }
@@ -12236,11 +12090,10 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
 
                tp->phy_id = eeprom_phy_id;
                if (eeprom_phy_serdes) {
-                       if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
-                           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
-                               tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
+                       if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
+                               tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
                        else
-                               tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
+                               tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
                }
 
                if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
@@ -12324,7 +12177,7 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
                        (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
                        tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
 
-               if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
+               if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
                    !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
                        tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
 
@@ -12333,19 +12186,21 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
                        tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
 
                if (cfg2 & (1 << 17))
-                       tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
+                       tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
 
                /* serdes signal pre-emphasis in register 0x590 set by */
                /* bootcode if bit 18 is set */
                if (cfg2 & (1 << 18))
-                       tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
+                       tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
 
                if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
                    (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
-                       tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
+                       tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
 
-               if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
+               if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
+                   GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
+                   !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
                        u32 cfg3;
 
                        tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
@@ -12450,9 +12305,9 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
        if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
                tp->phy_id = hw_phy_id;
                if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
-                       tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
+                       tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
                else
-                       tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
+                       tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
        } else {
                if (tp->phy_id != TG3_PHY_ID_INVALID) {
                        /* Do nothing, phy ID already set up in
@@ -12471,11 +12326,11 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
                        tp->phy_id = p->phy_id;
                        if (!tp->phy_id ||
                            tp->phy_id == TG3_PHY_ID_BCM8002)
-                               tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
+                               tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
                }
        }
 
-       if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
+       if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
            !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
                u32 bmsr, adv_reg, tg3_ctrl, mask;
@@ -12493,7 +12348,7 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
                           ADVERTISE_100HALF | ADVERTISE_100FULL |
                           ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
                tg3_ctrl = 0;
-               if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
+               if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
                        tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
                                    MII_TG3_CTRL_ADV_1000_FULL);
                        if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
@@ -12508,7 +12363,7 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
                if (!tg3_copper_is_advertising_all(tp, mask)) {
                        tg3_writephy(tp, MII_ADVERTISE, adv_reg);
 
-                       if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
+                       if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
                                tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
 
                        tg3_writephy(tp, MII_BMCR,
@@ -12517,7 +12372,7 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
                tg3_phy_set_wirespeed(tp);
 
                tg3_writephy(tp, MII_ADVERTISE, adv_reg);
-               if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
+               if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
                        tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
        }
 
@@ -12530,13 +12385,13 @@ skip_phy_reset:
                err = tg3_init_5401phy_dsp(tp);
        }
 
-       if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
+       if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
                tp->link_config.advertising =
                        (ADVERTISED_1000baseT_Half |
                         ADVERTISED_1000baseT_Full |
                         ADVERTISED_Autoneg |
                         ADVERTISED_FIBRE);
-       if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
+       if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
                tp->link_config.advertising &=
                        ~(ADVERTISED_1000baseT_Half |
                          ADVERTISED_1000baseT_Full);
@@ -12544,11 +12399,11 @@ skip_phy_reset:
        return err;
 }
 
-static void __devinit tg3_read_partno(struct tg3 *tp)
+static void __devinit tg3_read_vpd(struct tg3 *tp)
 {
-       unsigned char vpd_data[TG3_NVM_VPD_LEN];   /* in little-endian format */
+       u8 vpd_data[TG3_NVM_VPD_LEN];
        unsigned int block_end, rosize, len;
-       int i = 0;
+       int j, i = 0;
        u32 magic;
 
        if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
@@ -12597,6 +12452,32 @@ static void __devinit tg3_read_partno(struct tg3 *tp)
        if (block_end > TG3_NVM_VPD_LEN)
                goto out_not_found;
 
+       j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
+                                     PCI_VPD_RO_KEYWORD_MFR_ID);
+       if (j > 0) {
+               len = pci_vpd_info_field_size(&vpd_data[j]);
+
+               j += PCI_VPD_INFO_FLD_HDR_SIZE;
+               if (j + len > block_end || len != 4 ||
+                   memcmp(&vpd_data[j], "1028", 4))
+                       goto partno;
+
+               j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
+                                             PCI_VPD_RO_KEYWORD_VENDOR0);
+               if (j < 0)
+                       goto partno;
+
+               len = pci_vpd_info_field_size(&vpd_data[j]);
+
+               j += PCI_VPD_INFO_FLD_HDR_SIZE;
+               if (j + len > block_end)
+                       goto partno;
+
+               memcpy(tp->fw_ver, &vpd_data[j], len);
+               strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
+       }
+
+partno:
        i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
                                      PCI_VPD_RO_KEYWORD_PARTNO);
        if (i < 0)
@@ -12666,7 +12547,7 @@ static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
 {
        u32 val, offset, start, ver_offset;
-       int i;
+       int i, dst_off;
        bool newver = false;
 
        if (tg3_nvram_read(tp, 0xc, &offset) ||
@@ -12686,8 +12567,11 @@ static void __devinit tg3_read_bc_ver(struct tg3 *tp)
                        newver = true;
        }
 
+       dst_off = strlen(tp->fw_ver);
+
        if (newver) {
-               if (tg3_nvram_read(tp, offset + 8, &ver_offset))
+               if (TG3_VER_SIZE - dst_off < 16 ||
+                   tg3_nvram_read(tp, offset + 8, &ver_offset))
                        return;
 
                offset = offset + ver_offset - start;
@@ -12696,7 +12580,7 @@ static void __devinit tg3_read_bc_ver(struct tg3 *tp)
                        if (tg3_nvram_read_be32(tp, offset + i, &v))
                                return;
 
-                       memcpy(tp->fw_ver + i, &v, sizeof(v));
+                       memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
                }
        } else {
                u32 major, minor;
@@ -12707,7 +12591,8 @@ static void __devinit tg3_read_bc_ver(struct tg3 *tp)
                major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
                        TG3_NVM_BCVER_MAJSFT;
                minor = ver_offset & TG3_NVM_BCVER_MINMSK;
-               snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
+               snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
+                        "v%d.%02d", major, minor);
        }
 }
 
@@ -12731,9 +12616,7 @@ static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
 {
        u32 offset, major, minor, build;
 
-       tp->fw_ver[0] = 's';
-       tp->fw_ver[1] = 'b';
-       tp->fw_ver[2] = '\0';
+       strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
 
        if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
                return;
@@ -12770,11 +12653,14 @@ static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
        if (minor > 99 || build > 26)
                return;
 
-       snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
+       offset = strlen(tp->fw_ver);
+       snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
+                " v%d.%02d", major, minor);
 
        if (build > 0) {
-               tp->fw_ver[8] = 'a' + build - 1;
-               tp->fw_ver[9] = '\0';
+               offset = strlen(tp->fw_ver);
+               if (offset < TG3_VER_SIZE - 1)
+                       tp->fw_ver[offset] = 'a' + build - 1;
        }
 }
 
@@ -12834,6 +12720,7 @@ static void __devinit tg3_read_dash_ver(struct tg3 *tp)
 {
        int vlen;
        u32 apedata;
+       char *fwtype;
 
        if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
            !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
@@ -12849,9 +12736,15 @@ static void __devinit tg3_read_dash_ver(struct tg3 *tp)
 
        apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
 
+       if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
+               fwtype = "NCSI";
+       else
+               fwtype = "DASH";
+
        vlen = strlen(tp->fw_ver);
 
-       snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
+       snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
+                fwtype,
                 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
                 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
                 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
@@ -12861,12 +12754,13 @@ static void __devinit tg3_read_dash_ver(struct tg3 *tp)
 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
 {
        u32 val;
+       bool vpd_vers = false;
 
-       if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
-               tp->fw_ver[0] = 's';
-               tp->fw_ver[1] = 'b';
-               tp->fw_ver[2] = '\0';
+       if (tp->fw_ver[0] != 0)
+               vpd_vers = true;
 
+       if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
+               strcat(tp->fw_ver, "sb");
                return;
        }
 
@@ -12883,23 +12777,31 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp)
                return;
 
        if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
-            (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
-               return;
+            (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
+               goto done;
 
        tg3_read_mgmtfw_ver(tp);
 
+done:
        tp->fw_ver[TG3_VER_SIZE - 1] = 0;
 }
 
 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
 
+static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
+{
+#if TG3_VLAN_TAG_USED
+       dev->vlan_features |= flags;
+#endif
+}
+
 static int __devinit tg3_get_invariants(struct tg3 *tp)
 {
        static struct pci_device_id write_reorder_chipsets[] = {
                { PCI_DEVICE(PCI_VENDOR_ID_AMD,
-                            PCI_DEVICE_ID_AMD_FE_GATE_700C) },
+                            PCI_DEVICE_ID_AMD_FE_GATE_700C) },
                { PCI_DEVICE(PCI_VENDOR_ID_AMD,
-                            PCI_DEVICE_ID_AMD_8131_BRIDGE) },
+                            PCI_DEVICE_ID_AMD_8131_BRIDGE) },
                { PCI_DEVICE(PCI_VENDOR_ID_VIA,
                             PCI_DEVICE_ID_VIA_8385_0) },
                { },
@@ -12937,7 +12839,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
 
                if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
                    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
-                   tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
+                   tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724 ||
+                   tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
                        pci_read_config_dword(tp->pdev,
                                              TG3PCI_GEN2_PRODID_ASICREV,
                                              &prod_id_asic_rev);
@@ -13065,8 +12968,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
                tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
                tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
-       }
-       else {
+       } else {
                struct pci_dev *bridge = NULL;
 
                do {
@@ -13096,6 +12998,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
                tp->pdev_peer = tg3_find_peer(tp);
 
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
+               tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
+
        /* Intentionally exclude ASIC_REV_5906 */
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
@@ -13103,8 +13010,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
+           (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
                tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
@@ -13124,15 +13030,17 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
        if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
                tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
        else {
+               unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
+
                tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
-               tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
                if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
-                       tp->dev->features |= NETIF_F_IPV6_CSUM;
+                       features |= NETIF_F_IPV6_CSUM;
+               tp->dev->features |= features;
+               vlan_features_add(tp->dev, features);
        }
 
        /* Determine TSO capabilities */
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
+       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
                tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
        else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
                 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
@@ -13168,14 +13076,14 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                        tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
                }
 
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
+               if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
                        tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
                        tp->irq_max = TG3_IRQ_MAX_VECS;
                }
        }
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
                tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
        else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
@@ -13183,13 +13091,12 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
        }
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
+       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
                tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
 
        if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
-            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
-                (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
+           (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
+           (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
                tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
 
        pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
@@ -13223,7 +13130,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                   (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
                tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
                if (!tp->pcix_cap) {
-                       pr_err("Cannot find PCI-X capability, aborting\n");
+                       dev_err(&tp->pdev->dev,
+                               "Cannot find PCI-X capability, aborting\n");
                        return -EIO;
                }
 
@@ -13374,7 +13282,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                 * APE register and memory space.
                 */
                pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
-                                PCISTATE_ALLOW_APE_SHMEM_WR;
+                                PCISTATE_ALLOW_APE_SHMEM_WR |
+                                PCISTATE_ALLOW_APE_PSPACE_WR;
                pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
                                       pci_state_reg);
        }
@@ -13383,8 +13292,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
+           (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
                tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
 
        /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
@@ -13420,7 +13328,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
        /* Force the chip into D0. */
        err = tg3_set_power_state(tp, PCI_D0);
        if (err) {
-               pr_err("(%s) transition to D0 failed\n", pci_name(tp->pdev));
+               dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
                return err;
        }
 
@@ -13442,40 +13350,39 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
        }
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
-               tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
+               tp->phy_flags |= TG3_PHYFLG_IS_FET;
 
        /* A few boards don't want Ethernet@WireSpeed phy feature */
        if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
            ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
             (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
             (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
-           (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
-           (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
-               tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
+           (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
+           (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
+               tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
 
        if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
            GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
-               tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
+               tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
        if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
-               tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
+               tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
 
        if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
-           !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
+           !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
-           GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
-           GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
+           !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
                        if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
                            tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
-                               tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
+                               tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
                        if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
-                               tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
+                               tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
                } else
-                       tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
+                       tp->phy_flags |= TG3_PHYFLG_BER_BUG;
        }
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
@@ -13504,8 +13411,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                return err;
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
-           (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
-                (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
+           tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
                return -ENOTSUPP;
 
        /* Initialize data/descriptor byte/word swapping. */
@@ -13589,27 +13495,26 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
            tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
            tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
            tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
-           (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
-               tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
+           (tp->phy_flags & TG3_PHYFLG_IS_FET))
+               tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
 
        err = tg3_phy_probe(tp);
        if (err) {
-               pr_err("(%s) phy probe failed, err %d\n",
-                      pci_name(tp->pdev), err);
+               dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
                /* ... but do not return immediately ... */
                tg3_mdio_fini(tp);
        }
 
-       tg3_read_partno(tp);
+       tg3_read_vpd(tp);
        tg3_read_fw_ver(tp);
 
-       if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
-               tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
+       if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
+               tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
        } else {
                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
-                       tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
+                       tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
                else
-                       tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
+                       tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
        }
 
        /* 5700 {AX,BX} chips have a broken status block link
@@ -13627,21 +13532,26 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
         */
        if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
-           !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
-               tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
-                                 TG3_FLAG_USE_LINKCHG_REG);
+           !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
+               tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
+               tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
        }
 
        /* For all SERDES we poll the MAC status register. */
-       if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
+       if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
                tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
        else
                tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
 
-       tp->rx_offset = NET_IP_ALIGN;
+       tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
+       tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
-           (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
-               tp->rx_offset = 0;
+           (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
+               tp->rx_offset -= NET_IP_ALIGN;
+#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
+               tp->rx_copy_thresh = ~(u16)0;
+#endif
+       }
 
        tp->rx_std_max_post = TG3_RX_RING_SIZE;
 
@@ -13708,9 +13618,12 @@ static int __devinit tg3_get_device_address(struct tg3 *tp)
                        tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
                else
                        tg3_nvram_unlock(tp);
-       } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
-               if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
+       } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
+                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
+               if (PCI_FUNC(tp->pdev->devfn) & 1)
                        mac_offset = 0xcc;
+               if (PCI_FUNC(tp->pdev->devfn) > 1)
+                       mac_offset += 0x18c;
        } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
                mac_offset = 0x10;
 
@@ -13795,8 +13708,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
 #endif
 #endif
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
+       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
                val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
                goto out;
        }
@@ -13964,11 +13876,10 @@ static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dm
        }
        pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 
-       if (to_device) {
+       if (to_device)
                tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
-       } else {
+       else
                tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
-       }
 
        ret = -ENODEV;
        for (i = 0; i < 40; i++) {
@@ -14008,8 +13919,7 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
 
        tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
+       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
                goto out;
 
        if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
@@ -14104,8 +14014,9 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
                /* Send the buffer to the chip. */
                ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
                if (ret) {
-                       pr_err("tg3_test_dma() Write the buffer failed %d\n",
-                              ret);
+                       dev_err(&tp->pdev->dev,
+                               "%s: Buffer write failed. err = %d\n",
+                               __func__, ret);
                        break;
                }
 
@@ -14115,8 +14026,9 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
                        u32 val;
                        tg3_read_mem(tp, 0x2100 + (i*4), &val);
                        if (le32_to_cpu(val) != p[i]) {
-                               pr_err("  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n",
-                                      val, i);
+                               dev_err(&tp->pdev->dev,
+                                       "%s: Buffer corrupted on device! "
+                                       "(%d != %d)\n", __func__, val, i);
                                /* ret = -ENODEV here? */
                        }
                        p[i] = 0;
@@ -14125,9 +14037,8 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
                /* Now read it back. */
                ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
                if (ret) {
-                       pr_err("tg3_test_dma() Read the buffer failed %d\n",
-                              ret);
-
+                       dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
+                               "err = %d\n", __func__, ret);
                        break;
                }
 
@@ -14143,8 +14054,9 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
                                tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
                                break;
                        } else {
-                               pr_err("tg3_test_dma() buffer corrupted on read back! (%d != %d)\n",
-                                      p[i], i);
+                               dev_err(&tp->pdev->dev,
+                                       "%s: Buffer corrupted on read back! "
+                                       "(%d != %d)\n", __func__, p[i], i);
                                ret = -ENODEV;
                                goto out;
                        }
@@ -14171,10 +14083,10 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
                if (pci_dev_present(dma_wait_state_chipsets)) {
                        tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
                        tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
-               }
-               else
+               } else {
                        /* Safe to use the calculated DMA boundary. */
                        tp->dma_rwctrl = saved_dma_rwctrl;
+               }
 
                tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
        }
@@ -14197,7 +14109,6 @@ static void __devinit tg3_init_link_config(struct tg3 *tp)
        tp->link_config.autoneg = AUTONEG_ENABLE;
        tp->link_config.active_speed = SPEED_INVALID;
        tp->link_config.active_duplex = DUPLEX_INVALID;
-       tp->link_config.phy_is_low_power = 0;
        tp->link_config.orig_speed = SPEED_INVALID;
        tp->link_config.orig_duplex = DUPLEX_INVALID;
        tp->link_config.orig_autoneg = AUTONEG_INVALID;
@@ -14205,8 +14116,7 @@ static void __devinit tg3_init_link_config(struct tg3 *tp)
 
 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
 {
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
+       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
                tp->bufmgr_config.mbuf_read_dma_low_water =
                        DEFAULT_MB_RDMA_LOW_WATER_5705;
                tp->bufmgr_config.mbuf_mac_rx_low_water =
@@ -14283,6 +14193,7 @@ static char * __devinit tg3_phy_string(struct tg3 *tp)
        case TG3_PHY_ID_BCM5718C:       return "5718C";
        case TG3_PHY_ID_BCM5718S:       return "5718S";
        case TG3_PHY_ID_BCM57765:       return "57765";
+       case TG3_PHY_ID_BCM5719C:       return "5719C";
        case TG3_PHY_ID_BCM8002:        return "8002/serdes";
        case 0:                 return "serdes";
        default:                return "unknown";
@@ -14388,7 +14299,7 @@ static const struct net_device_ops tg3_netdev_ops = {
        .ndo_open               = tg3_open,
        .ndo_stop               = tg3_close,
        .ndo_start_xmit         = tg3_start_xmit,
-       .ndo_get_stats          = tg3_get_stats,
+       .ndo_get_stats64        = tg3_get_stats64,
        .ndo_validate_addr      = eth_validate_addr,
        .ndo_set_multicast_list = tg3_set_rx_mode,
        .ndo_set_mac_address    = tg3_set_mac_addr,
@@ -14407,7 +14318,7 @@ static const struct net_device_ops tg3_netdev_ops_dma_bug = {
        .ndo_open               = tg3_open,
        .ndo_stop               = tg3_close,
        .ndo_start_xmit         = tg3_start_xmit_dma_bug,
-       .ndo_get_stats          = tg3_get_stats,
+       .ndo_get_stats64        = tg3_get_stats64,
        .ndo_validate_addr      = eth_validate_addr,
        .ndo_set_multicast_list = tg3_set_rx_mode,
        .ndo_set_mac_address    = tg3_set_mac_addr,
@@ -14436,13 +14347,13 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
 
        err = pci_enable_device(pdev);
        if (err) {
-               pr_err("Cannot enable PCI device, aborting\n");
+               dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
                return err;
        }
 
        err = pci_request_regions(pdev, DRV_MODULE_NAME);
        if (err) {
-               pr_err("Cannot obtain PCI resources, aborting\n");
+               dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
                goto err_out_disable_pdev;
        }
 
@@ -14451,14 +14362,15 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
        /* Find power-management capability. */
        pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
        if (pm_cap == 0) {
-               pr_err("Cannot find PowerManagement capability, aborting\n");
+               dev_err(&pdev->dev,
+                       "Cannot find Power Management capability, aborting\n");
                err = -EIO;
                goto err_out_free_res;
        }
 
        dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
        if (!dev) {
-               pr_err("Etherdev alloc failed, aborting\n");
+               dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
                err = -ENOMEM;
                goto err_out_free_res;
        }
@@ -14508,7 +14420,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
 
        tp->regs = pci_ioremap_bar(pdev, BAR_0);
        if (!tp->regs) {
-               netdev_err(dev, "Cannot map device registers, aborting\n");
+               dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
                err = -ENOMEM;
                goto err_out_free_dev;
        }
@@ -14524,12 +14436,14 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
 
        err = tg3_get_invariants(tp);
        if (err) {
-               netdev_err(dev, "Problem fetching invariants of chip, aborting\n");
+               dev_err(&pdev->dev,
+                       "Problem fetching invariants of chip, aborting\n");
                goto err_out_iounmap;
        }
 
        if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
-           tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
+           tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 &&
+           GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
                dev->netdev_ops = &tg3_netdev_ops;
        else
                dev->netdev_ops = &tg3_netdev_ops_dma_bug;
@@ -14559,7 +14473,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
                        err = pci_set_consistent_dma_mask(pdev,
                                                          persist_dma_mask);
                        if (err < 0) {
-                               netdev_err(dev, "Unable to obtain 64 bit DMA for consistent allocations\n");
+                               dev_err(&pdev->dev, "Unable to obtain 64 bit "
+                                       "DMA for consistent allocations\n");
                                goto err_out_iounmap;
                        }
                }
@@ -14567,7 +14482,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
        if (err || dma_mask == DMA_BIT_MASK(32)) {
                err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
                if (err) {
-                       netdev_err(dev, "No usable DMA configuration, aborting\n");
+                       dev_err(&pdev->dev,
+                               "No usable DMA configuration, aborting\n");
                        goto err_out_iounmap;
                }
        }
@@ -14591,20 +14507,25 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
         * is off by default, but can be enabled using ethtool.
         */
        if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
-           (dev->features & NETIF_F_IP_CSUM))
+           (dev->features & NETIF_F_IP_CSUM)) {
                dev->features |= NETIF_F_TSO;
-
+               vlan_features_add(dev, NETIF_F_TSO);
+       }
        if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
            (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
-               if (dev->features & NETIF_F_IPV6_CSUM)
+               if (dev->features & NETIF_F_IPV6_CSUM) {
                        dev->features |= NETIF_F_TSO6;
+                       vlan_features_add(dev, NETIF_F_TSO6);
+               }
                if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
                     GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
                        GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
-                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
+                   GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
                        dev->features |= NETIF_F_TSO_ECN;
+                       vlan_features_add(dev, NETIF_F_TSO_ECN);
+               }
        }
 
        if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
@@ -14616,14 +14537,16 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
 
        err = tg3_get_device_address(tp);
        if (err) {
-               netdev_err(dev, "Could not obtain valid ethernet address, aborting\n");
+               dev_err(&pdev->dev,
+                       "Could not obtain valid ethernet address, aborting\n");
                goto err_out_iounmap;
        }
 
        if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
                tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
                if (!tp->aperegs) {
-                       netdev_err(dev, "Cannot map APE registers, aborting\n");
+                       dev_err(&pdev->dev,
+                               "Cannot map APE registers, aborting\n");
                        err = -ENOMEM;
                        goto err_out_iounmap;
                }
@@ -14647,7 +14570,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
 
        err = tg3_test_dma(tp);
        if (err) {
-               netdev_err(dev, "DMA engine test failed, aborting\n");
+               dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
                goto err_out_apeunmap;
        }
 
@@ -14708,7 +14631,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
 
        err = register_netdev(dev);
        if (err) {
-               netdev_err(dev, "Cannot register net device, aborting\n");
+               dev_err(&pdev->dev, "Cannot register net device, aborting\n");
                goto err_out_apeunmap;
        }
 
@@ -14718,23 +14641,31 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
                    tg3_bus_string(tp, str),
                    dev->dev_addr);
 
-       if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
+       if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
                struct phy_device *phydev;
                phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
-               netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
+               netdev_info(dev,
+                           "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
                            phydev->drv->name, dev_name(&phydev->dev));
-       } else
-               netdev_info(dev, "attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
-                           tg3_phy_string(tp),
-                           ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
-                            ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
-                             "10/100/1000Base-T")),
-                           (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
+       } else {
+               char *ethtype;
+
+               if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
+                       ethtype = "10/100Base-TX";
+               else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
+                       ethtype = "1000Base-SX";
+               else
+                       ethtype = "10/100/1000Base-T";
+
+               netdev_info(dev, "attached PHY is %s (%s Ethernet) "
+                           "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
+                         (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
+       }
 
        netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
                    (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
                    (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
-                   (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
+                   (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
                    (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
        netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",