tg3: cleanup pci device table vars
[linux-2.6.git] / drivers / net / tg3.c
index f2d96dd..73eacbd 100644 (file)
@@ -4,7 +4,7 @@
  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
  * Copyright (C) 2004 Sun Microsystems Inc.
- * Copyright (C) 2005-2010 Broadcom Corporation.
+ * Copyright (C) 2005-2011 Broadcom Corporation.
  *
  * Firmware is:
  *     Derived from proprietary unpublished source code,
@@ -32,6 +32,7 @@
 #include <linux/etherdevice.h>
 #include <linux/skbuff.h>
 #include <linux/ethtool.h>
+#include <linux/mdio.h>
 #include <linux/mii.h>
 #include <linux/phy.h>
 #include <linux/brcmphy.h>
 #define BAR_0  0
 #define BAR_2  2
 
-#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
-#define TG3_VLAN_TAG_USED 1
-#else
-#define TG3_VLAN_TAG_USED 0
-#endif
-
 #include "tg3.h"
 
 #define DRV_MODULE_NAME                "tg3"
 #define TG3_MAJ_NUM                    3
-#define TG3_MIN_NUM                    114
+#define TG3_MIN_NUM                    117
 #define DRV_MODULE_VERSION     \
        __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
-#define DRV_MODULE_RELDATE     "September 30, 2010"
+#define DRV_MODULE_RELDATE     "January 25, 2011"
 
 #define TG3_DEF_MAC_MODE       0
 #define TG3_DEF_RX_MODE                0
                                 TG3_TX_RING_SIZE)
 #define NEXT_TX(N)             (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 
-#define TG3_RX_DMA_ALIGN               16
-#define TG3_RX_HEADROOM                        ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
-
 #define TG3_DMA_BYTE_ENAB              64
 
 #define TG3_RX_STD_DMA_SZ              1536
@@ -1769,9 +1761,9 @@ static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
 
        if (tp->link_config.autoneg == AUTONEG_ENABLE &&
            current_link_up == 1 &&
-           (tp->link_config.active_speed == SPEED_1000 ||
-            (tp->link_config.active_speed == SPEED_100 &&
-             tp->link_config.active_duplex == DUPLEX_FULL))) {
+           tp->link_config.active_duplex == DUPLEX_FULL &&
+           (tp->link_config.active_speed == SPEED_100 ||
+            tp->link_config.active_speed == SPEED_1000)) {
                u32 eeectl;
 
                if (tp->link_config.active_speed == SPEED_1000)
@@ -1781,11 +1773,32 @@ static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
 
                tw32(TG3_CPMU_EEE_CTRL, eeectl);
 
-               tg3_phy_cl45_read(tp, 0x7, TG3_CL45_D7_EEERES_STAT, &val);
-
-               if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
-                   val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
+               tg3_phy_cl45_read(tp, MDIO_MMD_AN,
+                                 TG3_CL45_D7_EEERES_STAT, &val);
+
+               switch (val) {
+               case TG3_CL45_D7_EEERES_STAT_LP_1000T:
+                       switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
+                       case ASIC_REV_5717:
+                       case ASIC_REV_5719:
+                       case ASIC_REV_57765:
+                               /* Enable SM_DSP clock and tx 6dB coding. */
+                               val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
+                                     MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
+                                     MII_TG3_AUXCTL_ACTL_TX_6DB;
+                               tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
+
+                               tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
+
+                               /* Turn off SM_DSP clock. */
+                               val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
+                                     MII_TG3_AUXCTL_ACTL_TX_6DB;
+                               tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
+                       }
+                       /* Fallthrough */
+               case TG3_CL45_D7_EEERES_STAT_LP_100TX:
                        tp->setlpicnt = 2;
+               }
        }
 
        if (!tp->setlpicnt) {
@@ -2549,39 +2562,35 @@ static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
        tw32(MAC_TX_BACKOFF_SEED, addr_high);
 }
 
-static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
+static void tg3_enable_register_access(struct tg3 *tp)
 {
-       u32 misc_host_ctrl;
-       bool device_should_wake, do_low_power;
-
-       /* Make sure register accesses (indirect or otherwise)
-        * will function correctly.
+       /*
+        * Make sure register accesses (indirect or otherwise) will function
+        * correctly.
         */
        pci_write_config_dword(tp->pdev,
-                              TG3PCI_MISC_HOST_CTRL,
-                              tp->misc_host_ctrl);
+                              TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
+}
 
-       switch (state) {
-       case PCI_D0:
-               pci_enable_wake(tp->pdev, state, false);
-               pci_set_power_state(tp->pdev, PCI_D0);
+static int tg3_power_up(struct tg3 *tp)
+{
+       tg3_enable_register_access(tp);
 
-               /* Switch out of Vaux if it is a NIC */
-               if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
-                       tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
+       pci_set_power_state(tp->pdev, PCI_D0);
 
-               return 0;
+       /* Switch out of Vaux if it is a NIC */
+       if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
+               tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
 
-       case PCI_D1:
-       case PCI_D2:
-       case PCI_D3hot:
-               break;
+       return 0;
+}
 
-       default:
-               netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
-                          state);
-               return -EINVAL;
-       }
+static int tg3_power_down_prepare(struct tg3 *tp)
+{
+       u32 misc_host_ctrl;
+       bool device_should_wake, do_low_power;
+
+       tg3_enable_register_access(tp);
 
        /* Restore the CLKREQ setting. */
        if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
@@ -2600,8 +2609,7 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
        tw32(TG3PCI_MISC_HOST_CTRL,
             misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
 
-       device_should_wake = pci_pme_capable(tp->pdev, state) &&
-                            device_may_wakeup(&tp->pdev->dev) &&
+       device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
                             (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
 
        if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
@@ -2728,12 +2736,10 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
                     (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
                        mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
 
-               if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
-                       mac_mode |= tp->mac_mode &
-                                   (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
-                       if (mac_mode & MAC_MODE_APE_TX_EN)
-                               mac_mode |= MAC_MODE_TDE_ENABLE;
-               }
+               if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
+                       mac_mode |= MAC_MODE_APE_TX_EN |
+                                   MAC_MODE_APE_RX_EN |
+                                   MAC_MODE_TDE_ENABLE;
 
                tw32_f(MAC_MODE, mac_mode);
                udelay(100);
@@ -2823,13 +2829,15 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
 
        tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
 
-       if (device_should_wake)
-               pci_enable_wake(tp->pdev, state, true);
+       return 0;
+}
 
-       /* Finally, set the new power state. */
-       pci_set_power_state(tp->pdev, state);
+static void tg3_power_down(struct tg3 *tp)
+{
+       tg3_power_down_prepare(tp);
 
-       return 0;
+       pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
+       pci_set_power_state(tp->pdev, PCI_D3hot);
 }
 
 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
@@ -2969,7 +2977,7 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
        }
 
        if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
-               u32 val = 0;
+               u32 val;
 
                tw32(TG3_CPMU_EEE_MODE,
                     tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
@@ -2980,25 +2988,32 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
                      MII_TG3_AUXCTL_ACTL_TX_6DB;
                tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
 
-               if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
-                   !tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
-                       tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2,
-                                        val | MII_TG3_DSP_CH34TP2_HIBW01);
+               switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
+               case ASIC_REV_5717:
+               case ASIC_REV_57765:
+                       if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
+                               tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
+                                                MII_TG3_DSP_CH34TP2_HIBW01);
+                       /* Fall through */
+               case ASIC_REV_5719:
+                       val = MII_TG3_DSP_TAP26_ALNOKO |
+                             MII_TG3_DSP_TAP26_RMRXSTO |
+                             MII_TG3_DSP_TAP26_OPCSINPT;
+                       tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
+               }
 
+               val = 0;
                if (tp->link_config.autoneg == AUTONEG_ENABLE) {
                        /* Advertise 100-BaseTX EEE ability */
                        if (tp->link_config.advertising &
-                           (ADVERTISED_100baseT_Half |
-                            ADVERTISED_100baseT_Full))
-                               val |= TG3_CL45_D7_EEEADV_CAP_100TX;
+                           ADVERTISED_100baseT_Full)
+                               val |= MDIO_AN_EEE_ADV_100TX;
                        /* Advertise 1000-BaseT EEE ability */
                        if (tp->link_config.advertising &
-                           (ADVERTISED_1000baseT_Half |
-                            ADVERTISED_1000baseT_Full))
-                               val |= TG3_CL45_D7_EEEADV_CAP_1000T;
+                           ADVERTISED_1000baseT_Full)
+                               val |= MDIO_AN_EEE_ADV_1000T;
                }
-               tg3_phy_cl45_write(tp, 0x7, TG3_CL45_D7_EEEADV_CAP, val);
+               tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
 
                /* Turn off SM_DSP clock. */
                val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
@@ -4573,12 +4588,11 @@ static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
                            u32 opaque_key, u32 dest_idx_unmasked)
 {
        struct tg3_rx_buffer_desc *desc;
-       struct ring_info *map, *src_map;
+       struct ring_info *map;
        struct sk_buff *skb;
        dma_addr_t mapping;
        int skb_size, dest_idx;
 
-       src_map = NULL;
        switch (opaque_key) {
        case RXD_OPAQUE_RING_STD:
                dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
@@ -4727,8 +4741,6 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget)
                struct sk_buff *skb;
                dma_addr_t dma_addr;
                u32 opaque_key, desc_idx, *post_ptr;
-               bool hw_vlan __maybe_unused = false;
-               u16 vtag __maybe_unused = 0;
 
                desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
                opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
@@ -4755,7 +4767,7 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget)
                                       desc_idx, *post_ptr);
                drop_it_no_recycle:
                        /* Other statistics kept track of by card. */
-                       tp->net_stats.rx_dropped++;
+                       tp->rx_dropped++;
                        goto next_pkt;
                }
 
@@ -4787,12 +4799,12 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget)
                        tg3_recycle_rx(tnapi, tpr, opaque_key,
                                       desc_idx, *post_ptr);
 
-                       copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
+                       copy_skb = netdev_alloc_skb(tp->dev, len +
                                                    TG3_RAW_IP_ALIGN);
                        if (copy_skb == NULL)
                                goto drop_it_no_recycle;
 
-                       skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
+                       skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
                        skb_put(copy_skb, len);
                        pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
                        skb_copy_from_linear_data(skb, copy_skb->data, len);
@@ -4815,34 +4827,15 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget)
                if (len > (tp->dev->mtu + ETH_HLEN) &&
                    skb->protocol != htons(ETH_P_8021Q)) {
                        dev_kfree_skb(skb);
-                       goto next_pkt;
+                       goto drop_it_no_recycle;
                }
 
                if (desc->type_flags & RXD_FLAG_VLAN &&
-                   !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
-                       vtag = desc->err_vlan & RXD_VLAN_MASK;
-#if TG3_VLAN_TAG_USED
-                       if (tp->vlgrp)
-                               hw_vlan = true;
-                       else
-#endif
-                       {
-                               struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
-                                                   __skb_push(skb, VLAN_HLEN);
-
-                               memmove(ve, skb->data + VLAN_HLEN,
-                                       ETH_ALEN * 2);
-                               ve->h_vlan_proto = htons(ETH_P_8021Q);
-                               ve->h_vlan_TCI = htons(vtag);
-                       }
-               }
+                   !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
+                       __vlan_hwaccel_put_tag(skb,
+                                              desc->err_vlan & RXD_VLAN_MASK);
 
-#if TG3_VLAN_TAG_USED
-               if (hw_vlan)
-                       vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
-               else
-#endif
-                       napi_gro_receive(&tnapi->napi, skb);
+               napi_gro_receive(&tnapi->napi, skb);
 
                received++;
                budget--;
@@ -5745,11 +5738,9 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
                base_flags |= TXD_FLAG_TCPUDP_CSUM;
        }
 
-#if TG3_VLAN_TAG_USED
-       if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
+       if (vlan_tx_tag_present(skb))
                base_flags |= (TXD_FLAG_VLAN |
                               (vlan_tx_tag_get(skb) << 16));
-#endif
 
        len = skb_headlen(skb);
 
@@ -5764,7 +5755,7 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
        dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
 
        if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
-           !mss && skb->len > ETH_DATA_LEN)
+           !mss && skb->len > VLAN_ETH_FRAME_LEN)
                base_flags |= TXD_FLAG_JMB_PKT;
 
        tg3_set_txd(tnapi, entry, mapping, len, base_flags,
@@ -5991,14 +5982,13 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
                        }
                }
        }
-#if TG3_VLAN_TAG_USED
-       if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
+
+       if (vlan_tx_tag_present(skb))
                base_flags |= (TXD_FLAG_VLAN |
                               (vlan_tx_tag_get(skb) << 16));
-#endif
 
        if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
-           !mss && skb->len > ETH_DATA_LEN)
+           !mss && skb->len > VLAN_ETH_FRAME_LEN)
                base_flags |= TXD_FLAG_JMB_PKT;
 
        len = skb_headlen(skb);
@@ -6220,7 +6210,8 @@ static void tg3_rx_prodring_free(struct tg3 *tp,
                tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
                                tp->rx_pkt_map_sz);
 
-       if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
+       if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
+           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
                for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
                        tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
                                        TG3_RX_JMB_MAP_SZ);
@@ -6247,7 +6238,7 @@ static int tg3_rx_prodring_alloc(struct tg3 *tp,
        if (tpr != &tp->napi[0].prodring) {
                memset(&tpr->rx_std_buffers[0], 0,
                       TG3_RX_STD_BUFF_RING_SIZE(tp));
-               if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
+               if (tpr->rx_jmb_buffers)
                        memset(&tpr->rx_jmb_buffers[0], 0,
                               TG3_RX_JMB_BUFF_RING_SIZE(tp));
                goto done;
@@ -6290,7 +6281,8 @@ static int tg3_rx_prodring_alloc(struct tg3 *tp,
                }
        }
 
-       if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
+       if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ||
+           (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
                goto done;
 
        memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
@@ -6338,13 +6330,13 @@ static void tg3_rx_prodring_fini(struct tg3 *tp,
        kfree(tpr->rx_jmb_buffers);
        tpr->rx_jmb_buffers = NULL;
        if (tpr->rx_std) {
-               pci_free_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
-                                   tpr->rx_std, tpr->rx_std_mapping);
+               dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
+                                 tpr->rx_std, tpr->rx_std_mapping);
                tpr->rx_std = NULL;
        }
        if (tpr->rx_jmb) {
-               pci_free_consistent(tp->pdev, TG3_RX_JMB_RING_BYTES(tp),
-                                   tpr->rx_jmb, tpr->rx_jmb_mapping);
+               dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
+                                 tpr->rx_jmb, tpr->rx_jmb_mapping);
                tpr->rx_jmb = NULL;
        }
 }
@@ -6357,20 +6349,24 @@ static int tg3_rx_prodring_init(struct tg3 *tp,
        if (!tpr->rx_std_buffers)
                return -ENOMEM;
 
-       tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
-                                          &tpr->rx_std_mapping);
+       tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
+                                        TG3_RX_STD_RING_BYTES(tp),
+                                        &tpr->rx_std_mapping,
+                                        GFP_KERNEL);
        if (!tpr->rx_std)
                goto err_out;
 
-       if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
+       if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
+           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
                tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
                                              GFP_KERNEL);
                if (!tpr->rx_jmb_buffers)
                        goto err_out;
 
-               tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
-                                                  TG3_RX_JMB_RING_BYTES(tp),
-                                                  &tpr->rx_jmb_mapping);
+               tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
+                                                TG3_RX_JMB_RING_BYTES(tp),
+                                                &tpr->rx_jmb_mapping,
+                                                GFP_KERNEL);
                if (!tpr->rx_jmb)
                        goto err_out;
        }
@@ -6489,7 +6485,7 @@ static void tg3_free_consistent(struct tg3 *tp)
                struct tg3_napi *tnapi = &tp->napi[i];
 
                if (tnapi->tx_ring) {
-                       pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
+                       dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
                                tnapi->tx_ring, tnapi->tx_desc_mapping);
                        tnapi->tx_ring = NULL;
                }
@@ -6498,25 +6494,26 @@ static void tg3_free_consistent(struct tg3 *tp)
                tnapi->tx_buffers = NULL;
 
                if (tnapi->rx_rcb) {
-                       pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
-                                           tnapi->rx_rcb,
-                                           tnapi->rx_rcb_mapping);
+                       dma_free_coherent(&tp->pdev->dev,
+                                         TG3_RX_RCB_RING_BYTES(tp),
+                                         tnapi->rx_rcb,
+                                         tnapi->rx_rcb_mapping);
                        tnapi->rx_rcb = NULL;
                }
 
                tg3_rx_prodring_fini(tp, &tnapi->prodring);
 
                if (tnapi->hw_status) {
-                       pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
-                                           tnapi->hw_status,
-                                           tnapi->status_mapping);
+                       dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
+                                         tnapi->hw_status,
+                                         tnapi->status_mapping);
                        tnapi->hw_status = NULL;
                }
        }
 
        if (tp->hw_stats) {
-               pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
-                                   tp->hw_stats, tp->stats_mapping);
+               dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
+                                 tp->hw_stats, tp->stats_mapping);
                tp->hw_stats = NULL;
        }
 }
@@ -6529,9 +6526,10 @@ static int tg3_alloc_consistent(struct tg3 *tp)
 {
        int i;
 
-       tp->hw_stats = pci_alloc_consistent(tp->pdev,
-                                           sizeof(struct tg3_hw_stats),
-                                           &tp->stats_mapping);
+       tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
+                                         sizeof(struct tg3_hw_stats),
+                                         &tp->stats_mapping,
+                                         GFP_KERNEL);
        if (!tp->hw_stats)
                goto err_out;
 
@@ -6541,9 +6539,10 @@ static int tg3_alloc_consistent(struct tg3 *tp)
                struct tg3_napi *tnapi = &tp->napi[i];
                struct tg3_hw_status *sblk;
 
-               tnapi->hw_status = pci_alloc_consistent(tp->pdev,
-                                                       TG3_HW_STATUS_SIZE,
-                                                       &tnapi->status_mapping);
+               tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
+                                                     TG3_HW_STATUS_SIZE,
+                                                     &tnapi->status_mapping,
+                                                     GFP_KERNEL);
                if (!tnapi->hw_status)
                        goto err_out;
 
@@ -6564,9 +6563,10 @@ static int tg3_alloc_consistent(struct tg3 *tp)
                        if (!tnapi->tx_buffers)
                                goto err_out;
 
-                       tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
-                                                             TG3_TX_RING_BYTES,
-                                                      &tnapi->tx_desc_mapping);
+                       tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
+                                                           TG3_TX_RING_BYTES,
+                                                       &tnapi->tx_desc_mapping,
+                                                           GFP_KERNEL);
                        if (!tnapi->tx_ring)
                                goto err_out;
                }
@@ -6599,9 +6599,10 @@ static int tg3_alloc_consistent(struct tg3 *tp)
                if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
                        continue;
 
-               tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
-                                                    TG3_RX_RCB_RING_BYTES(tp),
-                                                    &tnapi->rx_rcb_mapping);
+               tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
+                                                  TG3_RX_RCB_RING_BYTES(tp),
+                                                  &tnapi->rx_rcb_mapping,
+                                                  GFP_KERNEL);
                if (!tnapi->rx_rcb)
                        goto err_out;
 
@@ -6985,7 +6986,7 @@ static void tg3_restore_pci_state(struct tg3 *tp)
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
                if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
-                       pcie_set_readrq(tp->pdev, 4096);
+                       pcie_set_readrq(tp->pdev, tp->pcie_readrq);
                else {
                        pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
                                              tp->pci_cacheline_sz);
@@ -7179,7 +7180,7 @@ static int tg3_chip_reset(struct tg3 *tp)
                                      tp->pcie_cap + PCI_EXP_DEVCTL,
                                      val16);
 
-               pcie_set_readrq(tp->pdev, 4096);
+               pcie_set_readrq(tp->pdev, tp->pcie_readrq);
 
                /* Clear error status */
                pci_write_config_word(tp->pdev,
@@ -7220,19 +7221,21 @@ static int tg3_chip_reset(struct tg3 *tp)
                tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
        }
 
+       if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
+               tp->mac_mode = MAC_MODE_APE_TX_EN |
+                              MAC_MODE_APE_RX_EN |
+                              MAC_MODE_TDE_ENABLE;
+
        if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
-               tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
-               tw32_f(MAC_MODE, tp->mac_mode);
+               tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
+               val = tp->mac_mode;
        } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
-               tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
-               tw32_f(MAC_MODE, tp->mac_mode);
-       } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
-               tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
-               if (tp->mac_mode & MAC_MODE_APE_TX_EN)
-                       tp->mac_mode |= MAC_MODE_TDE_ENABLE;
-               tw32_f(MAC_MODE, tp->mac_mode);
+               tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
+               val = tp->mac_mode;
        } else
-               tw32_f(MAC_MODE, 0);
+               val = 0;
+
+       tw32_f(MAC_MODE, val);
        udelay(40);
 
        tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
@@ -7799,6 +7802,37 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
                tg3_abort_hw(tp, 1);
 
+       /* Enable MAC control of LPI */
+       if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
+               tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
+                      TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
+                      TG3_CPMU_EEE_LNKIDL_UART_IDL);
+
+               tw32_f(TG3_CPMU_EEE_CTRL,
+                      TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
+
+               val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
+                     TG3_CPMU_EEEMD_LPI_IN_TX |
+                     TG3_CPMU_EEEMD_LPI_IN_RX |
+                     TG3_CPMU_EEEMD_EEE_ENABLE;
+
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
+                       val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
+
+               if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
+                       val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
+
+               tw32_f(TG3_CPMU_EEE_MODE, val);
+
+               tw32_f(TG3_CPMU_EEE_DBTMR1,
+                      TG3_CPMU_DBTMR1_PCIEXIT_2047US |
+                      TG3_CPMU_DBTMR1_LNKIDLE_2047US);
+
+               tw32_f(TG3_CPMU_EEE_DBTMR2,
+                      TG3_CPMU_DBTMR2_APE_TX_2047US |
+                      TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
+       }
+
        if (reset_phy)
                tg3_phy_reset(tp);
 
@@ -7858,18 +7892,21 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                tw32(GRC_MODE, grc_mode);
        }
 
-       if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
-               u32 grc_mode = tr32(GRC_MODE);
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
+               if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
+                       u32 grc_mode = tr32(GRC_MODE);
 
-               /* Access the lower 1K of PL PCIE block registers. */
-               val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
-               tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
+                       /* Access the lower 1K of PL PCIE block registers. */
+                       val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
+                       tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
 
-               val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
-               tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
-                    val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
+                       val = tr32(TG3_PCIE_TLDLPL_PORT +
+                                  TG3_PCIE_PL_LO_PHYCTL5);
+                       tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
+                            val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
 
-               tw32(GRC_MODE, grc_mode);
+                       tw32(GRC_MODE, grc_mode);
+               }
 
                val = tr32(TG3_CPMU_LSPD_10MB_CLK);
                val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
@@ -7877,22 +7914,6 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                tw32(TG3_CPMU_LSPD_10MB_CLK, val);
        }
 
-       /* Enable MAC control of LPI */
-       if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
-               tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
-                      TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
-                      TG3_CPMU_EEE_LNKIDL_UART_IDL);
-
-               tw32_f(TG3_CPMU_EEE_CTRL,
-                      TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
-
-               tw32_f(TG3_CPMU_EEE_MODE,
-                      TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
-                      TG3_CPMU_EEEMD_LPI_IN_TX |
-                      TG3_CPMU_EEEMD_LPI_IN_RX |
-                      TG3_CPMU_EEEMD_EEE_ENABLE);
-       }
-
        /* This works around an issue with Athlon chipsets on
         * B3 tigon3 silicon.  This bit has no effect on any
         * other revision.  But do not set this on PCI Express
@@ -8082,8 +8103,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        /* Program the jumbo buffer descriptor ring control
         * blocks on those devices that have them.
         */
-       if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
-           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
+           ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
+           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))) {
                /* Setup replenish threshold. */
                tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
 
@@ -8160,8 +8182,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                      RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
                      RDMAC_MODE_LNGREAD_ENAB);
 
-       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
                rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
 
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
@@ -8201,6 +8222,14 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
            (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
                val = tr32(TG3_RDMA_RSRVCTRL_REG);
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
+                       val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
+                                TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
+                                TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
+                       val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
+                              TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
+                              TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
+               }
                tw32(TG3_RDMA_RSRVCTRL_REG,
                     val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
        }
@@ -8278,7 +8307,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        }
 
        if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
-               tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
+               tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
        else
                tp->mac_mode = 0;
        tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
@@ -8321,7 +8350,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
        udelay(100);
 
-       if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
+       if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
+               tp->irq_cnt > 1) {
                val = tr32(MSGINT_MODE);
                val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
                tw32(MSGINT_MODE, val);
@@ -9029,8 +9059,14 @@ static bool tg3_enable_msix(struct tg3 *tp)
                pci_disable_msix(tp->pdev);
                return false;
        }
-       if (tp->irq_cnt > 1)
+
+       if (tp->irq_cnt > 1) {
                tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
+                       tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
+                       netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
+               }
+       }
 
        return true;
 }
@@ -9055,7 +9091,8 @@ static void tg3_ints_init(struct tg3 *tp)
 
        if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
                u32 msi_mode = tr32(MSGINT_MODE);
-               if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
+               if ((tp->tg3_flags2 & TG3_FLG2_USING_MSIX) &&
+                   tp->irq_cnt > 1)
                        msi_mode |= MSGINT_MODE_MULTIVEC_EN;
                tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
        }
@@ -9099,7 +9136,7 @@ static int tg3_open(struct net_device *dev)
 
        netif_carrier_off(tp->dev);
 
-       err = tg3_set_power_state(tp, PCI_D0);
+       err = tg3_power_up(tp);
        if (err)
                return err;
 
@@ -9264,7 +9301,7 @@ static int tg3_close(struct net_device *dev)
 
        tg3_free_consistent(tp);
 
-       tg3_set_power_state(tp, PCI_D3hot);
+       tg3_power_down(tp);
 
        netif_carrier_off(tp->dev);
 
@@ -9451,6 +9488,8 @@ static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
        stats->rx_missed_errors = old_stats->rx_missed_errors +
                get_stat64(&hw_stats->rx_discards);
 
+       stats->rx_dropped = tp->rx_dropped;
+
        return stats;
 }
 
@@ -9495,17 +9534,10 @@ static void __tg3_set_rx_mode(struct net_device *dev)
        rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
                                  RX_MODE_KEEP_VLAN_TAG);
 
+#if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
        /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
         * flag clear.
         */
-#if TG3_VLAN_TAG_USED
-       if (!tp->vlgrp &&
-           !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
-               rx_mode |= RX_MODE_KEEP_VLAN_TAG;
-#else
-       /* By definition, VLAN is disabled always in this
-        * case.
-        */
        if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
                rx_mode |= RX_MODE_KEEP_VLAN_TAG;
 #endif
@@ -9805,6 +9837,9 @@ static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
        if (netif_running(dev)) {
                cmd->speed = tp->link_config.active_speed;
                cmd->duplex = tp->link_config.active_duplex;
+       } else {
+               cmd->speed = SPEED_INVALID;
+               cmd->duplex = DUPLEX_INVALID;
        }
        cmd->phy_address = tp->phy_addr;
        cmd->transceiver = XCVR_INTERNAL;
@@ -9941,16 +9976,16 @@ static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
            !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
                return -EINVAL;
 
+       device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
+
        spin_lock_bh(&tp->lock);
-       if (wol->wolopts & WAKE_MAGIC) {
+       if (device_may_wakeup(dp))
                tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
-               device_set_wakeup_enable(dp, true);
-       } else {
+       else
                tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
-               device_set_wakeup_enable(dp, false);
-       }
        spin_unlock_bh(&tp->lock);
 
+
        return 0;
 }
 
@@ -10452,16 +10487,53 @@ static int tg3_test_nvram(struct tg3 *tp)
                goto out;
        }
 
+       err = -EIO;
+
        /* Bootstrap checksum at offset 0x10 */
        csum = calc_crc((unsigned char *) buf, 0x10);
-       if (csum != be32_to_cpu(buf[0x10/4]))
+       if (csum != le32_to_cpu(buf[0x10/4]))
                goto out;
 
        /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
        csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
-       if (csum != be32_to_cpu(buf[0xfc/4]))
+       if (csum != le32_to_cpu(buf[0xfc/4]))
                goto out;
 
+       for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
+               /* The data is in little-endian format in NVRAM.
+                * Use the big-endian read routines to preserve
+                * the byte order as it exists in NVRAM.
+                */
+               if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &buf[i/4]))
+                       goto out;
+       }
+
+       i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN,
+                            PCI_VPD_LRDT_RO_DATA);
+       if (i > 0) {
+               j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
+               if (j < 0)
+                       goto out;
+
+               if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN)
+                       goto out;
+
+               i += PCI_VPD_LRDT_TAG_SIZE;
+               j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
+                                             PCI_VPD_RO_KEYWORD_CHKSUM);
+               if (j > 0) {
+                       u8 csum8 = 0;
+
+                       j += PCI_VPD_INFO_FLD_HDR_SIZE;
+
+                       for (i = 0; i <= j; i++)
+                               csum8 += ((u8 *)buf)[i];
+
+                       if (csum8)
+                               goto out;
+               }
+       }
+
        err = 0;
 
 out:
@@ -10833,13 +10905,16 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
        if (loopback_mode == TG3_MAC_LOOPBACK) {
                /* HW errata - mac loopback fails in some cases on 5780.
                 * Normal traffic and PHY loopback are not affected by
-                * errata.
+                * errata.  Also, the MAC loopback test is deprecated for
+                * all newer ASIC revisions.
                 */
-               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
+                   (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
                        return 0;
 
-               mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
-                          MAC_MODE_PORT_INT_LPBACK;
+               mac_mode = tp->mac_mode &
+                          ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
+               mac_mode |= MAC_MODE_PORT_INT_LPBACK;
                if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
                        mac_mode |= MAC_MODE_LINK_POLARITY;
                if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
@@ -10861,7 +10936,8 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
                tg3_writephy(tp, MII_BMCR, val);
                udelay(40);
 
-               mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
+               mac_mode = tp->mac_mode &
+                          ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
                if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
                        tg3_writephy(tp, MII_TG3_FET_PTEST,
                                     MII_TG3_FET_PTEST_FRC_TX_LINK |
@@ -10889,6 +10965,13 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
                                     MII_TG3_EXT_CTRL_LNK3_LED_MODE);
                }
                tw32(MAC_MODE, mac_mode);
+
+               /* Wait for link */
+               for (i = 0; i < 100; i++) {
+                       if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
+                               break;
+                       mdelay(1);
+               }
        } else {
                return -EINVAL;
        }
@@ -10995,14 +11078,19 @@ out:
 static int tg3_test_loopback(struct tg3 *tp)
 {
        int err = 0;
-       u32 cpmuctrl = 0;
+       u32 eee_cap, cpmuctrl = 0;
 
        if (!netif_running(tp->dev))
                return TG3_LOOPBACK_FAILED;
 
+       eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
+       tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
+
        err = tg3_reset_hw(tp, 1);
-       if (err)
-               return TG3_LOOPBACK_FAILED;
+       if (err) {
+               err = TG3_LOOPBACK_FAILED;
+               goto done;
+       }
 
        /* Turn off gphy autopowerdown. */
        if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
@@ -11022,8 +11110,10 @@ static int tg3_test_loopback(struct tg3 *tp)
                        udelay(10);
                }
 
-               if (status != CPMU_MUTEX_GNT_DRIVER)
-                       return TG3_LOOPBACK_FAILED;
+               if (status != CPMU_MUTEX_GNT_DRIVER) {
+                       err = TG3_LOOPBACK_FAILED;
+                       goto done;
+               }
 
                /* Turn off link-based power management. */
                cpmuctrl = tr32(TG3_CPMU_CTRL);
@@ -11052,6 +11142,9 @@ static int tg3_test_loopback(struct tg3 *tp)
        if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
                tg3_phy_toggle_apd(tp, true);
 
+done:
+       tp->phy_flags |= eee_cap;
+
        return err;
 }
 
@@ -11061,7 +11154,7 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
        struct tg3 *tp = netdev_priv(dev);
 
        if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
-               tg3_set_power_state(tp, PCI_D0);
+               tg3_power_up(tp);
 
        memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
 
@@ -11129,7 +11222,7 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
                        tg3_phy_start(tp);
        }
        if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
-               tg3_set_power_state(tp, PCI_D3hot);
+               tg3_power_down(tp);
 
 }
 
@@ -11158,7 +11251,9 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
                if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
                        break;                  /* We have no PHY */
 
-               if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
+               if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) ||
+                   ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
+                    !netif_running(dev)))
                        return -EAGAIN;
 
                spin_lock_bh(&tp->lock);
@@ -11174,7 +11269,9 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
                if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
                        break;                  /* We have no PHY */
 
-               if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
+               if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) ||
+                   ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
+                    !netif_running(dev)))
                        return -EAGAIN;
 
                spin_lock_bh(&tp->lock);
@@ -11190,31 +11287,6 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
        return -EOPNOTSUPP;
 }
 
-#if TG3_VLAN_TAG_USED
-static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
-{
-       struct tg3 *tp = netdev_priv(dev);
-
-       if (!netif_running(dev)) {
-               tp->vlgrp = grp;
-               return;
-       }
-
-       tg3_netif_stop(tp);
-
-       tg3_full_lock(tp, 0);
-
-       tp->vlgrp = grp;
-
-       /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
-       __tg3_set_rx_mode(dev);
-
-       tg3_netif_start(tp);
-
-       tg3_full_unlock(tp);
-}
-#endif
-
 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
 {
        struct tg3 *tp = netdev_priv(dev);
@@ -12404,8 +12476,9 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
                if (cfg2 & (1 << 18))
                        tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
 
-               if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
-                     GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
+               if (((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) ||
+                   ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
+                     GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) &&
                    (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
                        tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
 
@@ -12427,9 +12500,11 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
                        tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
        }
 done:
-       device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
-       device_set_wakeup_enable(&tp->pdev->dev,
+       if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
+               device_set_wakeup_enable(&tp->pdev->dev,
                                 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
+       else
+               device_set_wakeup_capable(&tp->pdev->dev, false);
 }
 
 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
@@ -12541,9 +12616,11 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
                }
        }
 
-       if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
-           (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
-            tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))
+       if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
+           ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
+             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
+            (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
+             tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
                tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
 
        if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
@@ -12651,7 +12728,7 @@ static void __devinit tg3_read_vpd(struct tg3 *tp)
                        cnt = pci_read_vpd(tp->pdev, pos,
                                           TG3_NVM_VPD_LEN - pos,
                                           &vpd_data[pos]);
-                       if (cnt == -ETIMEDOUT || -EINTR)
+                       if (cnt == -ETIMEDOUT || cnt == -EINTR)
                                cnt = 0;
                        else if (cnt < 0)
                                goto out_not_found;
@@ -13023,9 +13100,7 @@ static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
 
 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
 {
-#if TG3_VLAN_TAG_USED
        dev->vlan_features |= flags;
-#endif
 }
 
 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
@@ -13040,17 +13115,15 @@ static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
                return 512;
 }
 
+static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
+       { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
+       { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
+       { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
+       { },
+};
+
 static int __devinit tg3_get_invariants(struct tg3 *tp)
 {
-       static struct pci_device_id write_reorder_chipsets[] = {
-               { PCI_DEVICE(PCI_VENDOR_ID_AMD,
-                            PCI_DEVICE_ID_AMD_FE_GATE_700C) },
-               { PCI_DEVICE(PCI_VENDOR_ID_AMD,
-                            PCI_DEVICE_ID_AMD_8131_BRIDGE) },
-               { PCI_DEVICE(PCI_VENDOR_ID_VIA,
-                            PCI_DEVICE_ID_VIA_8385_0) },
-               { },
-       };
        u32 misc_ctrl_reg;
        u32 pci_state_reg, grc_misc_cfg;
        u32 val;
@@ -13284,7 +13357,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
        }
 
        /* Determine TSO capabilities */
-       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
+               ; /* Do nothing. HW bug. */
+       else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
                tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
        else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
                 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
@@ -13335,7 +13410,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
        }
 
-       if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
+       if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
+           GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
                tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
 
        if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
@@ -13352,7 +13428,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
 
                tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
 
-               pcie_set_readrq(tp->pdev, 4096);
+               tp->pcie_readrq = 4096;
+               if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
+                       tp->pcie_readrq = 2048;
+
+               pcie_set_readrq(tp->pdev, tp->pcie_readrq);
 
                pci_read_config_word(tp->pdev,
                                     tp->pcie_cap + PCI_EXP_LNKCTL,
@@ -13389,7 +13469,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
         * every mailbox register write to force the writes to be
         * posted to the chip in order.
         */
-       if (pci_dev_present(write_reorder_chipsets) &&
+       if (pci_dev_present(tg3_write_reorder_chipsets) &&
            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
                tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
 
@@ -13539,7 +13619,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
            (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
                tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
 
-       /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
+       /* Set up tp->grc_local_ctrl before calling tg_power_up().
         * GPIO1 driven high will bring 5700's external PHY out of reset.
         * It is also used as eeprom write protect on LOMs.
         */
@@ -13570,7 +13650,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
        }
 
        /* Force the chip into D0. */
-       err = tg3_set_power_state(tp, PCI_D0);
+       err = tg3_power_up(tp);
        if (err) {
                dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
                return err;
@@ -13715,8 +13795,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
 
        /* Preserve the APE MAC_MODE bits */
        if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
-               tp->mac_mode = tr32(MAC_MODE) |
-                              MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
+               tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
        else
                tp->mac_mode = TG3_DEF_MAC_MODE;
 
@@ -13783,11 +13862,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
        else
                tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
 
-       tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
+       tp->rx_offset = NET_IP_ALIGN;
        tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
            (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
-               tp->rx_offset -= NET_IP_ALIGN;
+               tp->rx_offset = 0;
 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
                tp->rx_copy_thresh = ~(u16)0;
 #endif
@@ -14146,13 +14225,19 @@ static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dm
 
 #define TEST_BUFFER_SIZE       0x2000
 
+static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
+       { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
+       { },
+};
+
 static int __devinit tg3_test_dma(struct tg3 *tp)
 {
        dma_addr_t buf_dma;
        u32 *buf, saved_dma_rwctrl;
        int ret = 0;
 
-       buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
+       buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
+                                &buf_dma, GFP_KERNEL);
        if (!buf) {
                ret = -ENOMEM;
                goto out_nofree;
@@ -14314,17 +14399,12 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
        }
        if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
            DMA_RWCTRL_WRITE_BNDRY_16) {
-               static struct pci_device_id dma_wait_state_chipsets[] = {
-                       { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
-                                    PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
-                       { },
-               };
 
                /* DMA test passed without adjusting DMA boundary,
                 * now look for chipsets that are known to expose the
                 * DMA bug without failing the test.
                 */
-               if (pci_dev_present(dma_wait_state_chipsets)) {
+               if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
                        tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
                        tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
                } else {
@@ -14336,7 +14416,7 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
        }
 
 out:
-       pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
+       dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
 out_nofree:
        return ret;
 }
@@ -14550,9 +14630,6 @@ static const struct net_device_ops tg3_netdev_ops = {
        .ndo_do_ioctl           = tg3_ioctl,
        .ndo_tx_timeout         = tg3_tx_timeout,
        .ndo_change_mtu         = tg3_change_mtu,
-#if TG3_VLAN_TAG_USED
-       .ndo_vlan_rx_register   = tg3_vlan_rx_register,
-#endif
 #ifdef CONFIG_NET_POLL_CONTROLLER
        .ndo_poll_controller    = tg3_poll_controller,
 #endif
@@ -14569,9 +14646,6 @@ static const struct net_device_ops tg3_netdev_ops_dma_bug = {
        .ndo_do_ioctl           = tg3_ioctl,
        .ndo_tx_timeout         = tg3_tx_timeout,
        .ndo_change_mtu         = tg3_change_mtu,
-#if TG3_VLAN_TAG_USED
-       .ndo_vlan_rx_register   = tg3_vlan_rx_register,
-#endif
 #ifdef CONFIG_NET_POLL_CONTROLLER
        .ndo_poll_controller    = tg3_poll_controller,
 #endif
@@ -14621,9 +14695,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
 
        SET_NETDEV_DEV(dev, &pdev->dev);
 
-#if TG3_VLAN_TAG_USED
        dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
-#endif
 
        tp = netdev_priv(dev);
        tp->pdev = pdev;
@@ -14950,7 +15022,7 @@ static void __devexit tg3_remove_one(struct pci_dev *pdev)
                if (tp->fw)
                        release_firmware(tp->fw);
 
-               flush_scheduled_work();
+               cancel_work_sync(&tp->reset_task);
 
                if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
                        tg3_phy_fini(tp);
@@ -14973,23 +15045,18 @@ static void __devexit tg3_remove_one(struct pci_dev *pdev)
        }
 }
 
-static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
+#ifdef CONFIG_PM_SLEEP
+static int tg3_suspend(struct device *device)
 {
+       struct pci_dev *pdev = to_pci_dev(device);
        struct net_device *dev = pci_get_drvdata(pdev);
        struct tg3 *tp = netdev_priv(dev);
-       pci_power_t target_state;
        int err;
 
-       /* PCI register 4 needs to be saved whether netif_running() or not.
-        * MSI address and data need to be saved if using MSI and
-        * netif_running().
-        */
-       pci_save_state(pdev);
-
        if (!netif_running(dev))
                return 0;
 
-       flush_scheduled_work();
+       flush_work_sync(&tp->reset_task);
        tg3_phy_stop(tp);
        tg3_netif_stop(tp);
 
@@ -15006,9 +15073,7 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
        tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
        tg3_full_unlock(tp);
 
-       target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
-
-       err = tg3_set_power_state(tp, target_state);
+       err = tg3_power_down_prepare(tp);
        if (err) {
                int err2;
 
@@ -15035,21 +15100,16 @@ out:
        return err;
 }
 
-static int tg3_resume(struct pci_dev *pdev)
+static int tg3_resume(struct device *device)
 {
+       struct pci_dev *pdev = to_pci_dev(device);
        struct net_device *dev = pci_get_drvdata(pdev);
        struct tg3 *tp = netdev_priv(dev);
        int err;
 
-       pci_restore_state(tp->pdev);
-
        if (!netif_running(dev))
                return 0;
 
-       err = tg3_set_power_state(tp, PCI_D0);
-       if (err)
-               return err;
-
        netif_device_attach(dev);
 
        tg3_full_lock(tp, 0);
@@ -15073,13 +15133,21 @@ out:
        return err;
 }
 
+static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
+#define TG3_PM_OPS (&tg3_pm_ops)
+
+#else
+
+#define TG3_PM_OPS NULL
+
+#endif /* CONFIG_PM_SLEEP */
+
 static struct pci_driver tg3_driver = {
        .name           = DRV_MODULE_NAME,
        .id_table       = tg3_pci_tbl,
        .probe          = tg3_init_one,
        .remove         = __devexit_p(tg3_remove_one),
-       .suspend        = tg3_suspend,
-       .resume         = tg3_resume
+       .driver.pm      = TG3_PM_OPS,
 };
 
 static int __init tg3_init(void)