tg3: cleanup pci device table vars
[linux-2.6.git] / drivers / net / tg3.c
index c333481..73eacbd 100644 (file)
@@ -4,7 +4,7 @@
  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
  * Copyright (C) 2004 Sun Microsystems Inc.
- * Copyright (C) 2005-2010 Broadcom Corporation.
+ * Copyright (C) 2005-2011 Broadcom Corporation.
  *
  * Firmware is:
  *     Derived from proprietary unpublished source code,
 
 #define DRV_MODULE_NAME                "tg3"
 #define TG3_MAJ_NUM                    3
-#define TG3_MIN_NUM                    116
+#define TG3_MIN_NUM                    117
 #define DRV_MODULE_VERSION     \
        __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
-#define DRV_MODULE_RELDATE     "December 3, 2010"
+#define DRV_MODULE_RELDATE     "January 25, 2011"
 
 #define TG3_DEF_MAC_MODE       0
 #define TG3_DEF_RX_MODE                0
@@ -1776,9 +1776,29 @@ static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
                tg3_phy_cl45_read(tp, MDIO_MMD_AN,
                                  TG3_CL45_D7_EEERES_STAT, &val);
 
-               if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
-                   val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
+               switch (val) {
+               case TG3_CL45_D7_EEERES_STAT_LP_1000T:
+                       switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
+                       case ASIC_REV_5717:
+                       case ASIC_REV_5719:
+                       case ASIC_REV_57765:
+                               /* Enable SM_DSP clock and tx 6dB coding. */
+                               val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
+                                     MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
+                                     MII_TG3_AUXCTL_ACTL_TX_6DB;
+                               tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
+
+                               tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
+
+                               /* Turn off SM_DSP clock. */
+                               val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
+                                     MII_TG3_AUXCTL_ACTL_TX_6DB;
+                               tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
+                       }
+                       /* Fallthrough */
+               case TG3_CL45_D7_EEERES_STAT_LP_100TX:
                        tp->setlpicnt = 2;
+               }
        }
 
        if (!tp->setlpicnt) {
@@ -2968,11 +2988,19 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
                      MII_TG3_AUXCTL_ACTL_TX_6DB;
                tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
 
-               if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
-                   !tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
-                       tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2,
-                                        val | MII_TG3_DSP_CH34TP2_HIBW01);
+               switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
+               case ASIC_REV_5717:
+               case ASIC_REV_57765:
+                       if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
+                               tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
+                                                MII_TG3_DSP_CH34TP2_HIBW01);
+                       /* Fall through */
+               case ASIC_REV_5719:
+                       val = MII_TG3_DSP_TAP26_ALNOKO |
+                             MII_TG3_DSP_TAP26_RMRXSTO |
+                             MII_TG3_DSP_TAP26_OPCSINPT;
+                       tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
+               }
 
                val = 0;
                if (tp->link_config.autoneg == AUTONEG_ENABLE) {
@@ -7801,7 +7829,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                       TG3_CPMU_DBTMR1_LNKIDLE_2047US);
 
                tw32_f(TG3_CPMU_EEE_DBTMR2,
-                      TG3_CPMU_DBTMR1_APE_TX_2047US |
+                      TG3_CPMU_DBTMR2_APE_TX_2047US |
                       TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
        }
 
@@ -8075,7 +8103,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        /* Program the jumbo buffer descriptor ring control
         * blocks on those devices that have them.
         */
-       if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
            ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
            !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))) {
                /* Setup replenish threshold. */
@@ -10459,16 +10487,53 @@ static int tg3_test_nvram(struct tg3 *tp)
                goto out;
        }
 
+       err = -EIO;
+
        /* Bootstrap checksum at offset 0x10 */
        csum = calc_crc((unsigned char *) buf, 0x10);
-       if (csum != be32_to_cpu(buf[0x10/4]))
+       if (csum != le32_to_cpu(buf[0x10/4]))
                goto out;
 
        /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
        csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
-       if (csum != be32_to_cpu(buf[0xfc/4]))
+       if (csum != le32_to_cpu(buf[0xfc/4]))
                goto out;
 
+       for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
+               /* The data is in little-endian format in NVRAM.
+                * Use the big-endian read routines to preserve
+                * the byte order as it exists in NVRAM.
+                */
+               if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &buf[i/4]))
+                       goto out;
+       }
+
+       i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN,
+                            PCI_VPD_LRDT_RO_DATA);
+       if (i > 0) {
+               j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
+               if (j < 0)
+                       goto out;
+
+               if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN)
+                       goto out;
+
+               i += PCI_VPD_LRDT_TAG_SIZE;
+               j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
+                                             PCI_VPD_RO_KEYWORD_CHKSUM);
+               if (j > 0) {
+                       u8 csum8 = 0;
+
+                       j += PCI_VPD_INFO_FLD_HDR_SIZE;
+
+                       for (i = 0; i <= j; i++)
+                               csum8 += ((u8 *)buf)[i];
+
+                       if (csum8)
+                               goto out;
+               }
+       }
+
        err = 0;
 
 out:
@@ -12435,9 +12500,11 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
                        tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
        }
 done:
-       device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
-       device_set_wakeup_enable(&tp->pdev->dev,
+       if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
+               device_set_wakeup_enable(&tp->pdev->dev,
                                 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
+       else
+               device_set_wakeup_capable(&tp->pdev->dev, false);
 }
 
 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
@@ -13048,7 +13115,7 @@ static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
                return 512;
 }
 
-DEFINE_PCI_DEVICE_TABLE(write_reorder_chipsets) = {
+static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
        { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
@@ -13290,7 +13357,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
        }
 
        /* Determine TSO capabilities */
-       if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0)
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
                ; /* Do nothing. HW bug. */
        else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
                tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
@@ -13344,7 +13411,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
        }
 
        if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
-           tp->pci_chip_rev_id != CHIPREV_ID_5719_A0)
+           GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
                tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
 
        if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
@@ -13402,7 +13469,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
         * every mailbox register write to force the writes to be
         * posted to the chip in order.
         */
-       if (pci_dev_present(write_reorder_chipsets) &&
+       if (pci_dev_present(tg3_write_reorder_chipsets) &&
            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
                tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
 
@@ -14158,7 +14225,7 @@ static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dm
 
 #define TEST_BUFFER_SIZE       0x2000
 
-DEFINE_PCI_DEVICE_TABLE(dma_wait_state_chipsets) = {
+static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
        { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
        { },
 };
@@ -14337,7 +14404,7 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
                 * now look for chipsets that are known to expose the
                 * DMA bug without failing the test.
                 */
-               if (pci_dev_present(dma_wait_state_chipsets)) {
+               if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
                        tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
                        tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
                } else {