tg3: cleanup pci device table vars
[linux-2.6.git] / drivers / net / tg3.c
index 6be4185..73eacbd 100644 (file)
@@ -8103,7 +8103,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
        /* Program the jumbo buffer descriptor ring control
         * blocks on those devices that have them.
         */
-       if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
+       if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
            ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
            !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))) {
                /* Setup replenish threshold. */
@@ -10487,16 +10487,53 @@ static int tg3_test_nvram(struct tg3 *tp)
                goto out;
        }
 
+       err = -EIO;
+
        /* Bootstrap checksum at offset 0x10 */
        csum = calc_crc((unsigned char *) buf, 0x10);
-       if (csum != be32_to_cpu(buf[0x10/4]))
+       if (csum != le32_to_cpu(buf[0x10/4]))
                goto out;
 
        /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
        csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
-       if (csum != be32_to_cpu(buf[0xfc/4]))
+       if (csum != le32_to_cpu(buf[0xfc/4]))
                goto out;
 
+       for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
+               /* The data is in little-endian format in NVRAM.
+                * Use the big-endian read routines to preserve
+                * the byte order as it exists in NVRAM.
+                */
+               if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &buf[i/4]))
+                       goto out;
+       }
+
+       i = pci_vpd_find_tag((u8 *)buf, 0, TG3_NVM_VPD_LEN,
+                            PCI_VPD_LRDT_RO_DATA);
+       if (i > 0) {
+               j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
+               if (j < 0)
+                       goto out;
+
+               if (i + PCI_VPD_LRDT_TAG_SIZE + j > TG3_NVM_VPD_LEN)
+                       goto out;
+
+               i += PCI_VPD_LRDT_TAG_SIZE;
+               j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
+                                             PCI_VPD_RO_KEYWORD_CHKSUM);
+               if (j > 0) {
+                       u8 csum8 = 0;
+
+                       j += PCI_VPD_INFO_FLD_HDR_SIZE;
+
+                       for (i = 0; i <= j; i++)
+                               csum8 += ((u8 *)buf)[i];
+
+                       if (csum8)
+                               goto out;
+               }
+       }
+
        err = 0;
 
 out:
@@ -13078,7 +13115,7 @@ static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
                return 512;
 }
 
-DEFINE_PCI_DEVICE_TABLE(write_reorder_chipsets) = {
+static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
        { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
@@ -13432,7 +13469,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
         * every mailbox register write to force the writes to be
         * posted to the chip in order.
         */
-       if (pci_dev_present(write_reorder_chipsets) &&
+       if (pci_dev_present(tg3_write_reorder_chipsets) &&
            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
                tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
 
@@ -14188,7 +14225,7 @@ static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dm
 
 #define TEST_BUFFER_SIZE       0x2000
 
-DEFINE_PCI_DEVICE_TABLE(dma_wait_state_chipsets) = {
+static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
        { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
        { },
 };
@@ -14367,7 +14404,7 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
                 * now look for chipsets that are known to expose the
                 * DMA bug without failing the test.
                 */
-               if (pci_dev_present(dma_wait_state_chipsets)) {
+               if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
                        tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
                        tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
                } else {