clocksource: improve sh_cmt clocksource overflow handling
[linux-2.6.git] / drivers / net / smc91x.h
index 9e0fbc5..329f890 100644 (file)
 #ifndef _SMC91X_H_
 #define _SMC91X_H_
 
+#include <linux/smc91x.h>
 
 /*
  * Define your architecture specific bus configuration parameters here.
  */
 
-#if    defined(CONFIG_ARCH_LUBBOCK)
+#if defined(CONFIG_ARCH_LUBBOCK) ||\
+    defined(CONFIG_MACH_MAINSTONE) ||\
+    defined(CONFIG_MACH_ZYLONITE) ||\
+    defined(CONFIG_MACH_LITTLETON) ||\
+    defined(CONFIG_MACH_ZYLONITE2) ||\
+    defined(CONFIG_ARCH_VIPER)
 
-/* We can only do 16-bit reads and writes in the static memory space. */
-#define SMC_CAN_USE_8BIT       0
+#include <asm/mach-types.h>
+
+/* Now the bus width is specified in the platform data
+ * pretend here to support all I/O access types
+ */
+#define SMC_CAN_USE_8BIT       1
 #define SMC_CAN_USE_16BIT      1
-#define SMC_CAN_USE_32BIT      0
+#define SMC_CAN_USE_32BIT      1
 #define SMC_NOWAIT             1
 
-/* The first two address lines aren't connected... */
-#define SMC_IO_SHIFT           2
+#define SMC_IO_SHIFT           (lp->io_shift)
+
+#define SMC_inb(a, r)          readb((a) + (r))
+#define SMC_inw(a, r)          readw((a) + (r))
+#define SMC_inl(a, r)          readl((a) + (r))
+#define SMC_outb(v, a, r)      writeb(v, (a) + (r))
+#define SMC_outl(v, a, r)      writel(v, (a) + (r))
+#define SMC_insw(a, r, p, l)   readsw((a) + (r), p, l)
+#define SMC_outsw(a, r, p, l)  writesw((a) + (r), p, l)
+#define SMC_insl(a, r, p, l)   readsl((a) + (r), p, l)
+#define SMC_outsl(a, r, p, l)  writesl((a) + (r), p, l)
+#define SMC_IRQ_FLAGS          (-1)    /* from resource */
+
+/* We actually can't write halfwords properly if not word aligned */
+static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
+{
+       if (machine_is_mainstone() && reg & 2) {
+               unsigned int v = val << 16;
+               v |= readl(ioaddr + (reg & ~2)) & 0xffff;
+               writel(v, ioaddr + (reg & ~2));
+       } else {
+               writew(val, ioaddr + reg);
+       }
+}
+
+#elif defined(CONFIG_BLACKFIN)
+
+#define SMC_IRQ_FLAGS          IRQF_TRIGGER_HIGH
+#define RPC_LSA_DEFAULT                RPC_LED_100_10
+#define RPC_LSB_DEFAULT                RPC_LED_TX_RX
+
+#define SMC_CAN_USE_8BIT       0
+#define SMC_CAN_USE_16BIT      1
+# if defined(CONFIG_BF561)
+#define SMC_CAN_USE_32BIT      1
+# else
+#define SMC_CAN_USE_32BIT      0
+# endif
+#define SMC_IO_SHIFT           0
+#define SMC_NOWAIT             1
+#define SMC_USE_BFIN_DMA       0
 
 #define SMC_inw(a, r)          readw((a) + (r))
 #define SMC_outw(v, a, r)      writew(v, (a) + (r))
 #define SMC_insw(a, r, p, l)   readsw((a) + (r), p, l)
 #define SMC_outsw(a, r, p, l)  writesw((a) + (r), p, l)
+# if SMC_CAN_USE_32BIT
+#define SMC_inl(a, r)          readl((a) + (r))
+#define SMC_outl(v, a, r)      writel(v, (a) + (r))
+#define SMC_insl(a, r, p, l)   readsl((a) + (r), p, l)
+#define SMC_outsl(a, r, p, l)  writesl((a) + (r), p, l)
+# endif
 
 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
 
 #define SMC_outw(v, a, r)      writew(v, (a) + (r))
 #define SMC_outsw(a, r, p, l)  writesw((a) + (r), p, l)
 
-#define SMC_IRQ_FLAGS          (0)
+#define SMC_IRQ_FLAGS          (-1)
 
 #elif defined(CONFIG_SA1100_ASSABET)
 
-#include <asm/arch/neponset.h>
+#include <mach/neponset.h>
 
 /* We can only do 8-bit reads and writes in the static memory space. */
 #define SMC_CAN_USE_8BIT       1
 #define SMC_outb(v, a, r)      writeb(v, (a) + (r))
 #define SMC_insb(a, r, p, l)   readsb((a) + (r), p, (l))
 #define SMC_outsb(a, r, p, l)  writesb((a) + (r), p, (l))
+#define SMC_IRQ_FLAGS          (-1)    /* from resource */
 
 #elif  defined(CONFIG_MACH_LOGICPD_PXA270)
 
 #define SMC_outsw(a, r, p, l)  writesw((a) + (r), p, l)
 
 #elif  defined(CONFIG_ARCH_INNOKOM) || \
-       defined(CONFIG_MACH_MAINSTONE) || \
        defined(CONFIG_ARCH_PXA_IDP) || \
-       defined(CONFIG_ARCH_RAMSES)
+       defined(CONFIG_ARCH_RAMSES) || \
+       defined(CONFIG_ARCH_PCM027)
 
 #define SMC_CAN_USE_8BIT       1
 #define SMC_CAN_USE_16BIT      1
 #define SMC_outl(v, a, r)      writel(v, (a) + (r))
 #define SMC_insl(a, r, p, l)   readsl((a) + (r), p, l)
 #define SMC_outsl(a, r, p, l)  writesl((a) + (r), p, l)
+#define SMC_IRQ_FLAGS          (-1)    /* from resource */
 
 /* We actually can't write halfwords properly if not word aligned */
 static inline void
@@ -188,17 +245,7 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
 #define SMC_outw(v, a, r)      writew(v, (a) + (r))
 #define SMC_insw(a, r, p, l)   readsw((a) + (r), p, l)
 #define SMC_outsw(a, r, p, l)  writesw((a) + (r), p, l)
-
-#include <asm/mach-types.h>
-#include <asm/arch/cpu.h>
-
-#define        SMC_IRQ_FLAGS (( \
-                  machine_is_omap_h2() \
-               || machine_is_omap_h3() \
-               || machine_is_omap_h4() \
-               || (machine_is_omap_innovator() && !cpu_is_omap1510()) \
-       ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING)
-
+#define        SMC_IRQ_FLAGS           (-1)    /* from resource */
 
 #elif  defined(CONFIG_SH_SH4202_MICRODEV)
 
@@ -219,26 +266,13 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
 
 #define SMC_IRQ_FLAGS          (0)
 
-#elif  defined(CONFIG_ISA)
-
-#define SMC_CAN_USE_8BIT       1
-#define SMC_CAN_USE_16BIT      1
-#define SMC_CAN_USE_32BIT      0
-
-#define SMC_inb(a, r)          inb((a) + (r))
-#define SMC_inw(a, r)          inw((a) + (r))
-#define SMC_outb(v, a, r)      outb(v, (a) + (r))
-#define SMC_outw(v, a, r)      outw(v, (a) + (r))
-#define SMC_insw(a, r, p, l)   insw((a) + (r), p, l)
-#define SMC_outsw(a, r, p, l)  outsw((a) + (r), p, l)
-
 #elif   defined(CONFIG_M32R)
 
 #define SMC_CAN_USE_8BIT       0
 #define SMC_CAN_USE_16BIT      1
 #define SMC_CAN_USE_32BIT      0
 
-#define SMC_inb(a, r)          inb((u32)a) + (r))
+#define SMC_inb(a, r)          inb(((u32)a) + (r))
 #define SMC_inw(a, r)          inw(((u32)a) + (r))
 #define SMC_outb(v, a, r)      outb(v, ((u32)a) + (r))
 #define SMC_outw(v, a, r)      outw(v, ((u32)a) + (r))
@@ -273,7 +307,7 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
  * IOBARRIER on entry to their ISR.
  */
 
-#include <asm/arch/constants.h>        /* IOBARRIER_VIRT */
+#include <mach/constants.h>    /* IOBARRIER_VIRT */
 
 #define SMC_CAN_USE_8BIT       0
 #define SMC_CAN_USE_16BIT      1
@@ -312,38 +346,6 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r,
 #define RPC_LSA_DEFAULT                RPC_LED_TX_RX
 #define RPC_LSB_DEFAULT                RPC_LED_100_10
 
-#elif defined(CONFIG_SOC_AU1X00)
-
-#include <au1xxx.h>
-
-/* We can only do 16-bit reads and writes in the static memory space. */
-#define SMC_CAN_USE_8BIT       0
-#define SMC_CAN_USE_16BIT      1
-#define SMC_CAN_USE_32BIT      0
-#define SMC_IO_SHIFT           0
-#define SMC_NOWAIT             1
-
-#define SMC_inw(a, r)          au_readw((unsigned long)((a) + (r)))
-#define SMC_insw(a, r, p, l)   \
-       do {    \
-               unsigned long _a = (unsigned long)((a) + (r)); \
-               int _l = (l); \
-               u16 *_p = (u16 *)(p); \
-               while (_l-- > 0) \
-                       *_p++ = au_readw(_a); \
-       } while(0)
-#define SMC_outw(v, a, r)      au_writew(v, (unsigned long)((a) + (r)))
-#define SMC_outsw(a, r, p, l)  \
-       do {    \
-               unsigned long _a = (unsigned long)((a) + (r)); \
-               int _l = (l); \
-               const u16 *_p = (const u16 *)(p); \
-               while (_l-- > 0) \
-                       au_writew(*_p++ , _a); \
-       } while(0)
-
-#define SMC_IRQ_FLAGS          (0)
-
 #elif  defined(CONFIG_ARCH_VERSATILE)
 
 #define SMC_CAN_USE_8BIT       1
@@ -359,103 +361,100 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r,
 #define SMC_outl(v, a, r)      writel(v, (a) + (r))
 #define SMC_insl(a, r, p, l)   readsl((a) + (r), p, l)
 #define SMC_outsl(a, r, p, l)  writesl((a) + (r), p, l)
+#define SMC_IRQ_FLAGS          (-1)    /* from resource */
 
-#define SMC_IRQ_FLAGS          (0)
-
-#elif  defined(CONFIG_ARCH_VERSATILE)
+#elif defined(CONFIG_MN10300)
 
-#define SMC_CAN_USE_8BIT       1
-#define SMC_CAN_USE_16BIT      1
-#define SMC_CAN_USE_32BIT      1
-#define SMC_NOWAIT             1
+/*
+ * MN10300/AM33 configuration
+ */
 
-#define SMC_inb(a, r)          readb((a) + (r))
-#define SMC_inw(a, r)          readw((a) + (r))
-#define SMC_inl(a, r)          readl((a) + (r))
-#define SMC_outb(v, a, r)      writeb(v, (a) + (r))
-#define SMC_outw(v, a, r)      writew(v, (a) + (r))
-#define SMC_outl(v, a, r)      writel(v, (a) + (r))
-#define SMC_insl(a, r, p, l)   readsl((a) + (r), p, l)
-#define SMC_outsl(a, r, p, l)  writesl((a) + (r), p, l)
+#include <unit/smc91111.h>
 
-#define SMC_IRQ_FLAGS          (0)
+#else
 
-#elif  defined(CONFIG_ARCH_VERSATILE)
+/*
+ * Default configuration
+ */
 
 #define SMC_CAN_USE_8BIT       1
 #define SMC_CAN_USE_16BIT      1
 #define SMC_CAN_USE_32BIT      1
 #define SMC_NOWAIT             1
 
+#define SMC_IO_SHIFT           (lp->io_shift)
+
 #define SMC_inb(a, r)          readb((a) + (r))
 #define SMC_inw(a, r)          readw((a) + (r))
 #define SMC_inl(a, r)          readl((a) + (r))
 #define SMC_outb(v, a, r)      writeb(v, (a) + (r))
 #define SMC_outw(v, a, r)      writew(v, (a) + (r))
 #define SMC_outl(v, a, r)      writel(v, (a) + (r))
+#define SMC_insw(a, r, p, l)   readsw((a) + (r), p, l)
+#define SMC_outsw(a, r, p, l)  writesw((a) + (r), p, l)
 #define SMC_insl(a, r, p, l)   readsl((a) + (r), p, l)
 #define SMC_outsl(a, r, p, l)  writesl((a) + (r), p, l)
 
-#define SMC_IRQ_FLAGS          (0)
+#define RPC_LSA_DEFAULT                RPC_LED_100_10
+#define RPC_LSB_DEFAULT                RPC_LED_TX_RX
 
-#elif  defined(CONFIG_ARCH_VERSATILE)
+#endif
 
-#define SMC_CAN_USE_8BIT       1
-#define SMC_CAN_USE_16BIT      1
-#define SMC_CAN_USE_32BIT      1
-#define SMC_NOWAIT             1
 
-#define SMC_inb(a, r)          readb((a) + (r))
-#define SMC_inw(a, r)          readw((a) + (r))
-#define SMC_inl(a, r)          readl((a) + (r))
-#define SMC_outb(v, a, r)      writeb(v, (a) + (r))
-#define SMC_outw(v, a, r)      writew(v, (a) + (r))
-#define SMC_outl(v, a, r)      writel(v, (a) + (r))
-#define SMC_insl(a, r, p, l)   readsl((a) + (r), p, l)
-#define SMC_outsl(a, r, p, l)  writesl((a) + (r), p, l)
+/* store this information for the driver.. */
+struct smc_local {
+       /*
+        * If I have to wait until memory is available to send a
+        * packet, I will store the skbuff here, until I get the
+        * desired memory.  Then, I'll send it out and free it.
+        */
+       struct sk_buff *pending_tx_skb;
+       struct tasklet_struct tx_task;
 
-#define SMC_IRQ_FLAGS          (0)
+       /* version/revision of the SMC91x chip */
+       int     version;
 
-#elif  defined(CONFIG_ARCH_VERSATILE)
+       /* Contains the current active transmission mode */
+       int     tcr_cur_mode;
 
-#define SMC_CAN_USE_8BIT       1
-#define SMC_CAN_USE_16BIT      1
-#define SMC_CAN_USE_32BIT      1
-#define SMC_NOWAIT             1
+       /* Contains the current active receive mode */
+       int     rcr_cur_mode;
 
-#define SMC_inb(a, r)          readb((a) + (r))
-#define SMC_inw(a, r)          readw((a) + (r))
-#define SMC_inl(a, r)          readl((a) + (r))
-#define SMC_outb(v, a, r)      writeb(v, (a) + (r))
-#define SMC_outw(v, a, r)      writew(v, (a) + (r))
-#define SMC_outl(v, a, r)      writel(v, (a) + (r))
-#define SMC_insl(a, r, p, l)   readsl((a) + (r), p, l)
-#define SMC_outsl(a, r, p, l)  writesl((a) + (r), p, l)
+       /* Contains the current active receive/phy mode */
+       int     rpc_cur_mode;
+       int     ctl_rfduplx;
+       int     ctl_rspeed;
 
-#define SMC_IRQ_FLAGS          (0)
+       u32     msg_enable;
+       u32     phy_type;
+       struct mii_if_info mii;
 
-#else
+       /* work queue */
+       struct work_struct phy_configure;
+       struct net_device *dev;
+       int     work_pending;
 
-#define SMC_CAN_USE_8BIT       1
-#define SMC_CAN_USE_16BIT      1
-#define SMC_CAN_USE_32BIT      1
-#define SMC_NOWAIT             1
+       spinlock_t lock;
 
-#define SMC_inb(a, r)          readb((a) + (r))
-#define SMC_inw(a, r)          readw((a) + (r))
-#define SMC_inl(a, r)          readl((a) + (r))
-#define SMC_outb(v, a, r)      writeb(v, (a) + (r))
-#define SMC_outw(v, a, r)      writew(v, (a) + (r))
-#define SMC_outl(v, a, r)      writel(v, (a) + (r))
-#define SMC_insl(a, r, p, l)   readsl((a) + (r), p, l)
-#define SMC_outsl(a, r, p, l)  writesl((a) + (r), p, l)
+#ifdef CONFIG_ARCH_PXA
+       /* DMA needs the physical address of the chip */
+       u_long physaddr;
+       struct device *device;
+#endif
+       void __iomem *base;
+       void __iomem *datacs;
 
-#define RPC_LSA_DEFAULT                RPC_LED_100_10
-#define RPC_LSB_DEFAULT                RPC_LED_TX_RX
+       /* the low address lines on some platforms aren't connected... */
+       int     io_shift;
 
-#endif
+       struct smc91x_platdata cfg;
+};
 
-#ifdef SMC_USE_PXA_DMA
+#define SMC_8BIT(p)    ((p)->cfg.flags & SMC91X_USE_8BIT)
+#define SMC_16BIT(p)   ((p)->cfg.flags & SMC91X_USE_16BIT)
+#define SMC_32BIT(p)   ((p)->cfg.flags & SMC91X_USE_32BIT)
+
+#ifdef CONFIG_ARCH_PXA
 /*
  * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
  * always happening in irq context so no need to worry about races.  TX is
@@ -463,17 +462,17 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r,
  * as RX which can overrun memory and lose packets.
  */
 #include <linux/dma-mapping.h>
-#include <asm/dma.h>
-#include <asm/arch/pxa-regs.h>
+#include <mach/dma.h>
 
 #ifdef SMC_insl
 #undef SMC_insl
 #define SMC_insl(a, r, p, l) \
-       smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)
+       smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
 static inline void
-smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
+smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
                 u_char *buf, int len)
 {
+       u_long physaddr = lp->physaddr;
        dma_addr_t dmabuf;
 
        /* fallback if no DMA available */
@@ -490,7 +489,7 @@ smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
        }
 
        len *= 4;
-       dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
+       dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
        DCSR(dma) = DCSR_NODESC;
        DTADR(dma) = dmabuf;
        DSADR(dma) = physaddr + reg;
@@ -500,18 +499,19 @@ smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
        while (!(DCSR(dma) & DCSR_STOPSTATE))
                cpu_relax();
        DCSR(dma) = 0;
-       dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
+       dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
 }
 #endif
 
 #ifdef SMC_insw
 #undef SMC_insw
 #define SMC_insw(a, r, p, l) \
-       smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)
+       smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
 static inline void
-smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
+smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
                 u_char *buf, int len)
 {
+       u_long physaddr = lp->physaddr;
        dma_addr_t dmabuf;
 
        /* fallback if no DMA available */
@@ -528,7 +528,7 @@ smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
        }
 
        len *= 2;
-       dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
+       dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
        DCSR(dma) = DCSR_NODESC;
        DTADR(dma) = dmabuf;
        DSADR(dma) = physaddr + reg;
@@ -538,7 +538,7 @@ smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
        while (!(DCSR(dma) & DCSR_STOPSTATE))
                cpu_relax();
        DCSR(dma) = 0;
-       dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
+       dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
 }
 #endif
 
@@ -547,7 +547,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
 {
        DCSR(dma) = 0;
 }
-#endif  /* SMC_USE_PXA_DMA */
+#endif  /* CONFIG_ARCH_PXA */
 
 
 /*
@@ -644,7 +644,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
 
 // Transmit Control Register
 /* BANK 0  */
-#define TCR_REG        SMC_REG(0x0000, 0)
+#define TCR_REG(lp)    SMC_REG(lp, 0x0000, 0)
 #define TCR_ENABLE     0x0001  // When 1 we can transmit
 #define TCR_LOOP       0x0002  // Controls output pin LBK
 #define TCR_FORCOL     0x0004  // When 1 will force a collision
@@ -663,7 +663,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
 
 // EPH Status Register
 /* BANK 0  */
-#define EPH_STATUS_REG SMC_REG(0x0002, 0)
+#define EPH_STATUS_REG(lp)     SMC_REG(lp, 0x0002, 0)
 #define ES_TX_SUC      0x0001  // Last TX was successful
 #define ES_SNGL_COL    0x0002  // Single collision detected for last tx
 #define ES_MUL_COL     0x0004  // Multiple collisions detected for last tx
@@ -682,7 +682,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
 
 // Receive Control Register
 /* BANK 0  */
-#define RCR_REG                SMC_REG(0x0004, 0)
+#define RCR_REG(lp)            SMC_REG(lp, 0x0004, 0)
 #define RCR_RX_ABORT   0x0001  // Set if a rx frame was aborted
 #define RCR_PRMS       0x0002  // Enable promiscuous mode
 #define RCR_ALMUL      0x0004  // When set accepts all multicast frames
@@ -699,30 +699,22 @@ smc_pxa_dma_irq(int dma, void *dummy)
 
 // Counter Register
 /* BANK 0  */
-#define COUNTER_REG    SMC_REG(0x0006, 0)
+#define COUNTER_REG(lp)        SMC_REG(lp, 0x0006, 0)
 
 
 // Memory Information Register
 /* BANK 0  */
-#define MIR_REG                SMC_REG(0x0008, 0)
+#define MIR_REG(lp)            SMC_REG(lp, 0x0008, 0)
 
 
 // Receive/Phy Control Register
 /* BANK 0  */
-#define RPC_REG                SMC_REG(0x000A, 0)
+#define RPC_REG(lp)            SMC_REG(lp, 0x000A, 0)
 #define RPC_SPEED      0x2000  // When 1 PHY is in 100Mbps mode.
 #define RPC_DPLX       0x1000  // When 1 PHY is in Full-Duplex Mode
 #define RPC_ANEG       0x0800  // When 1 PHY is in Auto-Negotiate Mode
 #define RPC_LSXA_SHFT  5       // Bits to shift LS2A,LS1A,LS0A to lsb
 #define RPC_LSXB_SHFT  2       // Bits to get LS2B,LS1B,LS0B to lsb
-#define RPC_LED_100_10 (0x00)  // LED = 100Mbps OR's with 10Mbps link detect
-#define RPC_LED_RES    (0x01)  // LED = Reserved
-#define RPC_LED_10     (0x02)  // LED = 10Mbps link detect
-#define RPC_LED_FD     (0x03)  // LED = Full Duplex Mode
-#define RPC_LED_TX_RX  (0x04)  // LED = TX or RX packet occurred
-#define RPC_LED_100    (0x05)  // LED = 100Mbps link dectect
-#define RPC_LED_TX     (0x06)  // LED = TX packet occurred
-#define RPC_LED_RX     (0x07)  // LED = RX packet occurred
 
 #ifndef RPC_LSA_DEFAULT
 #define RPC_LSA_DEFAULT        RPC_LED_100
@@ -731,7 +723,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
 #define RPC_LSB_DEFAULT RPC_LED_FD
 #endif
 
-#define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
+#define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
 
 
 /* Bank 0 0x0C is reserved */
@@ -743,7 +735,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
 
 // Configuration Reg
 /* BANK 1 */
-#define CONFIG_REG     SMC_REG(0x0000, 1)
+#define CONFIG_REG(lp) SMC_REG(lp, 0x0000,     1)
 #define CONFIG_EXT_PHY 0x0200  // 1=external MII, 0=internal Phy
 #define CONFIG_GPCNTRL 0x0400  // Inverse value drives pin nCNTRL
 #define CONFIG_NO_WAIT 0x1000  // When 1 no extra wait states on ISA bus
@@ -755,24 +747,24 @@ smc_pxa_dma_irq(int dma, void *dummy)
 
 // Base Address Register
 /* BANK 1 */
-#define BASE_REG       SMC_REG(0x0002, 1)
+#define BASE_REG(lp)   SMC_REG(lp, 0x0002, 1)
 
 
 // Individual Address Registers
 /* BANK 1 */
-#define ADDR0_REG      SMC_REG(0x0004, 1)
-#define ADDR1_REG      SMC_REG(0x0006, 1)
-#define ADDR2_REG      SMC_REG(0x0008, 1)
+#define ADDR0_REG(lp)  SMC_REG(lp, 0x0004, 1)
+#define ADDR1_REG(lp)  SMC_REG(lp, 0x0006, 1)
+#define ADDR2_REG(lp)  SMC_REG(lp, 0x0008, 1)
 
 
 // General Purpose Register
 /* BANK 1 */
-#define GP_REG         SMC_REG(0x000A, 1)
+#define GP_REG(lp)             SMC_REG(lp, 0x000A, 1)
 
 
 // Control Register
 /* BANK 1 */
-#define CTL_REG                SMC_REG(0x000C, 1)
+#define CTL_REG(lp)            SMC_REG(lp, 0x000C, 1)
 #define CTL_RCV_BAD    0x4000 // When 1 bad CRC packets are received
 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
 #define CTL_LE_ENABLE  0x0080 // When 1 enables Link Error interrupt
@@ -785,7 +777,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
 
 // MMU Command Register
 /* BANK 2 */
-#define MMU_CMD_REG    SMC_REG(0x0000, 2)
+#define MMU_CMD_REG(lp)        SMC_REG(lp, 0x0000, 2)
 #define MC_BUSY                1       // When 1 the last release has not completed
 #define MC_NOP         (0<<5)  // No Op
 #define MC_ALLOC       (1<<5)  // OR with number of 256 byte packets
@@ -799,30 +791,30 @@ smc_pxa_dma_irq(int dma, void *dummy)
 
 // Packet Number Register
 /* BANK 2 */
-#define PN_REG         SMC_REG(0x0002, 2)
+#define PN_REG(lp)             SMC_REG(lp, 0x0002, 2)
 
 
 // Allocation Result Register
 /* BANK 2 */
-#define AR_REG         SMC_REG(0x0003, 2)
+#define AR_REG(lp)             SMC_REG(lp, 0x0003, 2)
 #define AR_FAILED      0x80    // Alocation Failed
 
 
 // TX FIFO Ports Register
 /* BANK 2 */
-#define TXFIFO_REG     SMC_REG(0x0004, 2)
+#define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
 #define TXFIFO_TEMPTY  0x80    // TX FIFO Empty
 
 // RX FIFO Ports Register
 /* BANK 2 */
-#define RXFIFO_REG     SMC_REG(0x0005, 2)
+#define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
 #define RXFIFO_REMPTY  0x80    // RX FIFO Empty
 
-#define FIFO_REG       SMC_REG(0x0004, 2)
+#define FIFO_REG(lp)   SMC_REG(lp, 0x0004, 2)
 
 // Pointer Register
 /* BANK 2 */
-#define PTR_REG                SMC_REG(0x0006, 2)
+#define PTR_REG(lp)            SMC_REG(lp, 0x0006, 2)
 #define PTR_RCV                0x8000 // 1=Receive area, 0=Transmit area
 #define PTR_AUTOINC    0x4000 // Auto increment the pointer on each access
 #define PTR_READ       0x2000 // When 1 the operation is a read
@@ -830,17 +822,17 @@ smc_pxa_dma_irq(int dma, void *dummy)
 
 // Data Register
 /* BANK 2 */
-#define DATA_REG       SMC_REG(0x0008, 2)
+#define DATA_REG(lp)   SMC_REG(lp, 0x0008, 2)
 
 
 // Interrupt Status/Acknowledge Register
 /* BANK 2 */
-#define INT_REG                SMC_REG(0x000C, 2)
+#define INT_REG(lp)            SMC_REG(lp, 0x000C, 2)
 
 
 // Interrupt Mask Register
 /* BANK 2 */
-#define IM_REG         SMC_REG(0x000D, 2)
+#define IM_REG(lp)             SMC_REG(lp, 0x000D, 2)
 #define IM_MDINT       0x80 // PHY MI Register 18 Interrupt
 #define IM_ERCV_INT    0x40 // Early Receive Interrupt
 #define IM_EPH_INT     0x20 // Set by Ethernet Protocol Handler section
@@ -853,15 +845,15 @@ smc_pxa_dma_irq(int dma, void *dummy)
 
 // Multicast Table Registers
 /* BANK 3 */
-#define MCAST_REG1     SMC_REG(0x0000, 3)
-#define MCAST_REG2     SMC_REG(0x0002, 3)
-#define MCAST_REG3     SMC_REG(0x0004, 3)
-#define MCAST_REG4     SMC_REG(0x0006, 3)
+#define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
+#define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
+#define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
+#define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
 
 
 // Management Interface Register (MII)
 /* BANK 3 */
-#define MII_REG                SMC_REG(0x0008, 3)
+#define MII_REG(lp)            SMC_REG(lp, 0x0008, 3)
 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
 #define MII_MDOE       0x0008 // MII Output Enable
 #define MII_MCLK       0x0004 // MII Clock, pin MDCLK
@@ -872,20 +864,20 @@ smc_pxa_dma_irq(int dma, void *dummy)
 // Revision Register
 /* BANK 3 */
 /* ( hi: chip id   low: rev # ) */
-#define REV_REG                SMC_REG(0x000A, 3)
+#define REV_REG(lp)            SMC_REG(lp, 0x000A, 3)
 
 
 // Early RCV Register
 /* BANK 3 */
 /* this is NOT on SMC9192 */
-#define ERCV_REG       SMC_REG(0x000C, 3)
+#define ERCV_REG(lp)   SMC_REG(lp, 0x000C, 3)
 #define ERCV_RCV_DISCRD        0x0080 // When 1 discards a packet being received
 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
 
 
 // External Register
 /* BANK 7 */
-#define EXT_REG                SMC_REG(0x0000, 7)
+#define EXT_REG(lp)            SMC_REG(lp, 0x0000, 7)
 
 
 #define CHIP_9192      3
@@ -1009,9 +1001,9 @@ static const char * chip_ids[ 16 ] =  {
  */
 
 #if SMC_DEBUG > 0
-#define SMC_REG(reg, bank)                                             \
+#define SMC_REG(lp, reg, bank)                                 \
        ({                                                              \
-               int __b = SMC_CURRENT_BANK();                           \
+               int __b = SMC_CURRENT_BANK(lp);                 \
                if (unlikely((__b & ~0xf0) != (0x3300 | bank))) {       \
                        printk( "%s: bank reg screwed (0x%04x)\n",      \
                                CARDNAME, __b );                        \
@@ -1020,7 +1012,7 @@ static const char * chip_ids[ 16 ] =  {
                reg<<SMC_IO_SHIFT;                                      \
        })
 #else
-#define SMC_REG(reg, bank)     (reg<<SMC_IO_SHIFT)
+#define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
 #endif
 
 /*
@@ -1032,212 +1024,225 @@ static const char * chip_ids[ 16 ] =  {
  *
  * Enforce it on any 32-bit capable setup for now.
  */
-#define SMC_MUST_ALIGN_WRITE   SMC_CAN_USE_32BIT
+#define SMC_MUST_ALIGN_WRITE(lp)       SMC_32BIT(lp)
 
-#define SMC_GET_PN()                                                   \
-       ( SMC_CAN_USE_8BIT      ? (SMC_inb(ioaddr, PN_REG))             \
-                               : (SMC_inw(ioaddr, PN_REG) & 0xFF) )
+#define SMC_GET_PN(lp)                                         \
+       (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, PN_REG(lp))) \
+                               : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
 
-#define SMC_SET_PN(x)                                                  \
+#define SMC_SET_PN(lp, x)                                              \
        do {                                                            \
-               if (SMC_MUST_ALIGN_WRITE)                               \
-                       SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2));       \
-               else if (SMC_CAN_USE_8BIT)                              \
-                       SMC_outb(x, ioaddr, PN_REG);                    \
+               if (SMC_MUST_ALIGN_WRITE(lp))                           \
+                       SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2));   \
+               else if (SMC_8BIT(lp))                          \
+                       SMC_outb(x, ioaddr, PN_REG(lp));                \
                else                                                    \
-                       SMC_outw(x, ioaddr, PN_REG);                    \
+                       SMC_outw(x, ioaddr, PN_REG(lp));                \
        } while (0)
 
-#define SMC_GET_AR()                                                   \
-       ( SMC_CAN_USE_8BIT      ? (SMC_inb(ioaddr, AR_REG))             \
-                               : (SMC_inw(ioaddr, PN_REG) >> 8) )
+#define SMC_GET_AR(lp)                                         \
+       (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, AR_REG(lp))) \
+                               : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
 
-#define SMC_GET_TXFIFO()                                               \
-       ( SMC_CAN_USE_8BIT      ? (SMC_inb(ioaddr, TXFIFO_REG))         \
-                               : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) )
+#define SMC_GET_TXFIFO(lp)                                             \
+       (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, TXFIFO_REG(lp)))     \
+                               : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
 
-#define SMC_GET_RXFIFO()                                               \
-         ( SMC_CAN_USE_8BIT    ? (SMC_inb(ioaddr, RXFIFO_REG))         \
-                               : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) )
+#define SMC_GET_RXFIFO(lp)                                             \
+       (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, RXFIFO_REG(lp)))     \
+                               : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
 
-#define SMC_GET_INT()                                                  \
-       ( SMC_CAN_USE_8BIT      ? (SMC_inb(ioaddr, INT_REG))            \
-                               : (SMC_inw(ioaddr, INT_REG) & 0xFF) )
+#define SMC_GET_INT(lp)                                                \
+       (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, INT_REG(lp)))        \
+                               : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
 
-#define SMC_ACK_INT(x)                                                 \
+#define SMC_ACK_INT(lp, x)                                             \
        do {                                                            \
-               if (SMC_CAN_USE_8BIT)                                   \
-                       SMC_outb(x, ioaddr, INT_REG);                   \
+               if (SMC_8BIT(lp))                                       \
+                       SMC_outb(x, ioaddr, INT_REG(lp));               \
                else {                                                  \
                        unsigned long __flags;                          \
                        int __mask;                                     \
                        local_irq_save(__flags);                        \
-                       __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff;    \
-                       SMC_outw( __mask | (x), ioaddr, INT_REG );      \
+                       __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
+                       SMC_outw(__mask | (x), ioaddr, INT_REG(lp));    \
                        local_irq_restore(__flags);                     \
                }                                                       \
        } while (0)
 
-#define SMC_GET_INT_MASK()                                             \
-       ( SMC_CAN_USE_8BIT      ? (SMC_inb(ioaddr, IM_REG))             \
-                               : (SMC_inw( ioaddr, INT_REG ) >> 8) )
+#define SMC_GET_INT_MASK(lp)                                           \
+       (SMC_8BIT(lp)   ? (SMC_inb(ioaddr, IM_REG(lp))) \
+                               : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
 
-#define SMC_SET_INT_MASK(x)                                            \
+#define SMC_SET_INT_MASK(lp, x)                                        \
        do {                                                            \
-               if (SMC_CAN_USE_8BIT)                                   \
-                       SMC_outb(x, ioaddr, IM_REG);                    \
+               if (SMC_8BIT(lp))                                       \
+                       SMC_outb(x, ioaddr, IM_REG(lp));                \
                else                                                    \
-                       SMC_outw((x) << 8, ioaddr, INT_REG);            \
+                       SMC_outw((x) << 8, ioaddr, INT_REG(lp));        \
        } while (0)
 
-#define SMC_CURRENT_BANK()     SMC_inw(ioaddr, BANK_SELECT)
+#define SMC_CURRENT_BANK(lp)   SMC_inw(ioaddr, BANK_SELECT)
 
-#define SMC_SELECT_BANK(x)                                             \
+#define SMC_SELECT_BANK(lp, x)                                 \
        do {                                                            \
-               if (SMC_MUST_ALIGN_WRITE)                               \
+               if (SMC_MUST_ALIGN_WRITE(lp))                           \
                        SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT);    \
                else                                                    \
                        SMC_outw(x, ioaddr, BANK_SELECT);               \
        } while (0)
 
-#define SMC_GET_BASE()         SMC_inw(ioaddr, BASE_REG)
+#define SMC_GET_BASE(lp)               SMC_inw(ioaddr, BASE_REG(lp))
+
+#define SMC_SET_BASE(lp, x)            SMC_outw(x, ioaddr, BASE_REG(lp))
 
-#define SMC_SET_BASE(x)                SMC_outw(x, ioaddr, BASE_REG)
+#define SMC_GET_CONFIG(lp)     SMC_inw(ioaddr, CONFIG_REG(lp))
 
-#define SMC_GET_CONFIG()       SMC_inw(ioaddr, CONFIG_REG)
+#define SMC_SET_CONFIG(lp, x)  SMC_outw(x, ioaddr, CONFIG_REG(lp))
 
-#define SMC_SET_CONFIG(x)      SMC_outw(x, ioaddr, CONFIG_REG)
+#define SMC_GET_COUNTER(lp)    SMC_inw(ioaddr, COUNTER_REG(lp))
 
-#define SMC_GET_COUNTER()      SMC_inw(ioaddr, COUNTER_REG)
+#define SMC_GET_CTL(lp)                SMC_inw(ioaddr, CTL_REG(lp))
 
-#define SMC_GET_CTL()          SMC_inw(ioaddr, CTL_REG)
+#define SMC_SET_CTL(lp, x)             SMC_outw(x, ioaddr, CTL_REG(lp))
 
-#define SMC_SET_CTL(x)         SMC_outw(x, ioaddr, CTL_REG)
+#define SMC_GET_MII(lp)                SMC_inw(ioaddr, MII_REG(lp))
 
-#define SMC_GET_MII()          SMC_inw(ioaddr, MII_REG)
+#define SMC_GET_GP(lp)         SMC_inw(ioaddr, GP_REG(lp))
+
+#define SMC_SET_GP(lp, x)                                              \
+       do {                                                            \
+               if (SMC_MUST_ALIGN_WRITE(lp))                           \
+                       SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1));   \
+               else                                                    \
+                       SMC_outw(x, ioaddr, GP_REG(lp));                \
+       } while (0)
 
-#define SMC_SET_MII(x)         SMC_outw(x, ioaddr, MII_REG)
+#define SMC_SET_MII(lp, x)             SMC_outw(x, ioaddr, MII_REG(lp))
 
-#define SMC_GET_MIR()          SMC_inw(ioaddr, MIR_REG)
+#define SMC_GET_MIR(lp)                SMC_inw(ioaddr, MIR_REG(lp))
 
-#define SMC_SET_MIR(x)         SMC_outw(x, ioaddr, MIR_REG)
+#define SMC_SET_MIR(lp, x)             SMC_outw(x, ioaddr, MIR_REG(lp))
 
-#define SMC_GET_MMU_CMD()      SMC_inw(ioaddr, MMU_CMD_REG)
+#define SMC_GET_MMU_CMD(lp)    SMC_inw(ioaddr, MMU_CMD_REG(lp))
 
-#define SMC_SET_MMU_CMD(x)     SMC_outw(x, ioaddr, MMU_CMD_REG)
+#define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
 
-#define SMC_GET_FIFO()         SMC_inw(ioaddr, FIFO_REG)
+#define SMC_GET_FIFO(lp)               SMC_inw(ioaddr, FIFO_REG(lp))
 
-#define SMC_GET_PTR()          SMC_inw(ioaddr, PTR_REG)
+#define SMC_GET_PTR(lp)                SMC_inw(ioaddr, PTR_REG(lp))
 
-#define SMC_SET_PTR(x)                                                 \
+#define SMC_SET_PTR(lp, x)                                             \
        do {                                                            \
-               if (SMC_MUST_ALIGN_WRITE)                               \
-                       SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2));       \
+               if (SMC_MUST_ALIGN_WRITE(lp))                           \
+                       SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2));   \
                else                                                    \
-                       SMC_outw(x, ioaddr, PTR_REG);                   \
+                       SMC_outw(x, ioaddr, PTR_REG(lp));               \
        } while (0)
 
-#define SMC_GET_EPH_STATUS()   SMC_inw(ioaddr, EPH_STATUS_REG)
+#define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
 
-#define SMC_GET_RCR()          SMC_inw(ioaddr, RCR_REG)
+#define SMC_GET_RCR(lp)                SMC_inw(ioaddr, RCR_REG(lp))
 
-#define SMC_SET_RCR(x)         SMC_outw(x, ioaddr, RCR_REG)
+#define SMC_SET_RCR(lp, x)             SMC_outw(x, ioaddr, RCR_REG(lp))
 
-#define SMC_GET_REV()          SMC_inw(ioaddr, REV_REG)
+#define SMC_GET_REV(lp)                SMC_inw(ioaddr, REV_REG(lp))
 
-#define SMC_GET_RPC()          SMC_inw(ioaddr, RPC_REG)
+#define SMC_GET_RPC(lp)                SMC_inw(ioaddr, RPC_REG(lp))
 
-#define SMC_SET_RPC(x)                                                 \
+#define SMC_SET_RPC(lp, x)                                             \
        do {                                                            \
-               if (SMC_MUST_ALIGN_WRITE)                               \
-                       SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0));       \
+               if (SMC_MUST_ALIGN_WRITE(lp))                           \
+                       SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0));   \
                else                                                    \
-                       SMC_outw(x, ioaddr, RPC_REG);                   \
+                       SMC_outw(x, ioaddr, RPC_REG(lp));               \
        } while (0)
 
-#define SMC_GET_TCR()          SMC_inw(ioaddr, TCR_REG)
+#define SMC_GET_TCR(lp)                SMC_inw(ioaddr, TCR_REG(lp))
 
-#define SMC_SET_TCR(x)         SMC_outw(x, ioaddr, TCR_REG)
+#define SMC_SET_TCR(lp, x)             SMC_outw(x, ioaddr, TCR_REG(lp))
 
 #ifndef SMC_GET_MAC_ADDR
-#define SMC_GET_MAC_ADDR(addr)                                         \
+#define SMC_GET_MAC_ADDR(lp, addr)                                     \
        do {                                                            \
                unsigned int __v;                                       \
-               __v = SMC_inw( ioaddr, ADDR0_REG );                     \
+               __v = SMC_inw(ioaddr, ADDR0_REG(lp));                   \
                addr[0] = __v; addr[1] = __v >> 8;                      \
-               __v = SMC_inw( ioaddr, ADDR1_REG );                     \
+               __v = SMC_inw(ioaddr, ADDR1_REG(lp));                   \
                addr[2] = __v; addr[3] = __v >> 8;                      \
-               __v = SMC_inw( ioaddr, ADDR2_REG );                     \
+               __v = SMC_inw(ioaddr, ADDR2_REG(lp));                   \
                addr[4] = __v; addr[5] = __v >> 8;                      \
        } while (0)
 #endif
 
-#define SMC_SET_MAC_ADDR(addr)                                         \
+#define SMC_SET_MAC_ADDR(lp, addr)                                     \
        do {                                                            \
-               SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG );  \
-               SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG );  \
-               SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG );  \
+               SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
+               SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
+               SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
        } while (0)
 
-#define SMC_SET_MCAST(x)                                               \
+#define SMC_SET_MCAST(lp, x)                                           \
        do {                                                            \
                const unsigned char *mt = (x);                          \
-               SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 );   \
-               SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 );   \
-               SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 );   \
-               SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 );   \
+               SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
+               SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
+               SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
+               SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
        } while (0)
 
-#define SMC_PUT_PKT_HDR(status, length)                                        \
+#define SMC_PUT_PKT_HDR(lp, status, length)                            \
        do {                                                            \
-               if (SMC_CAN_USE_32BIT)                                  \
-                       SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \
+               if (SMC_32BIT(lp))                                      \
+                       SMC_outl((status) | (length)<<16, ioaddr,       \
+                                DATA_REG(lp));                 \
                else {                                                  \
-                       SMC_outw(status, ioaddr, DATA_REG);             \
-                       SMC_outw(length, ioaddr, DATA_REG);             \
+                       SMC_outw(status, ioaddr, DATA_REG(lp)); \
+                       SMC_outw(length, ioaddr, DATA_REG(lp)); \
                }                                                       \
        } while (0)
 
-#define SMC_GET_PKT_HDR(status, length)                                        \
+#define SMC_GET_PKT_HDR(lp, status, length)                            \
        do {                                                            \
-               if (SMC_CAN_USE_32BIT) {                                \
-                       unsigned int __val = SMC_inl(ioaddr, DATA_REG); \
+               if (SMC_32BIT(lp)) {                            \
+                       unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
                        (status) = __val & 0xffff;                      \
                        (length) = __val >> 16;                         \
                } else {                                                \
-                       (status) = SMC_inw(ioaddr, DATA_REG);           \
-                       (length) = SMC_inw(ioaddr, DATA_REG);           \
+                       (status) = SMC_inw(ioaddr, DATA_REG(lp));       \
+                       (length) = SMC_inw(ioaddr, DATA_REG(lp));       \
                }                                                       \
        } while (0)
 
-#define SMC_PUSH_DATA(p, l)                                            \
+#define SMC_PUSH_DATA(lp, p, l)                                        \
        do {                                                            \
-               if (SMC_CAN_USE_32BIT) {                                \
+               if (SMC_32BIT(lp)) {                            \
                        void *__ptr = (p);                              \
                        int __len = (l);                                \
                        void __iomem *__ioaddr = ioaddr;                \
                        if (__len >= 2 && (unsigned long)__ptr & 2) {   \
                                __len -= 2;                             \
-                               SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
+                               SMC_outw(*(u16 *)__ptr, ioaddr,         \
+                                       DATA_REG(lp));          \
                                __ptr += 2;                             \
                        }                                               \
                        if (SMC_CAN_USE_DATACS && lp->datacs)           \
                                __ioaddr = lp->datacs;                  \
-                       SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \
+                       SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
                        if (__len & 2) {                                \
                                __ptr += (__len & ~3);                  \
-                               SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \
+                               SMC_outw(*((u16 *)__ptr), ioaddr,       \
+                                        DATA_REG(lp));         \
                        }                                               \
-               } else if (SMC_CAN_USE_16BIT)                           \
-                       SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1);       \
-               else if (SMC_CAN_USE_8BIT)                              \
-                       SMC_outsb(ioaddr, DATA_REG, p, l);              \
+               } else if (SMC_16BIT(lp))                               \
+                       SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1);   \
+               else if (SMC_8BIT(lp))                          \
+                       SMC_outsb(ioaddr, DATA_REG(lp), p, l);  \
        } while (0)
 
-#define SMC_PULL_DATA(p, l)                                            \
+#define SMC_PULL_DATA(lp, p, l)                                        \
        do {                                                            \
-               if (SMC_CAN_USE_32BIT) {                                \
+               if (SMC_32BIT(lp)) {                            \
                        void *__ptr = (p);                              \
                        int __len = (l);                                \
                        void __iomem *__ioaddr = ioaddr;                \
@@ -1257,16 +1262,17 @@ static const char * chip_ids[ 16 ] =  {
                                 */                                     \
                                __ptr -= 2;                             \
                                __len += 2;                             \
-                               SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
+                               SMC_SET_PTR(lp,                 \
+                                       2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
                        }                                               \
                        if (SMC_CAN_USE_DATACS && lp->datacs)           \
                                __ioaddr = lp->datacs;                  \
                        __len += 2;                                     \
-                       SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2);  \
-               } else if (SMC_CAN_USE_16BIT)                           \
-                       SMC_insw(ioaddr, DATA_REG, p, (l) >> 1);        \
-               else if (SMC_CAN_USE_8BIT)                              \
-                       SMC_insb(ioaddr, DATA_REG, p, l);               \
+                       SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
+               } else if (SMC_16BIT(lp))                               \
+                       SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1);    \
+               else if (SMC_8BIT(lp))                          \
+                       SMC_insb(ioaddr, DATA_REG(lp), p, l);           \
        } while (0)
 
 #endif  /* _SMC91X_H_ */