Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6.git] / drivers / net / bnx2x / bnx2x_main.c
index 3696a4b..5b4a8f3 100644 (file)
@@ -1,6 +1,6 @@
 /* bnx2x_main.c: Broadcom Everest network driver.
  *
- * Copyright (c) 2007-2010 Broadcom Corporation
+ * Copyright (c) 2007-2011 Broadcom Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -23,7 +23,6 @@
 #include <linux/errno.h>
 #include <linux/ioport.h>
 #include <linux/slab.h>
-#include <linux/vmalloc.h>
 #include <linux/interrupt.h>
 #include <linux/pci.h>
 #include <linux/init.h>
@@ -40,6 +39,7 @@
 #include <linux/mii.h>
 #include <linux/if_vlan.h>
 #include <net/ip.h>
+#include <net/ipv6.h>
 #include <net/tcp.h>
 #include <net/checksum.h>
 #include <net/ip6_checksum.h>
 #include <linux/zlib.h>
 #include <linux/io.h>
 #include <linux/stringify.h>
+#include <linux/vmalloc.h>
 
-#define BNX2X_MAIN
 #include "bnx2x.h"
 #include "bnx2x_init.h"
 #include "bnx2x_init_ops.h"
 #include "bnx2x_cmn.h"
-
+#include "bnx2x_dcb.h"
+#include "bnx2x_sp.h"
 
 #include <linux/firmware.h>
 #include "bnx2x_fw_file_hdr.h"
        __stringify(BCM_5710_FW_ENGINEERING_VERSION)
 #define FW_FILE_NAME_E1                "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
 #define FW_FILE_NAME_E1H       "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
+#define FW_FILE_NAME_E2                "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
 
 /* Time in jiffies before concluding the transmitter is hung */
 #define TX_TIMEOUT             (5*HZ)
 
 static char version[] __devinitdata =
-       "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
+       "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
        DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 
 MODULE_AUTHOR("Eliezer Tamir");
-MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710/57711/57711E Driver");
+MODULE_DESCRIPTION("Broadcom NetXtreme II "
+                  "BCM57710/57711/57711E/"
+                  "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
+                  "57840/57840_MF Driver");
 MODULE_LICENSE("GPL");
 MODULE_VERSION(DRV_MODULE_VERSION);
 MODULE_FIRMWARE(FW_FILE_NAME_E1);
 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
+MODULE_FIRMWARE(FW_FILE_NAME_E2);
 
 static int multi_mode = 1;
 module_param(multi_mode, int, 0);
 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
                             "(0 Disable; 1 Enable (default))");
 
-static int num_queues;
+int num_queues;
 module_param(num_queues, int, 0);
 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
                                " (default is as a number of CPUs)");
@@ -97,9 +103,11 @@ static int disable_tpa;
 module_param(disable_tpa, int, 0);
 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 
+#define INT_MODE_INTx                  1
+#define INT_MODE_MSI                   2
 static int int_mode;
 module_param(int_mode, int, 0);
-MODULE_PARM_DESC(int_mode, " Force interrupt mode other then MSI-X "
+MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
                                "(1 INT#x; 2 MSI)");
 
 static int dropless_fc;
@@ -118,28 +126,87 @@ static int debug;
 module_param(debug, int, 0);
 MODULE_PARM_DESC(debug, " Default debug msglevel");
 
-static struct workqueue_struct *bnx2x_wq;
+
+
+struct workqueue_struct *bnx2x_wq;
 
 enum bnx2x_board_type {
        BCM57710 = 0,
-       BCM57711 = 1,
-       BCM57711E = 2,
+       BCM57711,
+       BCM57711E,
+       BCM57712,
+       BCM57712_MF,
+       BCM57800,
+       BCM57800_MF,
+       BCM57810,
+       BCM57810_MF,
+       BCM57840,
+       BCM57840_MF
 };
 
 /* indexed by board_type, above */
 static struct {
        char *name;
 } board_info[] __devinitdata = {
-       { "Broadcom NetXtreme II BCM57710 XGb" },
-       { "Broadcom NetXtreme II BCM57711 XGb" },
-       { "Broadcom NetXtreme II BCM57711E XGb" }
+       { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
+       { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
+       { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
+       { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
+       { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
+       { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
+       { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
+       { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
+       { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
+       { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
+       { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
+                                               "Ethernet Multi Function"}
 };
 
-
+#ifndef PCI_DEVICE_ID_NX2_57710
+#define PCI_DEVICE_ID_NX2_57710                CHIP_NUM_57710
+#endif
+#ifndef PCI_DEVICE_ID_NX2_57711
+#define PCI_DEVICE_ID_NX2_57711                CHIP_NUM_57711
+#endif
+#ifndef PCI_DEVICE_ID_NX2_57711E
+#define PCI_DEVICE_ID_NX2_57711E       CHIP_NUM_57711E
+#endif
+#ifndef PCI_DEVICE_ID_NX2_57712
+#define PCI_DEVICE_ID_NX2_57712                CHIP_NUM_57712
+#endif
+#ifndef PCI_DEVICE_ID_NX2_57712_MF
+#define PCI_DEVICE_ID_NX2_57712_MF     CHIP_NUM_57712_MF
+#endif
+#ifndef PCI_DEVICE_ID_NX2_57800
+#define PCI_DEVICE_ID_NX2_57800                CHIP_NUM_57800
+#endif
+#ifndef PCI_DEVICE_ID_NX2_57800_MF
+#define PCI_DEVICE_ID_NX2_57800_MF     CHIP_NUM_57800_MF
+#endif
+#ifndef PCI_DEVICE_ID_NX2_57810
+#define PCI_DEVICE_ID_NX2_57810                CHIP_NUM_57810
+#endif
+#ifndef PCI_DEVICE_ID_NX2_57810_MF
+#define PCI_DEVICE_ID_NX2_57810_MF     CHIP_NUM_57810_MF
+#endif
+#ifndef PCI_DEVICE_ID_NX2_57840
+#define PCI_DEVICE_ID_NX2_57840                CHIP_NUM_57840
+#endif
+#ifndef PCI_DEVICE_ID_NX2_57840_MF
+#define PCI_DEVICE_ID_NX2_57840_MF     CHIP_NUM_57840_MF
+#endif
 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
        { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
        { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
        { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
+       { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
+       { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
+       { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
+       { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
+       { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
+       { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
+       { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
+       { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
        { 0 }
 };
 
@@ -149,10 +216,70 @@ MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 * General service functions
 ****************************************************************************/
 
+static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
+                                      u32 addr, dma_addr_t mapping)
+{
+       REG_WR(bp,  addr, U64_LO(mapping));
+       REG_WR(bp,  addr + 4, U64_HI(mapping));
+}
+
+static inline void storm_memset_spq_addr(struct bnx2x *bp,
+                                        dma_addr_t mapping, u16 abs_fid)
+{
+       u32 addr = XSEM_REG_FAST_MEMORY +
+                       XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
+
+       __storm_memset_dma_mapping(bp, addr, mapping);
+}
+
+static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
+                                        u16 pf_id)
+{
+       REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
+               pf_id);
+       REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
+               pf_id);
+       REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
+               pf_id);
+       REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
+               pf_id);
+}
+
+static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
+                                       u8 enable)
+{
+       REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
+               enable);
+       REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
+               enable);
+       REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
+               enable);
+       REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
+               enable);
+}
+
+static inline void storm_memset_eq_data(struct bnx2x *bp,
+                               struct event_ring_data *eq_data,
+                               u16 pfid)
+{
+       size_t size = sizeof(struct event_ring_data);
+
+       u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
+
+       __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
+}
+
+static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
+                                       u16 pfid)
+{
+       u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
+       REG_WR16(bp, addr, eq_prod);
+}
+
 /* used only at init
  * locking is done by mcp
  */
-void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
+static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 {
        pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
        pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
@@ -172,12 +299,75 @@ static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
        return val;
 }
 
-const u32 dmae_reg_go_c[] = {
-       DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
-       DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
-       DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
-       DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
-};
+#define DMAE_DP_SRC_GRC                "grc src_addr [%08x]"
+#define DMAE_DP_SRC_PCI                "pci src_addr [%x:%08x]"
+#define DMAE_DP_DST_GRC                "grc dst_addr [%08x]"
+#define DMAE_DP_DST_PCI                "pci dst_addr [%x:%08x]"
+#define DMAE_DP_DST_NONE       "dst_addr [none]"
+
+static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
+                         int msglvl)
+{
+       u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
+
+       switch (dmae->opcode & DMAE_COMMAND_DST) {
+       case DMAE_CMD_DST_PCI:
+               if (src_type == DMAE_CMD_SRC_PCI)
+                       DP(msglvl, "DMAE: opcode 0x%08x\n"
+                          "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
+                          "comp_addr [%x:%08x], comp_val 0x%08x\n",
+                          dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
+                          dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
+                          dmae->comp_addr_hi, dmae->comp_addr_lo,
+                          dmae->comp_val);
+               else
+                       DP(msglvl, "DMAE: opcode 0x%08x\n"
+                          "src [%08x], len [%d*4], dst [%x:%08x]\n"
+                          "comp_addr [%x:%08x], comp_val 0x%08x\n",
+                          dmae->opcode, dmae->src_addr_lo >> 2,
+                          dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
+                          dmae->comp_addr_hi, dmae->comp_addr_lo,
+                          dmae->comp_val);
+               break;
+       case DMAE_CMD_DST_GRC:
+               if (src_type == DMAE_CMD_SRC_PCI)
+                       DP(msglvl, "DMAE: opcode 0x%08x\n"
+                          "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
+                          "comp_addr [%x:%08x], comp_val 0x%08x\n",
+                          dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
+                          dmae->len, dmae->dst_addr_lo >> 2,
+                          dmae->comp_addr_hi, dmae->comp_addr_lo,
+                          dmae->comp_val);
+               else
+                       DP(msglvl, "DMAE: opcode 0x%08x\n"
+                          "src [%08x], len [%d*4], dst [%08x]\n"
+                          "comp_addr [%x:%08x], comp_val 0x%08x\n",
+                          dmae->opcode, dmae->src_addr_lo >> 2,
+                          dmae->len, dmae->dst_addr_lo >> 2,
+                          dmae->comp_addr_hi, dmae->comp_addr_lo,
+                          dmae->comp_val);
+               break;
+       default:
+               if (src_type == DMAE_CMD_SRC_PCI)
+                       DP(msglvl, "DMAE: opcode 0x%08x\n"
+                          DP_LEVEL "src_addr [%x:%08x]  len [%d * 4]  "
+                                   "dst_addr [none]\n"
+                          DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
+                          dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
+                          dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
+                          dmae->comp_val);
+               else
+                       DP(msglvl, "DMAE: opcode 0x%08x\n"
+                          DP_LEVEL "src_addr [%08x]  len [%d * 4]  "
+                                   "dst_addr [none]\n"
+                          DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
+                          dmae->opcode, dmae->src_addr_lo >> 2,
+                          dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
+                          dmae->comp_val);
+               break;
+       }
+
+}
 
 /* copy command into DMAE command memory and set DMAE command go */
 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
@@ -195,85 +385,143 @@ void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
        REG_WR(bp, dmae_reg_go_c[idx], 1);
 }
 
-void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
-                     u32 len32)
+u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 {
-       struct dmae_command dmae;
-       u32 *wb_comp = bnx2x_sp(bp, wb_comp);
-       int cnt = 200;
+       return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
+                          DMAE_CMD_C_ENABLE);
+}
 
-       if (!bp->dmae_ready) {
-               u32 *data = bnx2x_sp(bp, wb_data[0]);
+u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
+{
+       return opcode & ~DMAE_CMD_SRC_RESET;
+}
 
-               DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x  len32 %d)"
-                  "  using indirect\n", dst_addr, len32);
-               bnx2x_init_ind_wr(bp, dst_addr, data, len32);
-               return;
-       }
+u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
+                            bool with_comp, u8 comp_type)
+{
+       u32 opcode = 0;
+
+       opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
+                  (dst_type << DMAE_COMMAND_DST_SHIFT));
+
+       opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 
-       memset(&dmae, 0, sizeof(struct dmae_command));
+       opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
+       opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
+                  (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
+       opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 
-       dmae.opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
-                      DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
-                      DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
 #ifdef __BIG_ENDIAN
-                      DMAE_CMD_ENDIANITY_B_DW_SWAP |
+       opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 #else
-                      DMAE_CMD_ENDIANITY_DW_SWAP |
+       opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 #endif
-                      (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
-                      (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
-       dmae.src_addr_lo = U64_LO(dma_addr);
-       dmae.src_addr_hi = U64_HI(dma_addr);
-       dmae.dst_addr_lo = dst_addr >> 2;
-       dmae.dst_addr_hi = 0;
-       dmae.len = len32;
-       dmae.comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
-       dmae.comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
-       dmae.comp_val = DMAE_COMP_VAL;
-
-       DP(BNX2X_MSG_OFF, "DMAE: opcode 0x%08x\n"
-          DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
-                   "dst_addr [%x:%08x (%08x)]\n"
-          DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
-          dmae.opcode, dmae.src_addr_hi, dmae.src_addr_lo,
-          dmae.len, dmae.dst_addr_hi, dmae.dst_addr_lo, dst_addr,
-          dmae.comp_addr_hi, dmae.comp_addr_lo, dmae.comp_val);
-       DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
+       if (with_comp)
+               opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
+       return opcode;
+}
+
+static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
+                                     struct dmae_command *dmae,
+                                     u8 src_type, u8 dst_type)
+{
+       memset(dmae, 0, sizeof(struct dmae_command));
+
+       /* set the opcode */
+       dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
+                                        true, DMAE_COMP_PCI);
+
+       /* fill in the completion parameters */
+       dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
+       dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
+       dmae->comp_val = DMAE_COMP_VAL;
+}
+
+/* issue a dmae command over the init-channel and wailt for completion */
+static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
+                                     struct dmae_command *dmae)
+{
+       u32 *wb_comp = bnx2x_sp(bp, wb_comp);
+       int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
+       int rc = 0;
+
+       DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
           bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
           bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
 
-       mutex_lock(&bp->dmae_mutex);
+       /*
+        * Lock the dmae channel. Disable BHs to prevent a dead-lock
+        * as long as this code is called both from syscall context and
+        * from ndo_set_rx_mode() flow that may be called from BH.
+        */
+       spin_lock_bh(&bp->dmae_lock);
 
+       /* reset completion */
        *wb_comp = 0;
 
-       bnx2x_post_dmae(bp, &dmae, INIT_DMAE_C(bp));
+       /* post the command on the channel used for initializations */
+       bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 
+       /* wait for completion */
        udelay(5);
-
-       while (*wb_comp != DMAE_COMP_VAL) {
+       while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
                DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
 
                if (!cnt) {
                        BNX2X_ERR("DMAE timeout!\n");
-                       break;
+                       rc = DMAE_TIMEOUT;
+                       goto unlock;
                }
                cnt--;
-               /* adjust delay for emulation/FPGA */
-               if (CHIP_REV_IS_SLOW(bp))
-                       msleep(100);
-               else
-                       udelay(5);
+               udelay(50);
        }
+       if (*wb_comp & DMAE_PCI_ERR_FLAG) {
+               BNX2X_ERR("DMAE PCI error!\n");
+               rc = DMAE_PCI_ERROR;
+       }
+
+       DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
+          bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
+          bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
 
-       mutex_unlock(&bp->dmae_mutex);
+unlock:
+       spin_unlock_bh(&bp->dmae_lock);
+       return rc;
+}
+
+void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
+                     u32 len32)
+{
+       struct dmae_command dmae;
+
+       if (!bp->dmae_ready) {
+               u32 *data = bnx2x_sp(bp, wb_data[0]);
+
+               DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x  len32 %d)"
+                  "  using indirect\n", dst_addr, len32);
+               bnx2x_init_ind_wr(bp, dst_addr, data, len32);
+               return;
+       }
+
+       /* set opcode and fixed command fields */
+       bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
+
+       /* fill in addresses and len */
+       dmae.src_addr_lo = U64_LO(dma_addr);
+       dmae.src_addr_hi = U64_HI(dma_addr);
+       dmae.dst_addr_lo = dst_addr >> 2;
+       dmae.dst_addr_hi = 0;
+       dmae.len = len32;
+
+       bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
+
+       /* issue the command and wait for completion */
+       bnx2x_issue_dmae_with_comp(bp, &dmae);
 }
 
 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 {
        struct dmae_command dmae;
-       u32 *wb_comp = bnx2x_sp(bp, wb_comp);
-       int cnt = 200;
 
        if (!bp->dmae_ready) {
                u32 *data = bnx2x_sp(bp, wb_data[0]);
@@ -286,66 +534,24 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
                return;
        }
 
-       memset(&dmae, 0, sizeof(struct dmae_command));
+       /* set opcode and fixed command fields */
+       bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 
-       dmae.opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
-                      DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
-                      DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
-#ifdef __BIG_ENDIAN
-                      DMAE_CMD_ENDIANITY_B_DW_SWAP |
-#else
-                      DMAE_CMD_ENDIANITY_DW_SWAP |
-#endif
-                      (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
-                      (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
+       /* fill in addresses and len */
        dmae.src_addr_lo = src_addr >> 2;
        dmae.src_addr_hi = 0;
        dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
        dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
        dmae.len = len32;
-       dmae.comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
-       dmae.comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
-       dmae.comp_val = DMAE_COMP_VAL;
 
-       DP(BNX2X_MSG_OFF, "DMAE: opcode 0x%08x\n"
-          DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
-                   "dst_addr [%x:%08x (%08x)]\n"
-          DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
-          dmae.opcode, dmae.src_addr_hi, dmae.src_addr_lo,
-          dmae.len, dmae.dst_addr_hi, dmae.dst_addr_lo, src_addr,
-          dmae.comp_addr_hi, dmae.comp_addr_lo, dmae.comp_val);
+       bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
 
-       mutex_lock(&bp->dmae_mutex);
-
-       memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
-       *wb_comp = 0;
-
-       bnx2x_post_dmae(bp, &dmae, INIT_DMAE_C(bp));
-
-       udelay(5);
-
-       while (*wb_comp != DMAE_COMP_VAL) {
-
-               if (!cnt) {
-                       BNX2X_ERR("DMAE timeout!\n");
-                       break;
-               }
-               cnt--;
-               /* adjust delay for emulation/FPGA */
-               if (CHIP_REV_IS_SLOW(bp))
-                       msleep(100);
-               else
-                       udelay(5);
-       }
-       DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
-          bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
-          bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
-
-       mutex_unlock(&bp->dmae_mutex);
+       /* issue the command and wait for completion */
+       bnx2x_issue_dmae_with_comp(bp, &dmae);
 }
 
-void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
-                              u32 addr, u32 len)
+static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
+                                     u32 addr, u32 len)
 {
        int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
        int offset = 0;
@@ -502,25 +708,38 @@ static int bnx2x_mc_assert(struct bnx2x *bp)
        return rc;
 }
 
-static void bnx2x_fw_dump(struct bnx2x *bp)
+void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 {
-       u32 addr;
+       u32 addr, val;
        u32 mark, offset;
        __be32 data[9];
        int word;
-
+       u32 trace_shmem_base;
        if (BP_NOMCP(bp)) {
                BNX2X_ERR("NO MCP - can not dump\n");
                return;
        }
+       netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
+               (bp->common.bc_ver & 0xff0000) >> 16,
+               (bp->common.bc_ver & 0xff00) >> 8,
+               (bp->common.bc_ver & 0xff));
+
+       val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
+       if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
+               printk("%s" "MCP PC at 0x%x\n", lvl, val);
 
-       addr = bp->common.shmem_base - 0x0800 + 4;
+       if (BP_PATH(bp) == 0)
+               trace_shmem_base = bp->common.shmem_base;
+       else
+               trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
+       addr = trace_shmem_base - 0x0800 + 4;
        mark = REG_RD(bp, addr);
-       mark = MCP_REG_MCPR_SCRATCH + ((mark + 0x3) & ~0x3) - 0x08000000;
-       pr_err("begin fw dump (mark 0x%x)\n", mark);
+       mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
+                       + ((mark + 0x3) & ~0x3) - 0x08000000;
+       printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 
-       pr_err("");
-       for (offset = mark; offset <= bp->common.shmem_base; offset += 0x8*4) {
+       printk("%s", lvl);
+       for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
                for (word = 0; word < 8; word++)
                        data[word] = htonl(REG_RD(bp, offset + 4*word));
                data[8] = 0x0;
@@ -532,13 +751,23 @@ static void bnx2x_fw_dump(struct bnx2x *bp)
                data[8] = 0x0;
                pr_cont("%s", (char *)data);
        }
-       pr_err("end of fw dump\n");
+       printk("%s" "end of fw dump\n", lvl);
+}
+
+static inline void bnx2x_fw_dump(struct bnx2x *bp)
+{
+       bnx2x_fw_dump_lvl(bp, KERN_ERR);
 }
 
 void bnx2x_panic_dump(struct bnx2x *bp)
 {
        int i;
-       u16 j, start, end;
+       u16 j;
+       struct hc_sp_status_block_data sp_sb_data;
+       int func = BP_FUNC(bp);
+#ifdef BNX2X_STOP_ON_ERROR
+       u16 start = 0, end = 0;
+#endif
 
        bp->stats_state = STATS_STATE_DISABLED;
        DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
@@ -547,47 +776,156 @@ void bnx2x_panic_dump(struct bnx2x *bp)
 
        /* Indices */
        /* Common */
-       BNX2X_ERR("def_c_idx(0x%x)  def_u_idx(0x%x)  def_x_idx(0x%x)"
-                 "  def_t_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)"
-                 "  spq_prod_idx(0x%x)\n",
-                 bp->def_c_idx, bp->def_u_idx, bp->def_x_idx, bp->def_t_idx,
-                 bp->def_att_idx, bp->attn_state, bp->spq_prod_idx);
-
-       /* Rx */
-       for_each_queue(bp, i) {
+       BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)"
+                 "  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
+                 bp->def_idx, bp->def_att_idx, bp->attn_state,
+                 bp->spq_prod_idx, bp->stats_counter);
+       BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
+                 bp->def_status_blk->atten_status_block.attn_bits,
+                 bp->def_status_blk->atten_status_block.attn_bits_ack,
+                 bp->def_status_blk->atten_status_block.status_block_id,
+                 bp->def_status_blk->atten_status_block.attn_bits_index);
+       BNX2X_ERR("     def (");
+       for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
+               pr_cont("0x%x%s",
+                      bp->def_status_blk->sp_sb.index_values[i],
+                      (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
+
+       for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
+               *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
+                       CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
+                       i*sizeof(u32));
+
+       pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) "
+                        "pf_id(0x%x)  vnic_id(0x%x)  "
+                        "vf_id(0x%x)  vf_valid (0x%x) "
+                        "state(0x%x)\n",
+              sp_sb_data.igu_sb_id,
+              sp_sb_data.igu_seg_id,
+              sp_sb_data.p_func.pf_id,
+              sp_sb_data.p_func.vnic_id,
+              sp_sb_data.p_func.vf_id,
+              sp_sb_data.p_func.vf_valid,
+              sp_sb_data.state);
+
+
+       for_each_eth_queue(bp, i) {
                struct bnx2x_fastpath *fp = &bp->fp[i];
-
+               int loop;
+               struct hc_status_block_data_e2 sb_data_e2;
+               struct hc_status_block_data_e1x sb_data_e1x;
+               struct hc_status_block_sm  *hc_sm_p =
+                       CHIP_IS_E1x(bp) ?
+                       sb_data_e1x.common.state_machine :
+                       sb_data_e2.common.state_machine;
+               struct hc_index_data *hc_index_p =
+                       CHIP_IS_E1x(bp) ?
+                       sb_data_e1x.index_data :
+                       sb_data_e2.index_data;
+               int data_size;
+               u32 *sb_data_p;
+
+               /* Rx */
                BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)"
-                         "  *rx_bd_cons_sb(0x%x)  rx_comp_prod(0x%x)"
+                         "  rx_comp_prod(0x%x)"
                          "  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
                          i, fp->rx_bd_prod, fp->rx_bd_cons,
-                         le16_to_cpu(*fp->rx_bd_cons_sb), fp->rx_comp_prod,
+                         fp->rx_comp_prod,
                          fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
                BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)"
-                         "  fp_u_idx(0x%x) *sb_u_idx(0x%x)\n",
+                         "  fp_hc_idx(0x%x)\n",
                          fp->rx_sge_prod, fp->last_max_sge,
-                         le16_to_cpu(fp->fp_u_idx),
-                         fp->status_blk->u_status_block.status_block_index);
-       }
-
-       /* Tx */
-       for_each_queue(bp, i) {
-               struct bnx2x_fastpath *fp = &bp->fp[i];
+                         le16_to_cpu(fp->fp_hc_idx));
 
+               /* Tx */
                BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)"
                          "  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)"
                          "  *tx_cons_sb(0x%x)\n",
                          i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
                          fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
-               BNX2X_ERR("     fp_c_idx(0x%x)  *sb_c_idx(0x%x)"
-                         "  tx_db_prod(0x%x)\n", le16_to_cpu(fp->fp_c_idx),
-                         fp->status_blk->c_status_block.status_block_index,
-                         fp->tx_db.data.prod);
+
+               loop = CHIP_IS_E1x(bp) ?
+                       HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
+
+               /* host sb data */
+
+#ifdef BCM_CNIC
+               if (IS_FCOE_FP(fp))
+                       continue;
+#endif
+               BNX2X_ERR("     run indexes (");
+               for (j = 0; j < HC_SB_MAX_SM; j++)
+                       pr_cont("0x%x%s",
+                              fp->sb_running_index[j],
+                              (j == HC_SB_MAX_SM - 1) ? ")" : " ");
+
+               BNX2X_ERR("     indexes (");
+               for (j = 0; j < loop; j++)
+                       pr_cont("0x%x%s",
+                              fp->sb_index_values[j],
+                              (j == loop - 1) ? ")" : " ");
+               /* fw sb data */
+               data_size = CHIP_IS_E1x(bp) ?
+                       sizeof(struct hc_status_block_data_e1x) :
+                       sizeof(struct hc_status_block_data_e2);
+               data_size /= sizeof(u32);
+               sb_data_p = CHIP_IS_E1x(bp) ?
+                       (u32 *)&sb_data_e1x :
+                       (u32 *)&sb_data_e2;
+               /* copy sb data in here */
+               for (j = 0; j < data_size; j++)
+                       *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
+                               CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
+                               j * sizeof(u32));
+
+               if (!CHIP_IS_E1x(bp)) {
+                       pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) "
+                               "vnic_id(0x%x)  same_igu_sb_1b(0x%x) "
+                               "state(0x%x)\n",
+                               sb_data_e2.common.p_func.pf_id,
+                               sb_data_e2.common.p_func.vf_id,
+                               sb_data_e2.common.p_func.vf_valid,
+                               sb_data_e2.common.p_func.vnic_id,
+                               sb_data_e2.common.same_igu_sb_1b,
+                               sb_data_e2.common.state);
+               } else {
+                       pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) "
+                               "vnic_id(0x%x)  same_igu_sb_1b(0x%x) "
+                               "state(0x%x)\n",
+                               sb_data_e1x.common.p_func.pf_id,
+                               sb_data_e1x.common.p_func.vf_id,
+                               sb_data_e1x.common.p_func.vf_valid,
+                               sb_data_e1x.common.p_func.vnic_id,
+                               sb_data_e1x.common.same_igu_sb_1b,
+                               sb_data_e1x.common.state);
+               }
+
+               /* SB_SMs data */
+               for (j = 0; j < HC_SB_MAX_SM; j++) {
+                       pr_cont("SM[%d] __flags (0x%x) "
+                              "igu_sb_id (0x%x)  igu_seg_id(0x%x) "
+                              "time_to_expire (0x%x) "
+                              "timer_value(0x%x)\n", j,
+                              hc_sm_p[j].__flags,
+                              hc_sm_p[j].igu_sb_id,
+                              hc_sm_p[j].igu_seg_id,
+                              hc_sm_p[j].time_to_expire,
+                              hc_sm_p[j].timer_value);
+               }
+
+               /* Indecies data */
+               for (j = 0; j < loop; j++) {
+                       pr_cont("INDEX[%d] flags (0x%x) "
+                                        "timeout (0x%x)\n", j,
+                              hc_index_p[j].flags,
+                              hc_index_p[j].timeout);
+               }
        }
 
+#ifdef BNX2X_STOP_ON_ERROR
        /* Rings */
        /* Rx */
-       for_each_queue(bp, i) {
+       for_each_rx_queue(bp, i) {
                struct bnx2x_fastpath *fp = &bp->fp[i];
 
                start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
@@ -621,7 +959,7 @@ void bnx2x_panic_dump(struct bnx2x *bp)
        }
 
        /* Tx */
-       for_each_queue(bp, i) {
+       for_each_tx_queue(bp, i) {
                struct bnx2x_fastpath *fp = &bp->fp[i];
 
                start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
@@ -642,13 +980,380 @@ void bnx2x_panic_dump(struct bnx2x *bp)
                                  i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
                }
        }
-
+#endif
        bnx2x_fw_dump(bp);
        bnx2x_mc_assert(bp);
        BNX2X_ERR("end crash dump -----------------\n");
 }
 
-void bnx2x_int_enable(struct bnx2x *bp)
+/*
+ * FLR Support for E2
+ *
+ * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
+ * initialization.
+ */
+#define FLR_WAIT_USEC          10000   /* 10 miliseconds */
+#define FLR_WAIT_INTERAVAL     50      /* usec */
+#define        FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
+
+struct pbf_pN_buf_regs {
+       int pN;
+       u32 init_crd;
+       u32 crd;
+       u32 crd_freed;
+};
+
+struct pbf_pN_cmd_regs {
+       int pN;
+       u32 lines_occup;
+       u32 lines_freed;
+};
+
+static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
+                                    struct pbf_pN_buf_regs *regs,
+                                    u32 poll_count)
+{
+       u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
+       u32 cur_cnt = poll_count;
+
+       crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
+       crd = crd_start = REG_RD(bp, regs->crd);
+       init_crd = REG_RD(bp, regs->init_crd);
+
+       DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
+       DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
+       DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
+
+       while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
+              (init_crd - crd_start))) {
+               if (cur_cnt--) {
+                       udelay(FLR_WAIT_INTERAVAL);
+                       crd = REG_RD(bp, regs->crd);
+                       crd_freed = REG_RD(bp, regs->crd_freed);
+               } else {
+                       DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
+                          regs->pN);
+                       DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
+                          regs->pN, crd);
+                       DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
+                          regs->pN, crd_freed);
+                       break;
+               }
+       }
+       DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
+          poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
+}
+
+static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
+                                    struct pbf_pN_cmd_regs *regs,
+                                    u32 poll_count)
+{
+       u32 occup, to_free, freed, freed_start;
+       u32 cur_cnt = poll_count;
+
+       occup = to_free = REG_RD(bp, regs->lines_occup);
+       freed = freed_start = REG_RD(bp, regs->lines_freed);
+
+       DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
+       DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
+
+       while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
+               if (cur_cnt--) {
+                       udelay(FLR_WAIT_INTERAVAL);
+                       occup = REG_RD(bp, regs->lines_occup);
+                       freed = REG_RD(bp, regs->lines_freed);
+               } else {
+                       DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
+                          regs->pN);
+                       DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
+                          regs->pN, occup);
+                       DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
+                          regs->pN, freed);
+                       break;
+               }
+       }
+       DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
+          poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
+}
+
+static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
+                                    u32 expected, u32 poll_count)
+{
+       u32 cur_cnt = poll_count;
+       u32 val;
+
+       while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
+               udelay(FLR_WAIT_INTERAVAL);
+
+       return val;
+}
+
+static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
+                                                 char *msg, u32 poll_cnt)
+{
+       u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
+       if (val != 0) {
+               BNX2X_ERR("%s usage count=%d\n", msg, val);
+               return 1;
+       }
+       return 0;
+}
+
+static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
+{
+       /* adjust polling timeout */
+       if (CHIP_REV_IS_EMUL(bp))
+               return FLR_POLL_CNT * 2000;
+
+       if (CHIP_REV_IS_FPGA(bp))
+               return FLR_POLL_CNT * 120;
+
+       return FLR_POLL_CNT;
+}
+
+static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
+{
+       struct pbf_pN_cmd_regs cmd_regs[] = {
+               {0, (CHIP_IS_E3B0(bp)) ?
+                       PBF_REG_TQ_OCCUPANCY_Q0 :
+                       PBF_REG_P0_TQ_OCCUPANCY,
+                   (CHIP_IS_E3B0(bp)) ?
+                       PBF_REG_TQ_LINES_FREED_CNT_Q0 :
+                       PBF_REG_P0_TQ_LINES_FREED_CNT},
+               {1, (CHIP_IS_E3B0(bp)) ?
+                       PBF_REG_TQ_OCCUPANCY_Q1 :
+                       PBF_REG_P1_TQ_OCCUPANCY,
+                   (CHIP_IS_E3B0(bp)) ?
+                       PBF_REG_TQ_LINES_FREED_CNT_Q1 :
+                       PBF_REG_P1_TQ_LINES_FREED_CNT},
+               {4, (CHIP_IS_E3B0(bp)) ?
+                       PBF_REG_TQ_OCCUPANCY_LB_Q :
+                       PBF_REG_P4_TQ_OCCUPANCY,
+                   (CHIP_IS_E3B0(bp)) ?
+                       PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
+                       PBF_REG_P4_TQ_LINES_FREED_CNT}
+       };
+
+       struct pbf_pN_buf_regs buf_regs[] = {
+               {0, (CHIP_IS_E3B0(bp)) ?
+                       PBF_REG_INIT_CRD_Q0 :
+                       PBF_REG_P0_INIT_CRD ,
+                   (CHIP_IS_E3B0(bp)) ?
+                       PBF_REG_CREDIT_Q0 :
+                       PBF_REG_P0_CREDIT,
+                   (CHIP_IS_E3B0(bp)) ?
+                       PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
+                       PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
+               {1, (CHIP_IS_E3B0(bp)) ?
+                       PBF_REG_INIT_CRD_Q1 :
+                       PBF_REG_P1_INIT_CRD,
+                   (CHIP_IS_E3B0(bp)) ?
+                       PBF_REG_CREDIT_Q1 :
+                       PBF_REG_P1_CREDIT,
+                   (CHIP_IS_E3B0(bp)) ?
+                       PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
+                       PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
+               {4, (CHIP_IS_E3B0(bp)) ?
+                       PBF_REG_INIT_CRD_LB_Q :
+                       PBF_REG_P4_INIT_CRD,
+                   (CHIP_IS_E3B0(bp)) ?
+                       PBF_REG_CREDIT_LB_Q :
+                       PBF_REG_P4_CREDIT,
+                   (CHIP_IS_E3B0(bp)) ?
+                       PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
+                       PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
+       };
+
+       int i;
+
+       /* Verify the command queues are flushed P0, P1, P4 */
+       for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
+               bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
+
+
+       /* Verify the transmission buffers are flushed P0, P1, P4 */
+       for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
+               bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
+}
+
+#define OP_GEN_PARAM(param) \
+       (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
+
+#define OP_GEN_TYPE(type) \
+       (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
+
+#define OP_GEN_AGG_VECT(index) \
+       (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
+
+
+static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
+                                        u32 poll_cnt)
+{
+       struct sdm_op_gen op_gen = {0};
+
+       u32 comp_addr = BAR_CSTRORM_INTMEM +
+                       CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
+       int ret = 0;
+
+       if (REG_RD(bp, comp_addr)) {
+               BNX2X_ERR("Cleanup complete is not 0\n");
+               return 1;
+       }
+
+       op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
+       op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
+       op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
+       op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
+
+       DP(BNX2X_MSG_SP, "FW Final cleanup\n");
+       REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
+
+       if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
+               BNX2X_ERR("FW final cleanup did not succeed\n");
+               ret = 1;
+       }
+       /* Zero completion for nxt FLR */
+       REG_WR(bp, comp_addr, 0);
+
+       return ret;
+}
+
+static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
+{
+       int pos;
+       u16 status;
+
+       pos = pci_pcie_cap(dev);
+       if (!pos)
+               return false;
+
+       pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
+       return status & PCI_EXP_DEVSTA_TRPND;
+}
+
+/* PF FLR specific routines
+*/
+static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
+{
+
+       /* wait for CFC PF usage-counter to zero (includes all the VFs) */
+       if (bnx2x_flr_clnup_poll_hw_counter(bp,
+                       CFC_REG_NUM_LCIDS_INSIDE_PF,
+                       "CFC PF usage counter timed out",
+                       poll_cnt))
+               return 1;
+
+
+       /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
+       if (bnx2x_flr_clnup_poll_hw_counter(bp,
+                       DORQ_REG_PF_USAGE_CNT,
+                       "DQ PF usage counter timed out",
+                       poll_cnt))
+               return 1;
+
+       /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
+       if (bnx2x_flr_clnup_poll_hw_counter(bp,
+                       QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
+                       "QM PF usage counter timed out",
+                       poll_cnt))
+               return 1;
+
+       /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
+       if (bnx2x_flr_clnup_poll_hw_counter(bp,
+                       TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
+                       "Timers VNIC usage counter timed out",
+                       poll_cnt))
+               return 1;
+       if (bnx2x_flr_clnup_poll_hw_counter(bp,
+                       TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
+                       "Timers NUM_SCANS usage counter timed out",
+                       poll_cnt))
+               return 1;
+
+       /* Wait DMAE PF usage counter to zero */
+       if (bnx2x_flr_clnup_poll_hw_counter(bp,
+                       dmae_reg_go_c[INIT_DMAE_C(bp)],
+                       "DMAE dommand register timed out",
+                       poll_cnt))
+               return 1;
+
+       return 0;
+}
+
+static void bnx2x_hw_enable_status(struct bnx2x *bp)
+{
+       u32 val;
+
+       val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
+       DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
+
+       val = REG_RD(bp, PBF_REG_DISABLE_PF);
+       DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
+
+       val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
+       DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
+
+       val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
+       DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
+
+       val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
+       DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
+
+       val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
+       DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
+
+       val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
+       DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
+
+       val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
+       DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
+          val);
+}
+
+static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
+{
+       u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
+
+       DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
+
+       /* Re-enable PF target read access */
+       REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
+
+       /* Poll HW usage counters */
+       if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
+               return -EBUSY;
+
+       /* Zero the igu 'trailing edge' and 'leading edge' */
+
+       /* Send the FW cleanup command */
+       if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
+               return -EBUSY;
+
+       /* ATC cleanup */
+
+       /* Verify TX hw is flushed */
+       bnx2x_tx_hw_flushed(bp, poll_cnt);
+
+       /* Wait 100ms (not adjusted according to platform) */
+       msleep(100);
+
+       /* Verify no pending pci transactions */
+       if (bnx2x_is_pcie_pending(bp->pdev))
+               BNX2X_ERR("PCIE Transactions still pending\n");
+
+       /* Debug */
+       bnx2x_hw_enable_status(bp);
+
+       /*
+        * Master enable - Due to WB DMAE writes performed before this
+        * register is re-initialized as part of the regular function init
+        */
+       REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
+
+       return 0;
+}
+
+static void bnx2x_hc_int_enable(struct bnx2x *bp)
 {
        int port = BP_PORT(bp);
        u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
@@ -672,14 +1377,19 @@ void bnx2x_int_enable(struct bnx2x *bp)
                        HC_CONFIG_0_REG_INT_LINE_EN_0 |
                        HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 
-               DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
-                  val, port, addr);
+               if (!CHIP_IS_E1(bp)) {
+                       DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
+                          val, port, addr);
 
-               REG_WR(bp, addr, val);
+                       REG_WR(bp, addr, val);
 
-               val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
+                       val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
+               }
        }
 
+       if (CHIP_IS_E1(bp))
+               REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
+
        DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  mode %s\n",
           val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
 
@@ -690,9 +1400,9 @@ void bnx2x_int_enable(struct bnx2x *bp)
        mmiowb();
        barrier();
 
-       if (CHIP_IS_E1H(bp)) {
+       if (!CHIP_IS_E1(bp)) {
                /* init leading/trailing edge */
-               if (IS_E1HMF(bp)) {
+               if (IS_MF(bp)) {
                        val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
                        if (bp->port.pmf)
                                /* enable nig and gpio3 attention */
@@ -708,16 +1418,91 @@ void bnx2x_int_enable(struct bnx2x *bp)
        mmiowb();
 }
 
-static void bnx2x_int_disable(struct bnx2x *bp)
+static void bnx2x_igu_int_enable(struct bnx2x *bp)
+{
+       u32 val;
+       int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
+       int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
+
+       val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
+
+       if (msix) {
+               val &= ~(IGU_PF_CONF_INT_LINE_EN |
+                        IGU_PF_CONF_SINGLE_ISR_EN);
+               val |= (IGU_PF_CONF_FUNC_EN |
+                       IGU_PF_CONF_MSI_MSIX_EN |
+                       IGU_PF_CONF_ATTN_BIT_EN);
+       } else if (msi) {
+               val &= ~IGU_PF_CONF_INT_LINE_EN;
+               val |= (IGU_PF_CONF_FUNC_EN |
+                       IGU_PF_CONF_MSI_MSIX_EN |
+                       IGU_PF_CONF_ATTN_BIT_EN |
+                       IGU_PF_CONF_SINGLE_ISR_EN);
+       } else {
+               val &= ~IGU_PF_CONF_MSI_MSIX_EN;
+               val |= (IGU_PF_CONF_FUNC_EN |
+                       IGU_PF_CONF_INT_LINE_EN |
+                       IGU_PF_CONF_ATTN_BIT_EN |
+                       IGU_PF_CONF_SINGLE_ISR_EN);
+       }
+
+       DP(NETIF_MSG_INTR, "write 0x%x to IGU  mode %s\n",
+          val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
+
+       REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
+
+       barrier();
+
+       /* init leading/trailing edge */
+       if (IS_MF(bp)) {
+               val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
+               if (bp->port.pmf)
+                       /* enable nig and gpio3 attention */
+                       val |= 0x1100;
+       } else
+               val = 0xffff;
+
+       REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
+       REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
+
+       /* Make sure that interrupts are indeed enabled from here on */
+       mmiowb();
+}
+
+void bnx2x_int_enable(struct bnx2x *bp)
+{
+       if (bp->common.int_block == INT_BLOCK_HC)
+               bnx2x_hc_int_enable(bp);
+       else
+               bnx2x_igu_int_enable(bp);
+}
+
+static void bnx2x_hc_int_disable(struct bnx2x *bp)
 {
        int port = BP_PORT(bp);
        u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
        u32 val = REG_RD(bp, addr);
 
-       val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
-                HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
-                HC_CONFIG_0_REG_INT_LINE_EN_0 |
-                HC_CONFIG_0_REG_ATTN_BIT_EN_0);
+       /*
+        * in E1 we must use only PCI configuration space to disable
+        * MSI/MSIX capablility
+        * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
+        */
+       if (CHIP_IS_E1(bp)) {
+               /*  Since IGU_PF_CONF_MSI_MSIX_EN still always on
+                *  Use mask register to prevent from HC sending interrupts
+                *  after we exit the function
+                */
+               REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
+
+               val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
+                        HC_CONFIG_0_REG_INT_LINE_EN_0 |
+                        HC_CONFIG_0_REG_ATTN_BIT_EN_0);
+       } else
+               val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
+                        HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
+                        HC_CONFIG_0_REG_INT_LINE_EN_0 |
+                        HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 
        DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
           val, port, addr);
@@ -730,15 +1515,37 @@ static void bnx2x_int_disable(struct bnx2x *bp)
                BNX2X_ERR("BUG! proper val not read from IGU!\n");
 }
 
+static void bnx2x_igu_int_disable(struct bnx2x *bp)
+{
+       u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
+
+       val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
+                IGU_PF_CONF_INT_LINE_EN |
+                IGU_PF_CONF_ATTN_BIT_EN);
+
+       DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
+
+       /* flush all outstanding writes */
+       mmiowb();
+
+       REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
+       if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
+               BNX2X_ERR("BUG! proper val not read from IGU!\n");
+}
+
+static void bnx2x_int_disable(struct bnx2x *bp)
+{
+       if (bp->common.int_block == INT_BLOCK_HC)
+               bnx2x_hc_int_disable(bp);
+       else
+               bnx2x_igu_int_disable(bp);
+}
+
 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
 {
        int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
        int i, offset;
 
-       /* disable interrupt handling */
-       atomic_inc(&bp->intr_sem);
-       smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
-
        if (disable_hw)
                /* prevent the HW from sending interrupts */
                bnx2x_int_disable(bp);
@@ -750,13 +1557,14 @@ void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
 #ifdef BCM_CNIC
                offset++;
 #endif
-               for_each_queue(bp, i)
-                       synchronize_irq(bp->msix_table[i + offset].vector);
+               for_each_eth_queue(bp, i)
+                       synchronize_irq(bp->msix_table[offset++].vector);
        } else
                synchronize_irq(bp->pdev->irq);
 
        /* make sure sp_task is not running */
        cancel_delayed_work(&bp->sp_task);
+       cancel_delayed_work(&bp->period_task);
        flush_workqueue(bnx2x_wq);
 }
 
@@ -800,93 +1608,112 @@ static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
        return false;
 }
 
+/**
+ * bnx2x_get_leader_lock_resource - get the recovery leader resource id
+ *
+ * @bp:        driver handle
+ *
+ * Returns the recovery leader resource id according to the engine this function
+ * belongs to. Currently only only 2 engines is supported.
+ */
+static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
+{
+       if (BP_PATH(bp))
+               return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
+       else
+               return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
+}
+
+/**
+ * bnx2x_trylock_leader_lock- try to aquire a leader lock.
+ *
+ * @bp: driver handle
+ *
+ * Tries to aquire a leader lock for cuurent engine.
+ */
+static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
+{
+       return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
+}
 
 #ifdef BCM_CNIC
-static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid);
+static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
 #endif
 
-void bnx2x_sp_event(struct bnx2x_fastpath *fp,
-                          union eth_rx_cqe *rr_cqe)
+void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
 {
        struct bnx2x *bp = fp->bp;
        int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
        int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
+       enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
+       struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
 
        DP(BNX2X_MSG_SP,
           "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
           fp->index, cid, command, bp->state,
           rr_cqe->ramrod_cqe.ramrod_type);
 
-       bp->spq_left++;
-
-       if (fp->index) {
-               switch (command | fp->state) {
-               case (RAMROD_CMD_ID_ETH_CLIENT_SETUP |
-                                               BNX2X_FP_STATE_OPENING):
-                       DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n",
-                          cid);
-                       fp->state = BNX2X_FP_STATE_OPEN;
-                       break;
-
-               case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
-                       DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n",
-                          cid);
-                       fp->state = BNX2X_FP_STATE_HALTED;
-                       break;
-
-               default:
-                       BNX2X_ERR("unexpected MC reply (%d)  "
-                                 "fp[%d] state is %x\n",
-                                 command, fp->index, fp->state);
-                       break;
-               }
-               mb(); /* force bnx2x_wait_ramrod() to see the change */
-               return;
-       }
-
-       switch (command | bp->state) {
-       case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
-               DP(NETIF_MSG_IFUP, "got setup ramrod\n");
-               bp->state = BNX2X_STATE_OPEN;
-               break;
-
-       case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT):
-               DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
-               bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE;
-               fp->state = BNX2X_FP_STATE_HALTED;
+       switch (command) {
+       case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
+               DP(NETIF_MSG_IFUP, "got UPDATE ramrod. CID %d\n", cid);
+               drv_cmd = BNX2X_Q_CMD_UPDATE;
                break;
-
-       case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT):
-               DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n", cid);
-               bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED;
+       case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
+               DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
+               drv_cmd = BNX2X_Q_CMD_SETUP;
                break;
 
-#ifdef BCM_CNIC
-       case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_OPEN):
-               DP(NETIF_MSG_IFDOWN, "got delete ramrod for CID %d\n", cid);
-               bnx2x_cnic_cfc_comp(bp, cid);
+       case (RAMROD_CMD_ID_ETH_HALT):
+               DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
+               drv_cmd = BNX2X_Q_CMD_HALT;
                break;
-#endif
 
-       case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
-       case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG):
-               DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
-               bp->set_mac_pending--;
-               smp_wmb();
+       case (RAMROD_CMD_ID_ETH_TERMINATE):
+               DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
+               drv_cmd = BNX2X_Q_CMD_TERMINATE;
                break;
 
-       case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT):
-               DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
-               bp->set_mac_pending--;
-               smp_wmb();
+       case (RAMROD_CMD_ID_ETH_EMPTY):
+               DP(NETIF_MSG_IFDOWN, "got MULTI[%d] empty ramrod\n", cid);
+               drv_cmd = BNX2X_Q_CMD_EMPTY;
                break;
 
        default:
-               BNX2X_ERR("unexpected MC reply (%d)  bp->state is %x\n",
-                         command, bp->state);
-               break;
+               BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
+                         command, fp->index);
+               return;
        }
-       mb(); /* force bnx2x_wait_ramrod() to see the change */
+
+       if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
+           q_obj->complete_cmd(bp, q_obj, drv_cmd))
+               /* q_obj->complete_cmd() failure means that this was
+                * an unexpected completion.
+                *
+                * In this case we don't want to increase the bp->spq_left
+                * because apparently we haven't sent this command the first
+                * place.
+                */
+#ifdef BNX2X_STOP_ON_ERROR
+               bnx2x_panic();
+#else
+               return;
+#endif
+
+       smp_mb__before_atomic_inc();
+       atomic_inc(&bp->cq_spq_left);
+       /* push the change in bp->spq_left and towards the memory */
+       smp_mb__after_atomic_inc();
+
+       return;
+}
+
+void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
+                       u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
+{
+       u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
+
+       bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
+                                start);
 }
 
 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
@@ -903,44 +1730,37 @@ irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
        }
        DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
 
-       /* Return here if interrupt is disabled */
-       if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
-               DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
-               return IRQ_HANDLED;
-       }
-
 #ifdef BNX2X_STOP_ON_ERROR
        if (unlikely(bp->panic))
                return IRQ_HANDLED;
 #endif
 
-       for (i = 0; i < BNX2X_NUM_QUEUES(bp); i++) {
+       for_each_eth_queue(bp, i) {
                struct bnx2x_fastpath *fp = &bp->fp[i];
 
-               mask = 0x2 << fp->sb_id;
+               mask = 0x2 << (fp->index + CNIC_CONTEXT_USE);
                if (status & mask) {
-                       /* Handle Rx and Tx according to SB id */
+                       /* Handle Rx or Tx according to SB id */
                        prefetch(fp->rx_cons_sb);
-                       prefetch(&fp->status_blk->u_status_block.
-                                               status_block_index);
                        prefetch(fp->tx_cons_sb);
-                       prefetch(&fp->status_blk->c_status_block.
-                                               status_block_index);
+                       prefetch(&fp->sb_running_index[SM_RX_ID]);
                        napi_schedule(&bnx2x_fp(bp, fp->index, napi));
                        status &= ~mask;
                }
        }
 
 #ifdef BCM_CNIC
-       mask = 0x2 << CNIC_SB_ID(bp);
+       mask = 0x2;
        if (status & (mask | 0x1)) {
                struct cnic_ops *c_ops = NULL;
 
-               rcu_read_lock();
-               c_ops = rcu_dereference(bp->cnic_ops);
-               if (c_ops)
-                       c_ops->cnic_handler(bp->cnic_data, NULL);
-               rcu_read_unlock();
+               if (likely(bp->state == BNX2X_STATE_OPEN)) {
+                       rcu_read_lock();
+                       c_ops = rcu_dereference(bp->cnic_ops);
+                       if (c_ops)
+                               c_ops->cnic_handler(bp->cnic_data, NULL);
+                       rcu_read_unlock();
+               }
 
                status &= ~mask;
        }
@@ -961,9 +1781,6 @@ irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
        return IRQ_HANDLED;
 }
 
-/* end of fast path */
-
-
 /* Link */
 
 /*
@@ -1015,6 +1832,11 @@ int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
        return -EAGAIN;
 }
 
+int bnx2x_release_leader_lock(struct bnx2x *bp)
+{
+       return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
+}
+
 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
 {
        u32 lock_status;
@@ -1135,6 +1957,53 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
        return 0;
 }
 
+int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
+{
+       u32 gpio_reg = 0;
+       int rc = 0;
+
+       /* Any port swapping should be handled by caller. */
+
+       bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
+       /* read GPIO and mask except the float bits */
+       gpio_reg = REG_RD(bp, MISC_REG_GPIO);
+       gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
+       gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
+       gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
+
+       switch (mode) {
+       case MISC_REGISTERS_GPIO_OUTPUT_LOW:
+               DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
+               /* set CLR */
+               gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
+               break;
+
+       case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
+               DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
+               /* set SET */
+               gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
+               break;
+
+       case MISC_REGISTERS_GPIO_INPUT_HI_Z:
+               DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
+               /* set FLOAT */
+               gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
+               break;
+
+       default:
+               BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
+               rc = -EINVAL;
+               break;
+       }
+
+       if (rc == 0)
+               REG_WR(bp, MISC_REG_GPIO, gpio_reg);
+
+       bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
+
+       return rc;
+}
+
 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
 {
        /* The GPIO should be swapped if swap register is set and active */
@@ -1227,45 +2096,6 @@ static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
        return 0;
 }
 
-int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
-{
-       u32 sel_phy_idx = 0;
-       if (bp->link_vars.link_up) {
-               sel_phy_idx = EXT_PHY1;
-               /* In case link is SERDES, check if the EXT_PHY2 is the one */
-               if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
-                   (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE))
-                       sel_phy_idx = EXT_PHY2;
-       } else {
-
-               switch (bnx2x_phy_selection(&bp->link_params)) {
-               case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
-               case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
-               case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
-                      sel_phy_idx = EXT_PHY1;
-                      break;
-               case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
-               case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
-                      sel_phy_idx = EXT_PHY2;
-                      break;
-               }
-       }
-       /*
-       * The selected actived PHY is always after swapping (in case PHY
-       * swapping is enabled). So when swapping is enabled, we need to reverse
-       * the configuration
-       */
-
-       if (bp->link_params.multi_phy_config &
-           PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
-               if (sel_phy_idx == EXT_PHY1)
-                       sel_phy_idx = EXT_PHY2;
-               else if (sel_phy_idx == EXT_PHY2)
-                       sel_phy_idx = EXT_PHY1;
-       }
-       return LINK_CONFIG_IDX(sel_phy_idx);
-}
-
 void bnx2x_calc_fc_adv(struct bnx2x *bp)
 {
        u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
@@ -1273,12 +2103,12 @@ void bnx2x_calc_fc_adv(struct bnx2x *bp)
                MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
        case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
                bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
-                                         ADVERTISED_Pause);
+                                                  ADVERTISED_Pause);
                break;
 
        case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
                bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
-                                        ADVERTISED_Pause);
+                                                 ADVERTISED_Pause);
                break;
 
        case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
@@ -1287,12 +2117,11 @@ void bnx2x_calc_fc_adv(struct bnx2x *bp)
 
        default:
                bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
-                                         ADVERTISED_Pause);
+                                                  ADVERTISED_Pause);
                break;
        }
 }
 
-
 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
 {
        if (!BP_NOMCP(bp)) {
@@ -1302,7 +2131,7 @@ u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
                /* Initialize link parameters structure variables */
                /* It is recommended to turn off RX FC for jumbo frames
                   for better performance */
-               if (bp->dev->mtu > 5000)
+               if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
                        bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
                else
                        bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
@@ -1323,7 +2152,8 @@ u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
                if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
                        bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
                        bnx2x_link_report(bp);
-               }
+               } else
+                       queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
                bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
                return rc;
        }
@@ -1416,13 +2246,11 @@ static void bnx2x_init_port_minmax(struct bnx2x *bp)
 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
 {
        int all_zero = 1;
-       int port = BP_PORT(bp);
        int vn;
 
        bp->vn_weight_sum = 0;
        for (vn = VN_0; vn < E1HVN_MAX; vn++) {
-               int func = 2*vn + port;
-               u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
+               u32 vn_cfg = bp->mf_config[vn];
                u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
                                   FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
 
@@ -1439,8 +2267,12 @@ static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
                bp->vn_weight_sum += vn_min_rate;
        }
 
-       /* ... only if all min rates are zeros - disable fairness */
-       if (all_zero) {
+       /* if ETS or all min rates are zeros - disable fairness */
+       if (BNX2X_IS_ETS_ENABLED(bp)) {
+               bp->cmng.flags.cmng_enables &=
+                                       ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
+               DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
+       } else if (all_zero) {
                bp->cmng.flags.cmng_enables &=
                                        ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
                DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
@@ -1450,11 +2282,12 @@ static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
                                        CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
 }
 
-static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func)
+static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
 {
        struct rate_shaping_vars_per_vn m_rs_vn;
        struct fairness_vars_per_vn m_fair_vn;
-       u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
+       u32 vn_cfg = bp->mf_config[vn];
+       int func = 2*vn + BP_PORT(bp);
        u16 vn_min_rate, vn_max_rate;
        int i;
 
@@ -1464,14 +2297,24 @@ static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func)
                vn_max_rate = 0;
 
        } else {
+               u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
+
                vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
                                FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
-               /* If min rate is zero - set it to 1 */
-               if (!vn_min_rate)
+               /* If fairness is enabled (not all min rates are zeroes) and
+                  if current min rate is zero - set it to 1.
+                  This is a requirement of the algorithm. */
+               if (bp->vn_weight_sum && (vn_min_rate == 0))
                        vn_min_rate = DEF_MIN_RATE;
-               vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
-                               FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
+
+               if (IS_MF_SI(bp))
+                       /* maxCfg in percents of linkspeed */
+                       vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
+               else
+                       /* maxCfg is absolute in 100Mb units */
+                       vn_max_rate = maxCfg * 100;
        }
+
        DP(NETIF_MSG_IFUP,
           "func %d: vn_min_rate %d  vn_max_rate %d  vn_weight_sum %d\n",
           func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
@@ -1495,7 +2338,8 @@ static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func)
                m_fair_vn.vn_credit_delta =
                        max_t(u32, (vn_min_rate * (T_FAIR_COEF /
                                                   (8 * bp->vn_weight_sum))),
-                             (bp->cmng.fair_vars.fair_threshold * 2));
+                             (bp->cmng.fair_vars.fair_threshold +
+                                                       MIN_ABOVE_THRESH));
                DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
                   m_fair_vn.vn_credit_delta);
        }
@@ -1512,11 +2356,103 @@ static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func)
                       ((u32 *)(&m_fair_vn))[i]);
 }
 
+static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
+{
+       if (CHIP_REV_IS_SLOW(bp))
+               return CMNG_FNS_NONE;
+       if (IS_MF(bp))
+               return CMNG_FNS_MINMAX;
+
+       return CMNG_FNS_NONE;
+}
+
+void bnx2x_read_mf_cfg(struct bnx2x *bp)
+{
+       int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
+
+       if (BP_NOMCP(bp))
+               return; /* what should be the default bvalue in this case */
+
+       /* For 2 port configuration the absolute function number formula
+        * is:
+        *      abs_func = 2 * vn + BP_PORT + BP_PATH
+        *
+        *      and there are 4 functions per port
+        *
+        * For 4 port configuration it is
+        *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
+        *
+        *      and there are 2 functions per port
+        */
+       for (vn = VN_0; vn < E1HVN_MAX; vn++) {
+               int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
+
+               if (func >= E1H_FUNC_MAX)
+                       break;
+
+               bp->mf_config[vn] =
+                       MF_CFG_RD(bp, func_mf_config[func].config);
+       }
+}
+
+static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
+{
+
+       if (cmng_type == CMNG_FNS_MINMAX) {
+               int vn;
+
+               /* clear cmng_enables */
+               bp->cmng.flags.cmng_enables = 0;
+
+               /* read mf conf from shmem */
+               if (read_cfg)
+                       bnx2x_read_mf_cfg(bp);
+
+               /* Init rate shaping and fairness contexts */
+               bnx2x_init_port_minmax(bp);
+
+               /* vn_weight_sum and enable fairness if not 0 */
+               bnx2x_calc_vn_weight_sum(bp);
+
+               /* calculate and set min-max rate for each vn */
+               if (bp->port.pmf)
+                       for (vn = VN_0; vn < E1HVN_MAX; vn++)
+                               bnx2x_init_vn_minmax(bp, vn);
+
+               /* always enable rate shaping and fairness */
+               bp->cmng.flags.cmng_enables |=
+                                       CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
+               if (!bp->vn_weight_sum)
+                       DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
+                                  "  fairness will be disabled\n");
+               return;
+       }
+
+       /* rate shaping and fairness are disabled */
+       DP(NETIF_MSG_IFUP,
+          "rate shaping and fairness are disabled\n");
+}
+
+static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
+{
+       int port = BP_PORT(bp);
+       int func;
+       int vn;
+
+       /* Set the attention towards other drivers on the same port */
+       for (vn = VN_0; vn < E1HVN_MAX; vn++) {
+               if (vn == BP_E1HVN(bp))
+                       continue;
+
+               func = ((vn << 1) | port);
+               REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
+                      (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
+       }
+}
 
 /* This function is called upon link interrupt */
 static void bnx2x_link_attn(struct bnx2x *bp)
 {
-       u32 prev_link_status = bp->link_vars.link_status;
        /* Make sure that we are synced with the current statistics */
        bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 
@@ -1525,7 +2461,7 @@ static void bnx2x_link_attn(struct bnx2x *bp)
        if (bp->link_vars.link_up) {
 
                /* dropless flow control */
-               if (CHIP_IS_E1H(bp) && bp->dropless_fc) {
+               if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
                        int port = BP_PORT(bp);
                        u32 pause_enabled = 0;
 
@@ -1537,11 +2473,11 @@ static void bnx2x_link_attn(struct bnx2x *bp)
                               pause_enabled);
                }
 
-               if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
+               if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
                        struct host_port_stats *pstats;
 
                        pstats = bnx2x_sp(bp, port_stats);
-                       /* reset old bmac stats */
+                       /* reset old mac stats */
                        memset(&(pstats->mac_stx[0]), 0,
                               sizeof(struct mac_stx));
                }
@@ -1549,47 +2485,27 @@ static void bnx2x_link_attn(struct bnx2x *bp)
                        bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
        }
 
-       /* indicate link status only if link status actually changed */
-       if (prev_link_status != bp->link_vars.link_status)
-               bnx2x_link_report(bp);
+       if (bp->link_vars.link_up && bp->link_vars.line_speed) {
+               int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
 
-       if (IS_E1HMF(bp)) {
-               int port = BP_PORT(bp);
-               int func;
-               int vn;
-
-               /* Set the attention towards other drivers on the same port */
-               for (vn = VN_0; vn < E1HVN_MAX; vn++) {
-                       if (vn == BP_E1HVN(bp))
-                               continue;
-
-                       func = ((vn << 1) | port);
-                       REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
-                              (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
-               }
-
-               if (bp->link_vars.link_up) {
-                       int i;
+               if (cmng_fns != CMNG_FNS_NONE) {
+                       bnx2x_cmng_fns_init(bp, false, cmng_fns);
+                       storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
+               } else
+                       /* rate shaping and fairness are disabled */
+                       DP(NETIF_MSG_IFUP,
+                          "single function mode without fairness\n");
+       }
 
-                       /* Init rate shaping and fairness contexts */
-                       bnx2x_init_port_minmax(bp);
+       __bnx2x_link_report(bp);
 
-                       for (vn = VN_0; vn < E1HVN_MAX; vn++)
-                               bnx2x_init_vn_minmax(bp, 2*vn + port);
-
-                       /* Store it to internal memory */
-                       for (i = 0;
-                            i < sizeof(struct cmng_struct_per_port) / 4; i++)
-                               REG_WR(bp, BAR_XSTRORM_INTMEM +
-                                 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4,
-                                      ((u32 *)(&bp->cmng))[i]);
-               }
-       }
+       if (IS_MF(bp))
+               bnx2x_link_sync_notify(bp);
 }
 
 void bnx2x__link_status_update(struct bnx2x *bp)
 {
-       if ((bp->state != BNX2X_STATE_OPEN) || (bp->flags & MF_FUNC_DIS))
+       if (bp->state != BNX2X_STATE_OPEN)
                return;
 
        bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
@@ -1599,8 +2515,6 @@ void bnx2x__link_status_update(struct bnx2x *bp)
        else
                bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 
-       bnx2x_calc_vn_weight_sum(bp);
-
        /* indicate link status */
        bnx2x_link_report(bp);
 }
@@ -1613,10 +2527,26 @@ static void bnx2x_pmf_update(struct bnx2x *bp)
        bp->port.pmf = 1;
        DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
 
+       /*
+        * We need the mb() to ensure the ordering between the writing to
+        * bp->port.pmf here and reading it from the bnx2x_periodic_task().
+        */
+       smp_mb();
+
+       /* queue a periodic task */
+       queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
+
+       bnx2x_dcbx_pmf_update(bp);
+
        /* enable nig attention */
        val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
-       REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
-       REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
+       if (bp->common.int_block == INT_BLOCK_HC) {
+               REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
+               REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
+       } else if (!CHIP_IS_E1x(bp)) {
+               REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
+               REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
+       }
 
        bnx2x_stats_handle(bp, STATS_EVENT_PMF);
 }
@@ -1632,22 +2562,25 @@ static void bnx2x_pmf_update(struct bnx2x *bp)
 /* send the MCP a request, block until there is a reply */
 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
 {
-       int func = BP_FUNC(bp);
-       u32 seq = ++bp->fw_seq;
+       int mb_idx = BP_FW_MB_IDX(bp);
+       u32 seq;
        u32 rc = 0;
        u32 cnt = 1;
        u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
 
        mutex_lock(&bp->fw_mb_mutex);
-       SHMEM_WR(bp, func_mb[func].drv_mb_param, param);
-       SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq));
-       DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
+       seq = ++bp->fw_seq;
+       SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
+       SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
+
+       DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
+                       (command | seq), param);
 
        do {
                /* let the FW do it's magic ... */
                msleep(delay);
 
-               rc = SHMEM_RD(bp, func_mb[func].fw_mb_header);
+               rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
 
                /* Give the FW up to 5 second (500*10ms) */
        } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
@@ -1669,15 +2602,241 @@ u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
        return rc;
 }
 
+static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
+{
+#ifdef BCM_CNIC
+       /* Statistics are not supported for CNIC Clients at the moment */
+       if (IS_FCOE_FP(fp))
+               return false;
+#endif
+       return true;
+}
+
+void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
+{
+       if (CHIP_IS_E1x(bp)) {
+               struct tstorm_eth_function_common_config tcfg = {0};
+
+               storm_memset_func_cfg(bp, &tcfg, p->func_id);
+       }
+
+       /* Enable the function in the FW */
+       storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
+       storm_memset_func_en(bp, p->func_id, 1);
+
+       /* spq */
+       if (p->func_flgs & FUNC_FLG_SPQ) {
+               storm_memset_spq_addr(bp, p->spq_map, p->func_id);
+               REG_WR(bp, XSEM_REG_FAST_MEMORY +
+                      XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
+       }
+}
+
+static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
+                                             struct bnx2x_fastpath *fp,
+                                             bool leading)
+{
+       unsigned long flags = 0;
+
+       /* PF driver will always initialize the Queue to an ACTIVE state */
+       __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
+
+       /* calculate other queue flags */
+       if (IS_MF_SD(bp))
+               __set_bit(BNX2X_Q_FLG_OV, &flags);
+
+       if (IS_FCOE_FP(fp))
+               __set_bit(BNX2X_Q_FLG_FCOE, &flags);
+
+       if (!fp->disable_tpa)
+               __set_bit(BNX2X_Q_FLG_TPA, &flags);
+
+       if (stat_counter_valid(bp, fp)) {
+               __set_bit(BNX2X_Q_FLG_STATS, &flags);
+               __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
+       }
+
+       if (leading) {
+               __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
+               __set_bit(BNX2X_Q_FLG_MCAST, &flags);
+       }
+
+       /* Always set HW VLAN stripping */
+       __set_bit(BNX2X_Q_FLG_VLAN, &flags);
+
+       return flags;
+}
+
+static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
+       struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init)
+{
+       gen_init->stat_id = bnx2x_stats_id(fp);
+       gen_init->spcl_id = fp->cl_id;
+
+       /* Always use mini-jumbo MTU for FCoE L2 ring */
+       if (IS_FCOE_FP(fp))
+               gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
+       else
+               gen_init->mtu = bp->dev->mtu;
+}
+
+static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
+       struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
+       struct bnx2x_rxq_setup_params *rxq_init)
+{
+       u8 max_sge = 0;
+       u16 sge_sz = 0;
+       u16 tpa_agg_size = 0;
+
+       if (!fp->disable_tpa) {
+               pause->sge_th_hi = 250;
+               pause->sge_th_lo = 150;
+               tpa_agg_size = min_t(u32,
+                       (min_t(u32, 8, MAX_SKB_FRAGS) *
+                       SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
+               max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
+                       SGE_PAGE_SHIFT;
+               max_sge = ((max_sge + PAGES_PER_SGE - 1) &
+                         (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
+               sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
+                                   0xffff);
+       }
+
+       /* pause - not for e1 */
+       if (!CHIP_IS_E1(bp)) {
+               pause->bd_th_hi = 350;
+               pause->bd_th_lo = 250;
+               pause->rcq_th_hi = 350;
+               pause->rcq_th_lo = 250;
+
+               pause->pri_map = 1;
+       }
+
+       /* rxq setup */
+       rxq_init->dscr_map = fp->rx_desc_mapping;
+       rxq_init->sge_map = fp->rx_sge_mapping;
+       rxq_init->rcq_map = fp->rx_comp_mapping;
+       rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
+
+       /* This should be a maximum number of data bytes that may be
+        * placed on the BD (not including paddings).
+        */
+       rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN -
+               IP_HEADER_ALIGNMENT_PADDING;
+
+       rxq_init->cl_qzone_id = fp->cl_qzone_id;
+       rxq_init->tpa_agg_sz = tpa_agg_size;
+       rxq_init->sge_buf_sz = sge_sz;
+       rxq_init->max_sges_pkt = max_sge;
+       rxq_init->rss_engine_id = BP_FUNC(bp);
+
+       /* Maximum number or simultaneous TPA aggregation for this Queue.
+        *
+        * For PF Clients it should be the maximum avaliable number.
+        * VF driver(s) may want to define it to a smaller value.
+        */
+       rxq_init->max_tpa_queues =
+               (CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
+               ETH_MAX_AGGREGATION_QUEUES_E1H_E2);
+
+       rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
+       rxq_init->fw_sb_id = fp->fw_sb_id;
+
+       if (IS_FCOE_FP(fp))
+               rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
+       else
+               rxq_init->sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
+}
+
+static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
+       struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init)
+{
+       txq_init->dscr_map = fp->tx_desc_mapping;
+       txq_init->sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
+       txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
+       txq_init->fw_sb_id = fp->fw_sb_id;
+
+       /*
+        * set the tss leading client id for TX classfication ==
+        * leading RSS client id
+        */
+       txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
+
+       if (IS_FCOE_FP(fp)) {
+               txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
+               txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
+       }
+}
+
+static void bnx2x_pf_init(struct bnx2x *bp)
+{
+       struct bnx2x_func_init_params func_init = {0};
+       struct event_ring_data eq_data = { {0} };
+       u16 flags;
+
+       if (!CHIP_IS_E1x(bp)) {
+               /* reset IGU PF statistics: MSIX + ATTN */
+               /* PF */
+               REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
+                          BNX2X_IGU_STAS_MSG_VF_CNT*4 +
+                          (CHIP_MODE_IS_4_PORT(bp) ?
+                               BP_FUNC(bp) : BP_VN(bp))*4, 0);
+               /* ATTN */
+               REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
+                          BNX2X_IGU_STAS_MSG_VF_CNT*4 +
+                          BNX2X_IGU_STAS_MSG_PF_CNT*4 +
+                          (CHIP_MODE_IS_4_PORT(bp) ?
+                               BP_FUNC(bp) : BP_VN(bp))*4, 0);
+       }
+
+       /* function setup flags */
+       flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
+
+       /* This flag is relevant for E1x only.
+        * E2 doesn't have a TPA configuration in a function level.
+        */
+       flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
+
+       func_init.func_flgs = flags;
+       func_init.pf_id = BP_FUNC(bp);
+       func_init.func_id = BP_FUNC(bp);
+       func_init.spq_map = bp->spq_mapping;
+       func_init.spq_prod = bp->spq_prod_idx;
+
+       bnx2x_func_init(bp, &func_init);
+
+       memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
+
+       /*
+        * Congestion management values depend on the link rate
+        * There is no active link so initial link rate is set to 10 Gbps.
+        * When the link comes up The congestion management values are
+        * re-calculated according to the actual link rate.
+        */
+       bp->link_vars.line_speed = SPEED_10000;
+       bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
+
+       /* Only the PMF sets the HW */
+       if (bp->port.pmf)
+               storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
+
+       /* init Event Queue */
+       eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
+       eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
+       eq_data.producer = bp->eq_prod;
+       eq_data.index_id = HC_SP_INDEX_EQ_CONS;
+       eq_data.sb_id = DEF_SB_ID;
+       storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
+}
+
+
 static void bnx2x_e1h_disable(struct bnx2x *bp)
 {
        int port = BP_PORT(bp);
 
-       netif_tx_disable(bp->dev);
+       bnx2x_tx_disable(bp);
 
        REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
-
-       netif_carrier_off(bp->dev);
 }
 
 static void bnx2x_e1h_enable(struct bnx2x *bp)
@@ -1695,38 +2854,24 @@ static void bnx2x_e1h_enable(struct bnx2x *bp)
         */
 }
 
-static void bnx2x_update_min_max(struct bnx2x *bp)
+/* called due to MCP event (on pmf):
+ *     reread new bandwidth configuration
+ *     configure FW
+ *     notify others function about the change
+ */
+static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
 {
-       int port = BP_PORT(bp);
-       int vn, i;
-
-       /* Init rate shaping and fairness contexts */
-       bnx2x_init_port_minmax(bp);
-
-       bnx2x_calc_vn_weight_sum(bp);
-
-       for (vn = VN_0; vn < E1HVN_MAX; vn++)
-               bnx2x_init_vn_minmax(bp, 2*vn + port);
-
-       if (bp->port.pmf) {
-               int func;
-
-               /* Set the attention towards other drivers on the same port */
-               for (vn = VN_0; vn < E1HVN_MAX; vn++) {
-                       if (vn == BP_E1HVN(bp))
-                               continue;
-
-                       func = ((vn << 1) | port);
-                       REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
-                              (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
-               }
-
-               /* Store it to internal memory */
-               for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
-                       REG_WR(bp, BAR_XSTRORM_INTMEM +
-                              XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4,
-                              ((u32 *)(&bp->cmng))[i]);
+       if (bp->link_vars.link_up) {
+               bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
+               bnx2x_link_sync_notify(bp);
        }
+       storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
+}
+
+static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
+{
+       bnx2x_config_mf_bw(bp);
+       bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
 }
 
 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
@@ -1740,7 +2885,7 @@ static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
                 * where the bp->flags can change so it is done without any
                 * locks
                 */
-               if (bp->mf_config & FUNC_MF_CFG_FUNC_DISABLED) {
+               if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
                        DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
                        bp->flags |= MF_FUNC_DIS;
 
@@ -1754,8 +2899,7 @@ static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
                dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
        }
        if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
-
-               bnx2x_update_min_max(bp);
+               bnx2x_config_mf_bw(bp);
                dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
        }
 
@@ -1790,16 +2934,52 @@ static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
        /* Make sure that BD data is updated before writing the producer */
        wmb();
 
-       REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
-              bp->spq_prod_idx);
+       REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
+                bp->spq_prod_idx);
        mmiowb();
 }
 
-/* the slow path queue is odd since completions arrive on the fastpath ring */
+/**
+ * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
+ *
+ * @cmd:       command to check
+ * @cmd_type:  command type
+ */
+static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
+{
+       if ((cmd_type == NONE_CONNECTION_TYPE) ||
+           (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
+           (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
+           (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
+           (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
+           (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
+               return true;
+       else
+               return false;
+
+}
+
+
+/**
+ * bnx2x_sp_post - place a single command on an SP ring
+ *
+ * @bp:                driver handle
+ * @command:   command to place (e.g. SETUP, FILTER_RULES, etc.)
+ * @cid:       SW CID the command is related to
+ * @data_hi:   command private data address (high 32 bits)
+ * @data_lo:   command private data address (low 32 bits)
+ * @cmd_type:  command type (e.g. NONE, ETH)
+ *
+ * SP data is handled as if it's always an address pair, thus data fields are
+ * not swapped to little endian in upper functions. Instead this function swaps
+ * data as if it's two u32 fields.
+ */
 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
-                        u32 data_hi, u32 data_lo, int common)
+                 u32 data_hi, u32 data_lo, int cmd_type)
 {
        struct eth_spe *spe;
+       u16 type;
+       bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
 
 #ifdef BNX2X_STOP_ON_ERROR
        if (unlikely(bp->panic))
@@ -1808,11 +2988,18 @@ int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
 
        spin_lock_bh(&bp->spq_lock);
 
-       if (!bp->spq_left) {
-               BNX2X_ERR("BUG! SPQ ring full!\n");
-               spin_unlock_bh(&bp->spq_lock);
-               bnx2x_panic();
-               return -EBUSY;
+       if (common) {
+               if (!atomic_read(&bp->eq_spq_left)) {
+                       BNX2X_ERR("BUG! EQ ring full!\n");
+                       spin_unlock_bh(&bp->spq_lock);
+                       bnx2x_panic();
+                       return -EBUSY;
+               }
+       } else if (!atomic_read(&bp->cq_spq_left)) {
+                       BNX2X_ERR("BUG! SPQ ring full!\n");
+                       spin_unlock_bh(&bp->spq_lock);
+                       bnx2x_panic();
+                       return -EBUSY;
        }
 
        spe = bnx2x_sp_get_next(bp);
@@ -1821,22 +3008,39 @@ int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
        spe->hdr.conn_and_cmd_data =
                        cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
                                    HW_CID(bp, cid));
-       spe->hdr.type = cpu_to_le16(ETH_CONNECTION_TYPE);
-       if (common)
-               spe->hdr.type |=
-                       cpu_to_le16((1 << SPE_HDR_COMMON_RAMROD_SHIFT));
 
-       spe->data.mac_config_addr.hi = cpu_to_le32(data_hi);
-       spe->data.mac_config_addr.lo = cpu_to_le32(data_lo);
+       type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
+
+       type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
+                SPE_HDR_FUNCTION_ID);
+
+       spe->hdr.type = cpu_to_le16(type);
+
+       spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
+       spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
+
+       /* stats ramrod has it's own slot on the spq */
+       if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY) {
+               /*
+                * It's ok if the actual decrement is issued towards the memory
+                * somewhere between the spin_lock and spin_unlock. Thus no
+                * more explict memory barrier is needed.
+                */
+               if (common)
+                       atomic_dec(&bp->eq_spq_left);
+               else
+                       atomic_dec(&bp->cq_spq_left);
+       }
 
-       bp->spq_left--;
 
        DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
-          "SPQE[%x] (%x:%x)  command %d  hw_cid %x  data (%x:%x)  left %x\n",
+          "SPQE[%x] (%x:%x)  command %d  hw_cid %x  data (%x:%x) "
+          "type(0x%x) left (ETH, COMMON) (%x,%x)\n",
           bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
           (u32)(U64_LO(bp->spq_mapping) +
           (void *)bp->spq_prod_bd - (void *)bp->spq), command,
-          HW_CID(bp, cid), data_hi, data_lo, bp->spq_left);
+          HW_CID(bp, cid), data_hi, data_lo, type,
+          atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
 
        bnx2x_sp_prod_update(bp);
        spin_unlock_bh(&bp->spq_lock);
@@ -1873,32 +3077,27 @@ static void bnx2x_release_alr(struct bnx2x *bp)
        REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
 }
 
+#define BNX2X_DEF_SB_ATT_IDX   0x0001
+#define BNX2X_DEF_SB_IDX       0x0002
+
 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
 {
-       struct host_def_status_block *def_sb = bp->def_status_blk;
+       struct host_sp_status_block *def_sb = bp->def_status_blk;
        u16 rc = 0;
 
        barrier(); /* status block is written to by the chip */
        if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
                bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
-               rc |= 1;
-       }
-       if (bp->def_c_idx != def_sb->c_def_status_block.status_block_index) {
-               bp->def_c_idx = def_sb->c_def_status_block.status_block_index;
-               rc |= 2;
+               rc |= BNX2X_DEF_SB_ATT_IDX;
        }
-       if (bp->def_u_idx != def_sb->u_def_status_block.status_block_index) {
-               bp->def_u_idx = def_sb->u_def_status_block.status_block_index;
-               rc |= 4;
-       }
-       if (bp->def_x_idx != def_sb->x_def_status_block.status_block_index) {
-               bp->def_x_idx = def_sb->x_def_status_block.status_block_index;
-               rc |= 8;
-       }
-       if (bp->def_t_idx != def_sb->t_def_status_block.status_block_index) {
-               bp->def_t_idx = def_sb->t_def_status_block.status_block_index;
-               rc |= 16;
+
+       if (bp->def_idx != def_sb->sp_sb.running_index) {
+               bp->def_idx = def_sb->sp_sb.running_index;
+               rc |= BNX2X_DEF_SB_IDX;
        }
+
+       /* Do not reorder: indecies reading should complete before handling */
+       barrier();
        return rc;
 }
 
@@ -1909,14 +3108,13 @@ static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
 {
        int port = BP_PORT(bp);
-       u32 hc_addr = (HC_REG_COMMAND_REG + port*32 +
-                      COMMAND_REG_ATTN_BITS_SET);
        u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
                              MISC_REG_AEU_MASK_ATTN_FUNC_0;
        u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
                                       NIG_REG_MASK_INTERRUPT_PORT0;
        u32 aeu_mask;
        u32 nig_mask = 0;
+       u32 reg_addr;
 
        if (bp->attn_state & asserted)
                BNX2X_ERR("IGU ERROR\n");
@@ -1943,9 +3141,15 @@ static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
 
                        /* save nig interrupt mask */
                        nig_mask = REG_RD(bp, nig_int_mask_addr);
-                       REG_WR(bp, nig_int_mask_addr, 0);
 
-                       bnx2x_link_attn(bp);
+                       /* If nig_mask is not set, no need to call the update
+                        * function.
+                        */
+                       if (nig_mask) {
+                               REG_WR(bp, nig_int_mask_addr, 0);
+
+                               bnx2x_link_attn(bp);
+                       }
 
                        /* handle unicore attn? */
                }
@@ -1991,9 +3195,15 @@ static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
 
        } /* if hardwired */
 
-       DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
-          asserted, hc_addr);
-       REG_WR(bp, hc_addr, asserted);
+       if (bp->common.int_block == INT_BLOCK_HC)
+               reg_addr = (HC_REG_COMMAND_REG + port*32 +
+                           COMMAND_REG_ATTN_BITS_SET);
+       else
+               reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
+
+       DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
+          (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
+       REG_WR(bp, reg_addr, asserted);
 
        /* now set back the mask */
        if (asserted & ATTN_NIG_FOR_FUNC) {
@@ -2044,8 +3254,7 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
                bnx2x_fan_failure(bp);
        }
 
-       if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
-                   AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
+       if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
                bnx2x_acquire_phy_lock(bp);
                bnx2x_handle_module_detect_int(&bp->link_params);
                bnx2x_release_phy_lock(bp);
@@ -2108,12 +3317,16 @@ static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
        }
 
        if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
-
                val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
-               BNX2X_ERR("PXP hw attention 0x%x\n", val);
+               BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
                /* RQ_USDMDP_FIFO_OVERFLOW */
                if (val & 0x18000)
                        BNX2X_ERR("FATAL error from PXP\n");
+
+               if (!CHIP_IS_E1x(bp)) {
+                       val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
+                       BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
+               }
        }
 
        if (attn & HW_INTERRUT_ASSERT_SET_2) {
@@ -2144,16 +3357,41 @@ static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
                        int func = BP_FUNC(bp);
 
                        REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
-                       bp->mf_config = SHMEM_RD(bp,
-                                          mf_cfg.func_mf_config[func].config);
-                       val = SHMEM_RD(bp, func_mb[func].drv_status);
+                       bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
+                                       func_mf_config[BP_ABS_FUNC(bp)].config);
+                       val = SHMEM_RD(bp,
+                                      func_mb[BP_FW_MB_IDX(bp)].drv_status);
                        if (val & DRV_STATUS_DCC_EVENT_MASK)
                                bnx2x_dcc_event(bp,
                                            (val & DRV_STATUS_DCC_EVENT_MASK));
-                       bnx2x__link_status_update(bp);
+
+                       if (val & DRV_STATUS_SET_MF_BW)
+                               bnx2x_set_mf_bw(bp);
+
                        if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
                                bnx2x_pmf_update(bp);
 
+                       if (bp->port.pmf &&
+                           (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
+                               bp->dcbx_enabled > 0)
+                               /* start dcbx state machine */
+                               bnx2x_dcbx_set_params(bp,
+                                       BNX2X_DCBX_STATE_NEG_RECEIVED);
+                       if (bp->link_vars.periodic_flags &
+                           PERIODIC_FLAGS_LINK_EVENT) {
+                               /*  sync with link */
+                               bnx2x_acquire_phy_lock(bp);
+                               bp->link_vars.periodic_flags &=
+                                       ~PERIODIC_FLAGS_LINK_EVENT;
+                               bnx2x_release_phy_lock(bp);
+                               if (IS_MF(bp))
+                                       bnx2x_link_sync_notify(bp);
+                               bnx2x_link_report(bp);
+                       }
+                       /* Always call it here: bnx2x_link_report() will
+                        * prevent the link indication duplication.
+                        */
+                       bnx2x__link_status_update(bp);
                } else if (attn & BNX2X_MC_ASSERT_BITS) {
 
                        BNX2X_ERR("MC assert!\n");
@@ -2176,85 +3414,198 @@ static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
        if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
                BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
                if (attn & BNX2X_GRC_TIMEOUT) {
-                       val = CHIP_IS_E1H(bp) ?
-                               REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN) : 0;
+                       val = CHIP_IS_E1(bp) ? 0 :
+                                       REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
                        BNX2X_ERR("GRC time-out 0x%08x\n", val);
                }
                if (attn & BNX2X_GRC_RSV) {
-                       val = CHIP_IS_E1H(bp) ?
-                               REG_RD(bp, MISC_REG_GRC_RSV_ATTN) : 0;
+                       val = CHIP_IS_E1(bp) ? 0 :
+                                       REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
                        BNX2X_ERR("GRC reserved 0x%08x\n", val);
                }
                REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
        }
 }
 
-#define BNX2X_MISC_GEN_REG      MISC_REG_GENERIC_POR_1
-#define LOAD_COUNTER_BITS      16 /* Number of bits for load counter */
-#define LOAD_COUNTER_MASK      (((u32)0x1 << LOAD_COUNTER_BITS) - 1)
-#define RESET_DONE_FLAG_MASK   (~LOAD_COUNTER_MASK)
-#define RESET_DONE_FLAG_SHIFT  LOAD_COUNTER_BITS
-#define CHIP_PARITY_SUPPORTED(bp)   (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp))
 /*
+ * Bits map:
+ * 0-7   - Engine0 load counter.
+ * 8-15  - Engine1 load counter.
+ * 16    - Engine0 RESET_IN_PROGRESS bit.
+ * 17    - Engine1 RESET_IN_PROGRESS bit.
+ * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
+ *         on the engine
+ * 19    - Engine1 ONE_IS_LOADED.
+ * 20    - Chip reset flow bit. When set none-leader must wait for both engines
+ *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
+ *         just the one belonging to its engine).
+ *
+ */
+#define BNX2X_RECOVERY_GLOB_REG                MISC_REG_GENERIC_POR_1
+
+#define BNX2X_PATH0_LOAD_CNT_MASK      0x000000ff
+#define BNX2X_PATH0_LOAD_CNT_SHIFT     0
+#define BNX2X_PATH1_LOAD_CNT_MASK      0x0000ff00
+#define BNX2X_PATH1_LOAD_CNT_SHIFT     8
+#define BNX2X_PATH0_RST_IN_PROG_BIT    0x00010000
+#define BNX2X_PATH1_RST_IN_PROG_BIT    0x00020000
+#define BNX2X_GLOBAL_RESET_BIT         0x00040000
+
+/*
+ * Set the GLOBAL_RESET bit.
+ *
+ * Should be run under rtnl lock
+ */
+void bnx2x_set_reset_global(struct bnx2x *bp)
+{
+       u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
+
+       REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
+       barrier();
+       mmiowb();
+}
+
+/*
+ * Clear the GLOBAL_RESET bit.
+ *
+ * Should be run under rtnl lock
+ */
+static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
+{
+       u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
+
+       REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
+       barrier();
+       mmiowb();
+}
+
+/*
+ * Checks the GLOBAL_RESET bit.
+ *
  * should be run under rtnl lock
  */
+static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
+{
+       u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
+
+       DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
+       return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
+}
+
+/*
+ * Clear RESET_IN_PROGRESS bit for the current engine.
+ *
+ * Should be run under rtnl lock
+ */
 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
 {
-       u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
-       val &= ~(1 << RESET_DONE_FLAG_SHIFT);
-       REG_WR(bp, BNX2X_MISC_GEN_REG, val);
+       u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
+       u32 bit = BP_PATH(bp) ?
+               BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
+
+       /* Clear the bit */
+       val &= ~bit;
+       REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
        barrier();
        mmiowb();
 }
 
 /*
+ * Set RESET_IN_PROGRESS for the current engine.
+ *
  * should be run under rtnl lock
  */
-static inline void bnx2x_set_reset_in_progress(struct bnx2x *bp)
+void bnx2x_set_reset_in_progress(struct bnx2x *bp)
 {
-       u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
-       val |= (1 << 16);
-       REG_WR(bp, BNX2X_MISC_GEN_REG, val);
+       u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
+       u32 bit = BP_PATH(bp) ?
+               BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
+
+       /* Set the bit */
+       val |= bit;
+       REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
        barrier();
        mmiowb();
 }
 
 /*
+ * Checks the RESET_IN_PROGRESS bit for the given engine.
  * should be run under rtnl lock
  */
-bool bnx2x_reset_is_done(struct bnx2x *bp)
+bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
 {
-       u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
-       DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
-       return (val & RESET_DONE_FLAG_MASK) ? false : true;
+       u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
+       u32 bit = engine ?
+               BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
+
+       /* return false if bit is set */
+       return (val & bit) ? false : true;
 }
 
 /*
+ * Increment the load counter for the current engine.
+ *
  * should be run under rtnl lock
  */
-inline void bnx2x_inc_load_cnt(struct bnx2x *bp)
+void bnx2x_inc_load_cnt(struct bnx2x *bp)
 {
-       u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
+       u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
+       u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
+                            BNX2X_PATH0_LOAD_CNT_MASK;
+       u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
+                            BNX2X_PATH0_LOAD_CNT_SHIFT;
 
        DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
 
-       val1 = ((val & LOAD_COUNTER_MASK) + 1) & LOAD_COUNTER_MASK;
-       REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
+       /* get the current counter value */
+       val1 = (val & mask) >> shift;
+
+       /* increment... */
+       val1++;
+
+       /* clear the old value */
+       val &= ~mask;
+
+       /* set the new one */
+       val |= ((val1 << shift) & mask);
+
+       REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
        barrier();
        mmiowb();
 }
 
-/*
- * should be run under rtnl lock
+/**
+ * bnx2x_dec_load_cnt - decrement the load counter
+ *
+ * @bp:                driver handle
+ *
+ * Should be run under rtnl lock.
+ * Decrements the load counter for the current engine. Returns
+ * the new counter value.
  */
 u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
 {
-       u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
+       u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
+       u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
+                            BNX2X_PATH0_LOAD_CNT_MASK;
+       u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
+                            BNX2X_PATH0_LOAD_CNT_SHIFT;
 
        DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
 
-       val1 = ((val & LOAD_COUNTER_MASK) - 1) & LOAD_COUNTER_MASK;
-       REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
+       /* get the current counter value */
+       val1 = (val & mask) >> shift;
+
+       /* decrement... */
+       val1--;
+
+       /* clear the old value */
+       val &= ~mask;
+
+       /* set the new one */
+       val |= ((val1 << shift) & mask);
+
+       REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
        barrier();
        mmiowb();
 
@@ -2262,17 +3613,39 @@ u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
 }
 
 /*
+ * Read the load counter for the current engine.
+ *
  * should be run under rtnl lock
  */
-static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp)
+static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
 {
-       return REG_RD(bp, BNX2X_MISC_GEN_REG) & LOAD_COUNTER_MASK;
+       u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
+                            BNX2X_PATH0_LOAD_CNT_MASK);
+       u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
+                            BNX2X_PATH0_LOAD_CNT_SHIFT);
+       u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
+
+       DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
+
+       val = (val & mask) >> shift;
+
+       DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
+
+       return val;
 }
 
+/*
+ * Reset the load counter for the current engine.
+ *
+ * should be run under rtnl lock
+ */
 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
 {
-       u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
-       REG_WR(bp, BNX2X_MISC_GEN_REG, val & (~LOAD_COUNTER_MASK));
+       u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
+       u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
+                            BNX2X_PATH0_LOAD_CNT_MASK);
+
+       REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
 }
 
 static inline void _print_next_block(int idx, const char *blk)
@@ -2282,7 +3655,8 @@ static inline void _print_next_block(int idx, const char *blk)
        pr_cont("%s", blk);
 }
 
-static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num)
+static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
+                                                 bool print)
 {
        int i = 0;
        u32 cur_bit = 0;
@@ -2291,19 +3665,33 @@ static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num)
                if (sig & cur_bit) {
                        switch (cur_bit) {
                        case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
-                               _print_next_block(par_num++, "BRB");
+                               if (print)
+                                       _print_next_block(par_num++, "BRB");
                                break;
                        case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
-                               _print_next_block(par_num++, "PARSER");
+                               if (print)
+                                       _print_next_block(par_num++, "PARSER");
                                break;
                        case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
-                               _print_next_block(par_num++, "TSDM");
+                               if (print)
+                                       _print_next_block(par_num++, "TSDM");
                                break;
                        case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
-                               _print_next_block(par_num++, "SEARCHER");
+                               if (print)
+                                       _print_next_block(par_num++,
+                                                         "SEARCHER");
+                               break;
+                       case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
+                               if (print)
+                                       _print_next_block(par_num++, "TCM");
                                break;
                        case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
-                               _print_next_block(par_num++, "TSEMI");
+                               if (print)
+                                       _print_next_block(par_num++, "TSEMI");
+                               break;
+                       case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
+                               if (print)
+                                       _print_next_block(par_num++, "XPB");
                                break;
                        }
 
@@ -2315,7 +3703,8 @@ static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num)
        return par_num;
 }
 
-static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num)
+static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
+                                                 bool *global, bool print)
 {
        int i = 0;
        u32 cur_bit = 0;
@@ -2323,38 +3712,64 @@ static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num)
                cur_bit = ((u32)0x1 << i);
                if (sig & cur_bit) {
                        switch (cur_bit) {
-                       case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
-                               _print_next_block(par_num++, "PBCLIENT");
+                       case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
+                               if (print)
+                                       _print_next_block(par_num++, "PBF");
                                break;
                        case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
-                               _print_next_block(par_num++, "QM");
+                               if (print)
+                                       _print_next_block(par_num++, "QM");
+                               break;
+                       case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
+                               if (print)
+                                       _print_next_block(par_num++, "TM");
                                break;
                        case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
-                               _print_next_block(par_num++, "XSDM");
+                               if (print)
+                                       _print_next_block(par_num++, "XSDM");
+                               break;
+                       case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
+                               if (print)
+                                       _print_next_block(par_num++, "XCM");
                                break;
                        case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
-                               _print_next_block(par_num++, "XSEMI");
+                               if (print)
+                                       _print_next_block(par_num++, "XSEMI");
                                break;
                        case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
-                               _print_next_block(par_num++, "DOORBELLQ");
+                               if (print)
+                                       _print_next_block(par_num++,
+                                                         "DOORBELLQ");
+                               break;
+                       case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
+                               if (print)
+                                       _print_next_block(par_num++, "NIG");
                                break;
                        case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
-                               _print_next_block(par_num++, "VAUX PCI CORE");
+                               if (print)
+                                       _print_next_block(par_num++,
+                                                         "VAUX PCI CORE");
+                               *global = true;
                                break;
                        case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
-                               _print_next_block(par_num++, "DEBUG");
+                               if (print)
+                                       _print_next_block(par_num++, "DEBUG");
                                break;
                        case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
-                               _print_next_block(par_num++, "USDM");
+                               if (print)
+                                       _print_next_block(par_num++, "USDM");
                                break;
                        case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
-                               _print_next_block(par_num++, "USEMI");
+                               if (print)
+                                       _print_next_block(par_num++, "USEMI");
                                break;
                        case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
-                               _print_next_block(par_num++, "UPB");
+                               if (print)
+                                       _print_next_block(par_num++, "UPB");
                                break;
                        case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
-                               _print_next_block(par_num++, "CSDM");
+                               if (print)
+                                       _print_next_block(par_num++, "CSDM");
                                break;
                        }
 
@@ -2366,7 +3781,8 @@ static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num)
        return par_num;
 }
 
-static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num)
+static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
+                                                 bool print)
 {
        int i = 0;
        u32 cur_bit = 0;
@@ -2375,26 +3791,37 @@ static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num)
                if (sig & cur_bit) {
                        switch (cur_bit) {
                        case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
-                               _print_next_block(par_num++, "CSEMI");
+                               if (print)
+                                       _print_next_block(par_num++, "CSEMI");
                                break;
                        case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
-                               _print_next_block(par_num++, "PXP");
+                               if (print)
+                                       _print_next_block(par_num++, "PXP");
                                break;
                        case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
-                               _print_next_block(par_num++,
+                               if (print)
+                                       _print_next_block(par_num++,
                                        "PXPPCICLOCKCLIENT");
                                break;
                        case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
-                               _print_next_block(par_num++, "CFC");
+                               if (print)
+                                       _print_next_block(par_num++, "CFC");
                                break;
                        case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
-                               _print_next_block(par_num++, "CDU");
+                               if (print)
+                                       _print_next_block(par_num++, "CDU");
+                               break;
+                       case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
+                               if (print)
+                                       _print_next_block(par_num++, "DMAE");
                                break;
                        case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
-                               _print_next_block(par_num++, "IGU");
+                               if (print)
+                                       _print_next_block(par_num++, "IGU");
                                break;
                        case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
-                               _print_next_block(par_num++, "MISC");
+                               if (print)
+                                       _print_next_block(par_num++, "MISC");
                                break;
                        }
 
@@ -2406,7 +3833,8 @@ static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num)
        return par_num;
 }
 
-static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num)
+static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
+                                                 bool *global, bool print)
 {
        int i = 0;
        u32 cur_bit = 0;
@@ -2415,16 +3843,27 @@ static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num)
                if (sig & cur_bit) {
                        switch (cur_bit) {
                        case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
-                               _print_next_block(par_num++, "MCP ROM");
+                               if (print)
+                                       _print_next_block(par_num++, "MCP ROM");
+                               *global = true;
                                break;
                        case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
-                               _print_next_block(par_num++, "MCP UMP RX");
+                               if (print)
+                                       _print_next_block(par_num++,
+                                                         "MCP UMP RX");
+                               *global = true;
                                break;
                        case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
-                               _print_next_block(par_num++, "MCP UMP TX");
+                               if (print)
+                                       _print_next_block(par_num++,
+                                                         "MCP UMP TX");
+                               *global = true;
                                break;
                        case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
-                               _print_next_block(par_num++, "MCP SCPAD");
+                               if (print)
+                                       _print_next_block(par_num++,
+                                                         "MCP SCPAD");
+                               *global = true;
                                break;
                        }
 
@@ -2436,8 +3875,8 @@ static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num)
        return par_num;
 }
 
-static inline bool bnx2x_parity_attn(struct bnx2x *bp, u32 sig0, u32 sig1,
-                                    u32 sig2, u32 sig3)
+static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
+                                    u32 sig0, u32 sig1, u32 sig2, u32 sig3)
 {
        if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
            (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
@@ -2449,23 +3888,32 @@ static inline bool bnx2x_parity_attn(struct bnx2x *bp, u32 sig0, u32 sig1,
                          sig1 & HW_PRTY_ASSERT_SET_1,
                          sig2 & HW_PRTY_ASSERT_SET_2,
                          sig3 & HW_PRTY_ASSERT_SET_3);
-               printk(KERN_ERR"%s: Parity errors detected in blocks: ",
-                      bp->dev->name);
-               par_num = bnx2x_print_blocks_with_parity0(
-                       sig0 & HW_PRTY_ASSERT_SET_0, par_num);
-               par_num = bnx2x_print_blocks_with_parity1(
-                       sig1 & HW_PRTY_ASSERT_SET_1, par_num);
-               par_num = bnx2x_print_blocks_with_parity2(
-                       sig2 & HW_PRTY_ASSERT_SET_2, par_num);
-               par_num = bnx2x_print_blocks_with_parity3(
-                       sig3 & HW_PRTY_ASSERT_SET_3, par_num);
-               printk("\n");
+               if (print)
+                       netdev_err(bp->dev,
+                                  "Parity errors detected in blocks: ");
+               par_num = bnx2x_check_blocks_with_parity0(
+                       sig0 & HW_PRTY_ASSERT_SET_0, par_num, print);
+               par_num = bnx2x_check_blocks_with_parity1(
+                       sig1 & HW_PRTY_ASSERT_SET_1, par_num, global, print);
+               par_num = bnx2x_check_blocks_with_parity2(
+                       sig2 & HW_PRTY_ASSERT_SET_2, par_num, print);
+               par_num = bnx2x_check_blocks_with_parity3(
+                       sig3 & HW_PRTY_ASSERT_SET_3, par_num, global, print);
+               if (print)
+                       pr_cont("\n");
                return true;
        } else
                return false;
 }
 
-bool bnx2x_chk_parity_attn(struct bnx2x *bp)
+/**
+ * bnx2x_chk_parity_attn - checks for parity attentions.
+ *
+ * @bp:                driver handle
+ * @global:    true if there was a global attention
+ * @print:     show parity attention in syslog
+ */
+bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
 {
        struct attn_route attn;
        int port = BP_PORT(bp);
@@ -2483,8 +3931,76 @@ bool bnx2x_chk_parity_attn(struct bnx2x *bp)
                MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
                             port*4);
 
-       return bnx2x_parity_attn(bp, attn.sig[0], attn.sig[1], attn.sig[2],
-                                       attn.sig[3]);
+       return bnx2x_parity_attn(bp, global, print, attn.sig[0], attn.sig[1],
+                                attn.sig[2], attn.sig[3]);
+}
+
+
+static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
+{
+       u32 val;
+       if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
+
+               val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
+               BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
+               if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
+                       BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
+                                 "ADDRESS_ERROR\n");
+               if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
+                       BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
+                                 "INCORRECT_RCV_BEHAVIOR\n");
+               if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
+                       BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
+                                 "WAS_ERROR_ATTN\n");
+               if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
+                       BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
+                                 "VF_LENGTH_VIOLATION_ATTN\n");
+               if (val &
+                   PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
+                       BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
+                                 "VF_GRC_SPACE_VIOLATION_ATTN\n");
+               if (val &
+                   PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
+                       BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
+                                 "VF_MSIX_BAR_VIOLATION_ATTN\n");
+               if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
+                       BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
+                                 "TCPL_ERROR_ATTN\n");
+               if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
+                       BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
+                                 "TCPL_IN_TWO_RCBS_ATTN\n");
+               if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
+                       BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
+                                 "CSSNOOP_FIFO_OVERFLOW\n");
+       }
+       if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
+               val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
+               BNX2X_ERR("ATC hw attention 0x%x\n", val);
+               if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
+                       BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
+               if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
+                       BNX2X_ERR("ATC_ATC_INT_STS_REG"
+                                 "_ATC_TCPL_TO_NOT_PEND\n");
+               if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
+                       BNX2X_ERR("ATC_ATC_INT_STS_REG_"
+                                 "ATC_GPA_MULTIPLE_HITS\n");
+               if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
+                       BNX2X_ERR("ATC_ATC_INT_STS_REG_"
+                                 "ATC_RCPL_TO_EMPTY_CNT\n");
+               if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
+                       BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
+               if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
+                       BNX2X_ERR("ATC_ATC_INT_STS_REG_"
+                                 "ATC_IREQ_LESS_THAN_STU\n");
+       }
+
+       if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
+                   AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
+               BNX2X_ERR("FATAL parity attention set4 0x%x\n",
+               (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
+                   AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
+       }
+
 }
 
 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
@@ -2495,21 +4011,25 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
        u32 reg_addr;
        u32 val;
        u32 aeu_mask;
+       bool global = false;
 
        /* need to take HW lock because MCP or other port might also
           try to handle this event */
        bnx2x_acquire_alr(bp);
 
-       if (bnx2x_chk_parity_attn(bp)) {
+       if (bnx2x_chk_parity_attn(bp, &global, true)) {
+#ifndef BNX2X_STOP_ON_ERROR
                bp->recovery_state = BNX2X_RECOVERY_INIT;
-               bnx2x_set_reset_in_progress(bp);
                schedule_delayed_work(&bp->reset_task, 0);
                /* Disable HW interrupts */
                bnx2x_int_disable(bp);
-               bnx2x_release_alr(bp);
                /* In case of parity errors don't handle attentions so that
                 * other function would "see" parity errors.
                 */
+#else
+               bnx2x_panic();
+#endif
+               bnx2x_release_alr(bp);
                return;
        }
 
@@ -2517,17 +4037,28 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
        attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
        attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
        attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
-       DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x\n",
-          attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3]);
+       if (!CHIP_IS_E1x(bp))
+               attn.sig[4] =
+                     REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
+       else
+               attn.sig[4] = 0;
+
+       DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
+          attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
 
        for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
                if (deasserted & (1 << index)) {
                        group_mask = &bp->attn_group[index];
 
-                       DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x\n",
-                          index, group_mask->sig[0], group_mask->sig[1],
-                          group_mask->sig[2], group_mask->sig[3]);
+                       DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
+                                        "%08x %08x %08x\n",
+                          index,
+                          group_mask->sig[0], group_mask->sig[1],
+                          group_mask->sig[2], group_mask->sig[3],
+                          group_mask->sig[4]);
 
+                       bnx2x_attn_int_deasserted4(bp,
+                                       attn.sig[4] & group_mask->sig[4]);
                        bnx2x_attn_int_deasserted3(bp,
                                        attn.sig[3] & group_mask->sig[3]);
                        bnx2x_attn_int_deasserted1(bp,
@@ -2541,11 +4072,15 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
 
        bnx2x_release_alr(bp);
 
-       reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_CLR);
+       if (bp->common.int_block == INT_BLOCK_HC)
+               reg_addr = (HC_REG_COMMAND_REG + port*32 +
+                           COMMAND_REG_ATTN_BITS_CLR);
+       else
+               reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
 
        val = ~deasserted;
-       DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
-          val, reg_addr);
+       DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
+          (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
        REG_WR(bp, reg_addr, val);
 
        if (~bp->attn_state & deasserted)
@@ -2598,17 +4133,316 @@ static void bnx2x_attn_int(struct bnx2x *bp)
                bnx2x_attn_int_deasserted(bp, deasserted);
 }
 
-static void bnx2x_sp_task(struct work_struct *work)
+void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
+                     u16 index, u8 op, u8 update)
 {
-       struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
-       u16 status;
+       u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
+
+       bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
+                            igu_addr);
+}
+
+static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
+{
+       /* No memory barriers */
+       storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
+       mmiowb(); /* keep prod updates ordered */
+}
+
+#ifdef BCM_CNIC
+static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
+                                     union event_ring_elem *elem)
+{
+       u8 err = elem->message.error;
+
+       if (!bp->cnic_eth_dev.starting_cid  ||
+           (cid < bp->cnic_eth_dev.starting_cid &&
+           cid != bp->cnic_eth_dev.iscsi_l2_cid))
+               return 1;
+
+       DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
+
+       if (unlikely(err)) {
+
+               BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
+                         cid);
+               bnx2x_panic_dump(bp);
+       }
+       bnx2x_cnic_cfc_comp(bp, cid, err);
+       return 0;
+}
+#endif
+
+static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
+{
+       struct bnx2x_mcast_ramrod_params rparam;
+       int rc;
+
+       memset(&rparam, 0, sizeof(rparam));
+
+       rparam.mcast_obj = &bp->mcast_obj;
+
+       netif_addr_lock_bh(bp->dev);
+
+       /* Clear pending state for the last command */
+       bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
+
+       /* If there are pending mcast commands - send them */
+       if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
+               rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
+               if (rc < 0)
+                       BNX2X_ERR("Failed to send pending mcast commands: %d\n",
+                                 rc);
+       }
 
-       /* Return here if interrupt is disabled */
-       if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
-               DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
+       netif_addr_unlock_bh(bp->dev);
+}
+
+static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
+                                                  union event_ring_elem *elem)
+{
+       unsigned long ramrod_flags = 0;
+       int rc = 0;
+       u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
+       struct bnx2x_vlan_mac_obj *vlan_mac_obj;
+
+       /* Always push next commands out, don't wait here */
+       __set_bit(RAMROD_CONT, &ramrod_flags);
+
+       switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
+       case BNX2X_FILTER_MAC_PENDING:
+#ifdef BCM_CNIC
+               if (cid == BNX2X_ISCSI_ETH_CID)
+                       vlan_mac_obj = &bp->iscsi_l2_mac_obj;
+               else
+#endif
+                       vlan_mac_obj = &bp->fp[cid].mac_obj;
+
+               break;
+               vlan_mac_obj = &bp->fp[cid].mac_obj;
+
+       case BNX2X_FILTER_MCAST_PENDING:
+               /* This is only relevant for 57710 where multicast MACs are
+                * configured as unicast MACs using the same ramrod.
+                */
+               bnx2x_handle_mcast_eqe(bp);
+               return;
+       default:
+               BNX2X_ERR("Unsupported classification command: %d\n",
+                         elem->message.data.eth_event.echo);
                return;
        }
 
+       rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
+
+       if (rc < 0)
+               BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
+       else if (rc > 0)
+               DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
+
+}
+
+#ifdef BCM_CNIC
+static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
+#endif
+
+static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
+{
+       netif_addr_lock_bh(bp->dev);
+
+       clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
+
+       /* Send rx_mode command again if was requested */
+       if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
+               bnx2x_set_storm_rx_mode(bp);
+#ifdef BCM_CNIC
+       else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
+                                   &bp->sp_state))
+               bnx2x_set_iscsi_eth_rx_mode(bp, true);
+       else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
+                                   &bp->sp_state))
+               bnx2x_set_iscsi_eth_rx_mode(bp, false);
+#endif
+
+       netif_addr_unlock_bh(bp->dev);
+}
+
+static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
+       struct bnx2x *bp, u32 cid)
+{
+#ifdef BCM_CNIC
+       if (cid == BNX2X_FCOE_ETH_CID)
+               return &bnx2x_fcoe(bp, q_obj);
+       else
+#endif
+               return &bnx2x_fp(bp, cid, q_obj);
+}
+
+static void bnx2x_eq_int(struct bnx2x *bp)
+{
+       u16 hw_cons, sw_cons, sw_prod;
+       union event_ring_elem *elem;
+       u32 cid;
+       u8 opcode;
+       int spqe_cnt = 0;
+       struct bnx2x_queue_sp_obj *q_obj;
+       struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
+       struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
+
+       hw_cons = le16_to_cpu(*bp->eq_cons_sb);
+
+       /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
+        * when we get the the next-page we nned to adjust so the loop
+        * condition below will be met. The next element is the size of a
+        * regular element and hence incrementing by 1
+        */
+       if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
+               hw_cons++;
+
+       /* This function may never run in parallel with itself for a
+        * specific bp, thus there is no need in "paired" read memory
+        * barrier here.
+        */
+       sw_cons = bp->eq_cons;
+       sw_prod = bp->eq_prod;
+
+       DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->cq_spq_left %u\n",
+                       hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
+
+       for (; sw_cons != hw_cons;
+             sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
+
+
+               elem = &bp->eq_ring[EQ_DESC(sw_cons)];
+
+               cid = SW_CID(elem->message.data.cfc_del_event.cid);
+               opcode = elem->message.opcode;
+
+
+               /* handle eq element */
+               switch (opcode) {
+               case EVENT_RING_OPCODE_STAT_QUERY:
+                       DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
+                          bp->stats_comp++);
+                       /* nothing to do with stats comp */
+                       continue;
+
+               case EVENT_RING_OPCODE_CFC_DEL:
+                       /* handle according to cid range */
+                       /*
+                        * we may want to verify here that the bp state is
+                        * HALTING
+                        */
+                       DP(NETIF_MSG_IFDOWN,
+                          "got delete ramrod for MULTI[%d]\n", cid);
+#ifdef BCM_CNIC
+                       if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
+                               goto next_spqe;
+#endif
+                       q_obj = bnx2x_cid_to_q_obj(bp, cid);
+
+                       if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
+                               break;
+
+
+
+                       goto next_spqe;
+
+               case EVENT_RING_OPCODE_STOP_TRAFFIC:
+                       DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
+                       bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
+                       goto next_spqe;
+
+               case EVENT_RING_OPCODE_START_TRAFFIC:
+                       DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
+                       bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
+                       goto next_spqe;
+               case EVENT_RING_OPCODE_FUNCTION_START:
+                       DP(NETIF_MSG_IFUP, "got FUNC_START ramrod\n");
+                       if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
+                               break;
+
+                       goto next_spqe;
+
+               case EVENT_RING_OPCODE_FUNCTION_STOP:
+                       DP(NETIF_MSG_IFDOWN, "got FUNC_STOP ramrod\n");
+                       if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
+                               break;
+
+                       goto next_spqe;
+               }
+
+               switch (opcode | bp->state) {
+               case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
+                     BNX2X_STATE_OPEN):
+               case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
+                     BNX2X_STATE_OPENING_WAIT4_PORT):
+                       cid = elem->message.data.eth_event.echo &
+                               BNX2X_SWCID_MASK;
+                       DP(NETIF_MSG_IFUP, "got RSS_UPDATE ramrod. CID %d\n",
+                          cid);
+                       rss_raw->clear_pending(rss_raw);
+                       break;
+
+               case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
+               case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
+               case (EVENT_RING_OPCODE_SET_MAC |
+                     BNX2X_STATE_CLOSING_WAIT4_HALT):
+               case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
+                     BNX2X_STATE_OPEN):
+               case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
+                     BNX2X_STATE_DIAG):
+               case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
+                     BNX2X_STATE_CLOSING_WAIT4_HALT):
+                       DP(NETIF_MSG_IFUP, "got (un)set mac ramrod\n");
+                       bnx2x_handle_classification_eqe(bp, elem);
+                       break;
+
+               case (EVENT_RING_OPCODE_MULTICAST_RULES |
+                     BNX2X_STATE_OPEN):
+               case (EVENT_RING_OPCODE_MULTICAST_RULES |
+                     BNX2X_STATE_DIAG):
+               case (EVENT_RING_OPCODE_MULTICAST_RULES |
+                     BNX2X_STATE_CLOSING_WAIT4_HALT):
+                       DP(NETIF_MSG_IFUP, "got mcast ramrod\n");
+                       bnx2x_handle_mcast_eqe(bp);
+                       break;
+
+               case (EVENT_RING_OPCODE_FILTERS_RULES |
+                     BNX2X_STATE_OPEN):
+               case (EVENT_RING_OPCODE_FILTERS_RULES |
+                     BNX2X_STATE_DIAG):
+               case (EVENT_RING_OPCODE_FILTERS_RULES |
+                     BNX2X_STATE_CLOSING_WAIT4_HALT):
+                       DP(NETIF_MSG_IFUP, "got rx_mode ramrod\n");
+                       bnx2x_handle_rx_mode_eqe(bp);
+                       break;
+               default:
+                       /* unknown event log error and continue */
+                       BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
+                                 elem->message.opcode, bp->state);
+               }
+next_spqe:
+               spqe_cnt++;
+       } /* for */
+
+       smp_mb__before_atomic_inc();
+       atomic_add(spqe_cnt, &bp->eq_spq_left);
+
+       bp->eq_cons = sw_cons;
+       bp->eq_prod = sw_prod;
+       /* Make sure that above mem writes were issued towards the memory */
+       smp_wmb();
+
+       /* update producer */
+       bnx2x_update_eq_prod(bp, bp->eq_prod);
+}
+
+static void bnx2x_sp_task(struct work_struct *work)
+{
+       struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
+       u16 status;
+
        status = bnx2x_update_dsb_idx(bp);
 /*     if (status == 0)                                     */
 /*             BNX2X_ERR("spurious slowpath interrupt!\n"); */
@@ -2616,31 +4450,35 @@ static void bnx2x_sp_task(struct work_struct *work)
        DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
 
        /* HW attentions */
-       if (status & 0x1) {
+       if (status & BNX2X_DEF_SB_ATT_IDX) {
                bnx2x_attn_int(bp);
-               status &= ~0x1;
+               status &= ~BNX2X_DEF_SB_ATT_IDX;
        }
 
-       /* CStorm events: STAT_QUERY */
-       if (status & 0x2) {
-               DP(BNX2X_MSG_SP, "CStorm events: STAT_QUERY\n");
-               status &= ~0x2;
+       /* SP events: STAT_QUERY and others */
+       if (status & BNX2X_DEF_SB_IDX) {
+#ifdef BCM_CNIC
+               struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
+
+               if ((!NO_FCOE(bp)) &&
+                       (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)))
+                       napi_schedule(&bnx2x_fcoe(bp, napi));
+#endif
+               /* Handle EQ completions */
+               bnx2x_eq_int(bp);
+
+               bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
+                       le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
+
+               status &= ~BNX2X_DEF_SB_IDX;
        }
 
        if (unlikely(status))
                DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
                   status);
 
-       bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, le16_to_cpu(bp->def_att_idx),
-                    IGU_INT_NOP, 1);
-       bnx2x_ack_sb(bp, DEF_SB_ID, USTORM_ID, le16_to_cpu(bp->def_u_idx),
-                    IGU_INT_NOP, 1);
-       bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, le16_to_cpu(bp->def_c_idx),
-                    IGU_INT_NOP, 1);
-       bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, le16_to_cpu(bp->def_x_idx),
-                    IGU_INT_NOP, 1);
-       bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx),
-                    IGU_INT_ENABLE, 1);
+       bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
+            le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
 }
 
 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
@@ -2648,13 +4486,8 @@ irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
        struct net_device *dev = dev_instance;
        struct bnx2x *bp = netdev_priv(dev);
 
-       /* Return here if interrupt is disabled */
-       if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
-               DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
-               return IRQ_HANDLED;
-       }
-
-       bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, 0, IGU_INT_DISABLE, 0);
+       bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
+                    IGU_INT_DISABLE, 0);
 
 #ifdef BNX2X_STOP_ON_ERROR
        if (unlikely(bp->panic))
@@ -2679,6 +4512,14 @@ irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
 
 /* end of slow path */
 
+
+void bnx2x_drv_pulse(struct bnx2x *bp)
+{
+       SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
+                bp->fw_drv_pulse_wr_seq);
+}
+
+
 static void bnx2x_timer(unsigned long data)
 {
        struct bnx2x *bp = (struct bnx2x *) data;
@@ -2686,19 +4527,15 @@ static void bnx2x_timer(unsigned long data)
        if (!netif_running(bp->dev))
                return;
 
-       if (atomic_read(&bp->intr_sem) != 0)
-               goto timer_restart;
-
        if (poll) {
                struct bnx2x_fastpath *fp = &bp->fp[0];
-               int rc;
 
                bnx2x_tx_int(fp);
-               rc = bnx2x_rx_int(fp, 1000);
+               bnx2x_rx_int(fp, 1000);
        }
 
        if (!BP_NOMCP(bp)) {
-               int func = BP_FUNC(bp);
+               int mb_idx = BP_FW_MB_IDX(bp);
                u32 drv_pulse;
                u32 mcp_pulse;
 
@@ -2706,9 +4543,9 @@ static void bnx2x_timer(unsigned long data)
                bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
                /* TBD - add SYSTEM_TIME */
                drv_pulse = bp->fw_drv_pulse_wr_seq;
-               SHMEM_WR(bp, func_mb[func].drv_pulse_mb, drv_pulse);
+               bnx2x_drv_pulse(bp);
 
-               mcp_pulse = (SHMEM_RD(bp, func_mb[func].mcp_pulse_mb) &
+               mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
                             MCP_PULSE_SEQ_MASK);
                /* The delta between driver pulse and mcp response
                 * should be 1 (before mcp response) or 0 (after mcp response)
@@ -2724,7 +4561,6 @@ static void bnx2x_timer(unsigned long data)
        if (bp->state == BNX2X_STATE_OPEN)
                bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
 
-timer_restart:
        mod_timer(&bp->timer, jiffies + bp->current_interval);
 }
 
@@ -2736,687 +4572,459 @@ timer_restart:
  * nic init service functions
  */
 
-static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
+static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
 {
-       int port = BP_PORT(bp);
+       u32 i;
+       if (!(len%4) && !(addr%4))
+               for (i = 0; i < len; i += 4)
+                       REG_WR(bp, addr + i, fill);
+       else
+               for (i = 0; i < len; i++)
+                       REG_WR8(bp, addr + i, fill);
 
-       /* "CSTORM" */
-       bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
-                       CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, sb_id), 0,
-                       CSTORM_SB_STATUS_BLOCK_U_SIZE / 4);
-       bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
-                       CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id), 0,
-                       CSTORM_SB_STATUS_BLOCK_C_SIZE / 4);
 }
 
-void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
-                         dma_addr_t mapping, int sb_id)
+/* helper: writes FP SP data to FW - data_size in dwords */
+static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
+                                      int fw_sb_id,
+                                      u32 *sb_data_p,
+                                      u32 data_size)
 {
-       int port = BP_PORT(bp);
-       int func = BP_FUNC(bp);
        int index;
-       u64 section;
+       for (index = 0; index < data_size; index++)
+               REG_WR(bp, BAR_CSTRORM_INTMEM +
+                       CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
+                       sizeof(u32)*index,
+                       *(sb_data_p + index));
+}
+
+static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
+{
+       u32 *sb_data_p;
+       u32 data_size = 0;
+       struct hc_status_block_data_e2 sb_data_e2;
+       struct hc_status_block_data_e1x sb_data_e1x;
+
+       /* disable the function first */
+       if (!CHIP_IS_E1x(bp)) {
+               memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
+               sb_data_e2.common.state = SB_DISABLED;
+               sb_data_e2.common.p_func.vf_valid = false;
+               sb_data_p = (u32 *)&sb_data_e2;
+               data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
+       } else {
+               memset(&sb_data_e1x, 0,
+                      sizeof(struct hc_status_block_data_e1x));
+               sb_data_e1x.common.state = SB_DISABLED;
+               sb_data_e1x.common.p_func.vf_valid = false;
+               sb_data_p = (u32 *)&sb_data_e1x;
+               data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
+       }
+       bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
 
-       /* USTORM */
-       section = ((u64)mapping) + offsetof(struct host_status_block,
-                                           u_status_block);
-       sb->u_status_block.status_block_id = sb_id;
-
-       REG_WR(bp, BAR_CSTRORM_INTMEM +
-              CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, sb_id), U64_LO(section));
-       REG_WR(bp, BAR_CSTRORM_INTMEM +
-              ((CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, sb_id)) + 4),
-              U64_HI(section));
-       REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_USB_FUNC_OFF +
-               CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, sb_id), func);
-
-       for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
-               REG_WR16(bp, BAR_CSTRORM_INTMEM +
-                        CSTORM_SB_HC_DISABLE_U_OFFSET(port, sb_id, index), 1);
+       bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
+                       CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
+                       CSTORM_STATUS_BLOCK_SIZE);
+       bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
+                       CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
+                       CSTORM_SYNC_BLOCK_SIZE);
+}
 
-       /* CSTORM */
-       section = ((u64)mapping) + offsetof(struct host_status_block,
-                                           c_status_block);
-       sb->c_status_block.status_block_id = sb_id;
+/* helper:  writes SP SB data to FW */
+static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
+               struct hc_sp_status_block_data *sp_sb_data)
+{
+       int func = BP_FUNC(bp);
+       int i;
+       for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
+               REG_WR(bp, BAR_CSTRORM_INTMEM +
+                       CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
+                       i*sizeof(u32),
+                       *((u32 *)sp_sb_data + i));
+}
+
+static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
+{
+       int func = BP_FUNC(bp);
+       struct hc_sp_status_block_data sp_sb_data;
+       memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
+
+       sp_sb_data.state = SB_DISABLED;
+       sp_sb_data.p_func.vf_valid = false;
 
-       REG_WR(bp, BAR_CSTRORM_INTMEM +
-              CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, sb_id), U64_LO(section));
-       REG_WR(bp, BAR_CSTRORM_INTMEM +
-              ((CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, sb_id)) + 4),
-              U64_HI(section));
-       REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_CSB_FUNC_OFF +
-               CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id), func);
+       bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
 
-       for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++)
-               REG_WR16(bp, BAR_CSTRORM_INTMEM +
-                        CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id, index), 1);
+       bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
+                       CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
+                       CSTORM_SP_STATUS_BLOCK_SIZE);
+       bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
+                       CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
+                       CSTORM_SP_SYNC_BLOCK_SIZE);
 
-       bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
 }
 
-static void bnx2x_zero_def_sb(struct bnx2x *bp)
+
+static inline
+void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
+                                          int igu_sb_id, int igu_seg_id)
 {
-       int func = BP_FUNC(bp);
+       hc_sm->igu_sb_id = igu_sb_id;
+       hc_sm->igu_seg_id = igu_seg_id;
+       hc_sm->timer_value = 0xFF;
+       hc_sm->time_to_expire = 0xFFFFFFFF;
+}
+
+static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
+                         u8 vf_valid, int fw_sb_id, int igu_sb_id)
+{
+       int igu_seg_id;
 
-       bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY +
-                       TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
-                       sizeof(struct tstorm_def_status_block)/4);
-       bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
-                       CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(func), 0,
-                       sizeof(struct cstorm_def_status_block_u)/4);
-       bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY +
-                       CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(func), 0,
-                       sizeof(struct cstorm_def_status_block_c)/4);
-       bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY +
-                       XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
-                       sizeof(struct xstorm_def_status_block)/4);
+       struct hc_status_block_data_e2 sb_data_e2;
+       struct hc_status_block_data_e1x sb_data_e1x;
+       struct hc_status_block_sm  *hc_sm_p;
+       int data_size;
+       u32 *sb_data_p;
+
+       if (CHIP_INT_MODE_IS_BC(bp))
+               igu_seg_id = HC_SEG_ACCESS_NORM;
+       else
+               igu_seg_id = IGU_SEG_ACCESS_NORM;
+
+       bnx2x_zero_fp_sb(bp, fw_sb_id);
+
+       if (!CHIP_IS_E1x(bp)) {
+               memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
+               sb_data_e2.common.state = SB_ENABLED;
+               sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
+               sb_data_e2.common.p_func.vf_id = vfid;
+               sb_data_e2.common.p_func.vf_valid = vf_valid;
+               sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
+               sb_data_e2.common.same_igu_sb_1b = true;
+               sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
+               sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
+               hc_sm_p = sb_data_e2.common.state_machine;
+               sb_data_p = (u32 *)&sb_data_e2;
+               data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
+       } else {
+               memset(&sb_data_e1x, 0,
+                      sizeof(struct hc_status_block_data_e1x));
+               sb_data_e1x.common.state = SB_ENABLED;
+               sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
+               sb_data_e1x.common.p_func.vf_id = 0xff;
+               sb_data_e1x.common.p_func.vf_valid = false;
+               sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
+               sb_data_e1x.common.same_igu_sb_1b = true;
+               sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
+               sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
+               hc_sm_p = sb_data_e1x.common.state_machine;
+               sb_data_p = (u32 *)&sb_data_e1x;
+               data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
+       }
+
+       bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
+                                      igu_sb_id, igu_seg_id);
+       bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
+                                      igu_sb_id, igu_seg_id);
+
+       DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
+
+       /* write indecies to HW */
+       bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
 }
 
-static void bnx2x_init_def_sb(struct bnx2x *bp,
-                             struct host_def_status_block *def_sb,
-                             dma_addr_t mapping, int sb_id)
+static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
+                                    u16 tx_usec, u16 rx_usec)
 {
+       bnx2x_update_coalesce_sb_index(bp, fw_sb_id, U_SB_ETH_RX_CQ_INDEX,
+                                   false, rx_usec);
+       bnx2x_update_coalesce_sb_index(bp, fw_sb_id, C_SB_ETH_TX_CQ_INDEX,
+                                   false, tx_usec);
+}
+
+static void bnx2x_init_def_sb(struct bnx2x *bp)
+{
+       struct host_sp_status_block *def_sb = bp->def_status_blk;
+       dma_addr_t mapping = bp->def_status_blk_mapping;
+       int igu_sp_sb_index;
+       int igu_seg_id;
        int port = BP_PORT(bp);
        int func = BP_FUNC(bp);
-       int index, val, reg_offset;
+       int reg_offset;
        u64 section;
+       int index;
+       struct hc_sp_status_block_data sp_sb_data;
+       memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
+
+       if (CHIP_INT_MODE_IS_BC(bp)) {
+               igu_sp_sb_index = DEF_SB_IGU_ID;
+               igu_seg_id = HC_SEG_ACCESS_DEF;
+       } else {
+               igu_sp_sb_index = bp->igu_dsb_id;
+               igu_seg_id = IGU_SEG_ACCESS_DEF;
+       }
 
        /* ATTN */
-       section = ((u64)mapping) + offsetof(struct host_def_status_block,
+       section = ((u64)mapping) + offsetof(struct host_sp_status_block,
                                            atten_status_block);
-       def_sb->atten_status_block.status_block_id = sb_id;
+       def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
 
        bp->attn_state = 0;
 
        reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
                             MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
-
        for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
-               bp->attn_group[index].sig[0] = REG_RD(bp,
-                                                    reg_offset + 0x10*index);
-               bp->attn_group[index].sig[1] = REG_RD(bp,
-                                              reg_offset + 0x4 + 0x10*index);
-               bp->attn_group[index].sig[2] = REG_RD(bp,
-                                              reg_offset + 0x8 + 0x10*index);
-               bp->attn_group[index].sig[3] = REG_RD(bp,
-                                              reg_offset + 0xc + 0x10*index);
+               int sindex;
+               /* take care of sig[0]..sig[4] */
+               for (sindex = 0; sindex < 4; sindex++)
+                       bp->attn_group[index].sig[sindex] =
+                          REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
+
+               if (!CHIP_IS_E1x(bp))
+                       /*
+                        * enable5 is separate from the rest of the registers,
+                        * and therefore the address skip is 4
+                        * and not 16 between the different groups
+                        */
+                       bp->attn_group[index].sig[4] = REG_RD(bp,
+                                       reg_offset + 0x10 + 0x4*index);
+               else
+                       bp->attn_group[index].sig[4] = 0;
        }
 
-       reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
-                            HC_REG_ATTN_MSG0_ADDR_L);
-
-       REG_WR(bp, reg_offset, U64_LO(section));
-       REG_WR(bp, reg_offset + 4, U64_HI(section));
-
-       reg_offset = (port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0);
-
-       val = REG_RD(bp, reg_offset);
-       val |= sb_id;
-       REG_WR(bp, reg_offset, val);
+       if (bp->common.int_block == INT_BLOCK_HC) {
+               reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
+                                    HC_REG_ATTN_MSG0_ADDR_L);
 
-       /* USTORM */
-       section = ((u64)mapping) + offsetof(struct host_def_status_block,
-                                           u_def_status_block);
-       def_sb->u_def_status_block.status_block_id = sb_id;
-
-       REG_WR(bp, BAR_CSTRORM_INTMEM +
-              CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(func), U64_LO(section));
-       REG_WR(bp, BAR_CSTRORM_INTMEM +
-              ((CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(func)) + 4),
-              U64_HI(section));
-       REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_USB_FUNC_OFF +
-               CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(func), func);
-
-       for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
-               REG_WR16(bp, BAR_CSTRORM_INTMEM +
-                        CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(func, index), 1);
-
-       /* CSTORM */
-       section = ((u64)mapping) + offsetof(struct host_def_status_block,
-                                           c_def_status_block);
-       def_sb->c_def_status_block.status_block_id = sb_id;
-
-       REG_WR(bp, BAR_CSTRORM_INTMEM +
-              CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(func), U64_LO(section));
-       REG_WR(bp, BAR_CSTRORM_INTMEM +
-              ((CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(func)) + 4),
-              U64_HI(section));
-       REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
-               CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(func), func);
-
-       for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
-               REG_WR16(bp, BAR_CSTRORM_INTMEM +
-                        CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(func, index), 1);
-
-       /* TSTORM */
-       section = ((u64)mapping) + offsetof(struct host_def_status_block,
-                                           t_def_status_block);
-       def_sb->t_def_status_block.status_block_id = sb_id;
-
-       REG_WR(bp, BAR_TSTRORM_INTMEM +
-              TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
-       REG_WR(bp, BAR_TSTRORM_INTMEM +
-              ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
-              U64_HI(section));
-       REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF +
-               TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
-
-       for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
-               REG_WR16(bp, BAR_TSTRORM_INTMEM +
-                        TSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
+               REG_WR(bp, reg_offset, U64_LO(section));
+               REG_WR(bp, reg_offset + 4, U64_HI(section));
+       } else if (!CHIP_IS_E1x(bp)) {
+               REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
+               REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
+       }
 
-       /* XSTORM */
-       section = ((u64)mapping) + offsetof(struct host_def_status_block,
-                                           x_def_status_block);
-       def_sb->x_def_status_block.status_block_id = sb_id;
+       section = ((u64)mapping) + offsetof(struct host_sp_status_block,
+                                           sp_sb);
 
-       REG_WR(bp, BAR_XSTRORM_INTMEM +
-              XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
-       REG_WR(bp, BAR_XSTRORM_INTMEM +
-              ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
-              U64_HI(section));
-       REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF +
-               XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
+       bnx2x_zero_sp_sb(bp);
 
-       for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
-               REG_WR16(bp, BAR_XSTRORM_INTMEM +
-                        XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
+       sp_sb_data.state                = SB_ENABLED;
+       sp_sb_data.host_sb_addr.lo      = U64_LO(section);
+       sp_sb_data.host_sb_addr.hi      = U64_HI(section);
+       sp_sb_data.igu_sb_id            = igu_sp_sb_index;
+       sp_sb_data.igu_seg_id           = igu_seg_id;
+       sp_sb_data.p_func.pf_id         = func;
+       sp_sb_data.p_func.vnic_id       = BP_VN(bp);
+       sp_sb_data.p_func.vf_id         = 0xff;
 
-       bp->stats_pending = 0;
-       bp->set_mac_pending = 0;
+       bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
 
-       bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
+       bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
 }
 
 void bnx2x_update_coalesce(struct bnx2x *bp)
 {
-       int port = BP_PORT(bp);
        int i;
 
-       for_each_queue(bp, i) {
-               int sb_id = bp->fp[i].sb_id;
-
-               /* HC_INDEX_U_ETH_RX_CQ_CONS */
-               REG_WR8(bp, BAR_CSTRORM_INTMEM +
-                       CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, sb_id,
-                                                     U_SB_ETH_RX_CQ_INDEX),
-                       bp->rx_ticks/(4 * BNX2X_BTR));
-               REG_WR16(bp, BAR_CSTRORM_INTMEM +
-                        CSTORM_SB_HC_DISABLE_U_OFFSET(port, sb_id,
-                                                      U_SB_ETH_RX_CQ_INDEX),
-                        (bp->rx_ticks/(4 * BNX2X_BTR)) ? 0 : 1);
-
-               /* HC_INDEX_C_ETH_TX_CQ_CONS */
-               REG_WR8(bp, BAR_CSTRORM_INTMEM +
-                       CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, sb_id,
-                                                     C_SB_ETH_TX_CQ_INDEX),
-                       bp->tx_ticks/(4 * BNX2X_BTR));
-               REG_WR16(bp, BAR_CSTRORM_INTMEM +
-                        CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id,
-                                                      C_SB_ETH_TX_CQ_INDEX),
-                        (bp->tx_ticks/(4 * BNX2X_BTR)) ? 0 : 1);
-       }
+       for_each_eth_queue(bp, i)
+               bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
+                                        bp->tx_ticks, bp->rx_ticks);
 }
 
 static void bnx2x_init_sp_ring(struct bnx2x *bp)
 {
-       int func = BP_FUNC(bp);
-
        spin_lock_init(&bp->spq_lock);
+       atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
 
-       bp->spq_left = MAX_SPQ_PENDING;
        bp->spq_prod_idx = 0;
        bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
        bp->spq_prod_bd = bp->spq;
        bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
-
-       REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func),
-              U64_LO(bp->spq_mapping));
-       REG_WR(bp,
-              XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func) + 4,
-              U64_HI(bp->spq_mapping));
-
-       REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(func),
-              bp->spq_prod_idx);
 }
 
-static void bnx2x_init_context(struct bnx2x *bp)
+static void bnx2x_init_eq_ring(struct bnx2x *bp)
 {
        int i;
+       for (i = 1; i <= NUM_EQ_PAGES; i++) {
+               union event_ring_elem *elem =
+                       &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
+
+               elem->next_page.addr.hi =
+                       cpu_to_le32(U64_HI(bp->eq_mapping +
+                                  BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
+               elem->next_page.addr.lo =
+                       cpu_to_le32(U64_LO(bp->eq_mapping +
+                                  BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
+       }
+       bp->eq_cons = 0;
+       bp->eq_prod = NUM_EQ_DESC;
+       bp->eq_cons_sb = BNX2X_EQ_INDEX;
+       /* we want a warning message before it gets rought... */
+       atomic_set(&bp->eq_spq_left,
+               min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
+}
+
+
+/* called with netif_addr_lock_bh() */
+void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
+                        unsigned long rx_mode_flags,
+                        unsigned long rx_accept_flags,
+                        unsigned long tx_accept_flags,
+                        unsigned long ramrod_flags)
+{
+       struct bnx2x_rx_mode_ramrod_params ramrod_param;
+       int rc;
 
-       /* Rx */
-       for_each_queue(bp, i) {
-               struct eth_context *context = bnx2x_sp(bp, context[i].eth);
-               struct bnx2x_fastpath *fp = &bp->fp[i];
-               u8 cl_id = fp->cl_id;
-
-               context->ustorm_st_context.common.sb_index_numbers =
-                                               BNX2X_RX_SB_INDEX_NUM;
-               context->ustorm_st_context.common.clientId = cl_id;
-               context->ustorm_st_context.common.status_block_id = fp->sb_id;
-               context->ustorm_st_context.common.flags =
-                       (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT |
-                        USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS);
-               context->ustorm_st_context.common.statistics_counter_id =
-                                               cl_id;
-               context->ustorm_st_context.common.mc_alignment_log_size =
-                                               BNX2X_RX_ALIGN_SHIFT;
-               context->ustorm_st_context.common.bd_buff_size =
-                                               bp->rx_buf_size;
-               context->ustorm_st_context.common.bd_page_base_hi =
-                                               U64_HI(fp->rx_desc_mapping);
-               context->ustorm_st_context.common.bd_page_base_lo =
-                                               U64_LO(fp->rx_desc_mapping);
-               if (!fp->disable_tpa) {
-                       context->ustorm_st_context.common.flags |=
-                               USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA;
-                       context->ustorm_st_context.common.sge_buff_size =
-                               (u16)min_t(u32, SGE_PAGE_SIZE*PAGES_PER_SGE,
-                                          0xffff);
-                       context->ustorm_st_context.common.sge_page_base_hi =
-                                               U64_HI(fp->rx_sge_mapping);
-                       context->ustorm_st_context.common.sge_page_base_lo =
-                                               U64_LO(fp->rx_sge_mapping);
-
-                       context->ustorm_st_context.common.max_sges_for_packet =
-                               SGE_PAGE_ALIGN(bp->dev->mtu) >> SGE_PAGE_SHIFT;
-                       context->ustorm_st_context.common.max_sges_for_packet =
-                               ((context->ustorm_st_context.common.
-                                 max_sges_for_packet + PAGES_PER_SGE - 1) &
-                                (~(PAGES_PER_SGE - 1))) >> PAGES_PER_SGE_SHIFT;
-               }
+       memset(&ramrod_param, 0, sizeof(ramrod_param));
 
-               context->ustorm_ag_context.cdu_usage =
-                       CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
-                                              CDU_REGION_NUMBER_UCM_AG,
-                                              ETH_CONNECTION_TYPE);
+       /* Prepare ramrod parameters */
+       ramrod_param.cid = 0;
+       ramrod_param.cl_id = cl_id;
+       ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
+       ramrod_param.func_id = BP_FUNC(bp);
 
-               context->xstorm_ag_context.cdu_reserved =
-                       CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
-                                              CDU_REGION_NUMBER_XCM_AG,
-                                              ETH_CONNECTION_TYPE);
-       }
+       ramrod_param.pstate = &bp->sp_state;
+       ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
 
-       /* Tx */
-       for_each_queue(bp, i) {
-               struct bnx2x_fastpath *fp = &bp->fp[i];
-               struct eth_context *context =
-                       bnx2x_sp(bp, context[i].eth);
+       ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
+       ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
 
-               context->cstorm_st_context.sb_index_number =
-                                               C_SB_ETH_TX_CQ_INDEX;
-               context->cstorm_st_context.status_block_id = fp->sb_id;
+       set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
 
-               context->xstorm_st_context.tx_bd_page_base_hi =
-                                               U64_HI(fp->tx_desc_mapping);
-               context->xstorm_st_context.tx_bd_page_base_lo =
-                                               U64_LO(fp->tx_desc_mapping);
-               context->xstorm_st_context.statistics_data = (fp->cl_id |
-                               XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
-       }
-}
+       ramrod_param.ramrod_flags = ramrod_flags;
+       ramrod_param.rx_mode_flags = rx_mode_flags;
 
-static void bnx2x_init_ind_table(struct bnx2x *bp)
-{
-       int func = BP_FUNC(bp);
-       int i;
+       ramrod_param.rx_accept_flags = rx_accept_flags;
+       ramrod_param.tx_accept_flags = tx_accept_flags;
 
-       if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
+       rc = bnx2x_config_rx_mode(bp, &ramrod_param);
+       if (rc < 0) {
+               BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
                return;
-
-       DP(NETIF_MSG_IFUP,
-          "Initializing indirection table  multi_mode %d\n", bp->multi_mode);
-       for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
-               REG_WR8(bp, BAR_TSTRORM_INTMEM +
-                       TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
-                       bp->fp->cl_id + (i % bp->num_queues));
+       }
 }
 
-void bnx2x_set_client_config(struct bnx2x *bp)
+/* called with netif_addr_lock_bh() */
+void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
 {
-       struct tstorm_eth_client_config tstorm_client = {0};
-       int port = BP_PORT(bp);
-       int i;
+       unsigned long rx_mode_flags = 0, ramrod_flags = 0;
+       unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
 
-       tstorm_client.mtu = bp->dev->mtu;
-       tstorm_client.config_flags =
-                               (TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE |
-                                TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE);
-#ifdef BCM_VLAN
-       if (bp->rx_mode && bp->vlgrp && (bp->flags & HW_VLAN_RX_FLAG)) {
-               tstorm_client.config_flags |=
-                               TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE;
-               DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
-       }
-#endif
+#ifdef BCM_CNIC
+       if (!NO_FCOE(bp))
 
-       for_each_queue(bp, i) {
-               tstorm_client.statistics_counter_id = bp->fp[i].cl_id;
+               /* Configure rx_mode of FCoE Queue */
+               __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
+#endif
 
-               REG_WR(bp, BAR_TSTRORM_INTMEM +
-                      TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id),
-                      ((u32 *)&tstorm_client)[0]);
-               REG_WR(bp, BAR_TSTRORM_INTMEM +
-                      TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id) + 4,
-                      ((u32 *)&tstorm_client)[1]);
-       }
+       switch (bp->rx_mode) {
+       case BNX2X_RX_MODE_NONE:
+               /*
+                * 'drop all' supersedes any accept flags that may have been
+                * passed to the function.
+                */
+               break;
+       case BNX2X_RX_MODE_NORMAL:
+               __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
+               __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
+               __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
 
-       DP(BNX2X_MSG_OFF, "tstorm_client: 0x%08x 0x%08x\n",
-          ((u32 *)&tstorm_client)[0], ((u32 *)&tstorm_client)[1]);
-}
+               /* internal switching mode */
+               __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
+               __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
+               __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
 
-void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
-{
-       struct tstorm_eth_mac_filter_config tstorm_mac_filter = {0};
-       int mode = bp->rx_mode;
-       int mask = bp->rx_mode_cl_mask;
-       int func = BP_FUNC(bp);
-       int port = BP_PORT(bp);
-       int i;
-       /* All but management unicast packets should pass to the host as well */
-       u32 llh_mask =
-               NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
-               NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST |
-               NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
-               NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
+               break;
+       case BNX2X_RX_MODE_ALLMULTI:
+               __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
+               __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
+               __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
 
-       DP(NETIF_MSG_IFUP, "rx mode %d  mask 0x%x\n", mode, mask);
+               /* internal switching mode */
+               __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
+               __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
+               __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
 
-       switch (mode) {
-       case BNX2X_RX_MODE_NONE: /* no Rx */
-               tstorm_mac_filter.ucast_drop_all = mask;
-               tstorm_mac_filter.mcast_drop_all = mask;
-               tstorm_mac_filter.bcast_drop_all = mask;
                break;
+       case BNX2X_RX_MODE_PROMISC:
+               /* According to deffinition of SI mode, iface in promisc mode
+                * should receive matched and unmatched (in resolution of port)
+                * unicast packets.
+                */
+               __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
+               __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
+               __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
+               __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
 
-       case BNX2X_RX_MODE_NORMAL:
-               tstorm_mac_filter.bcast_accept_all = mask;
-               break;
+               /* internal switching mode */
+               __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
+               __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
 
-       case BNX2X_RX_MODE_ALLMULTI:
-               tstorm_mac_filter.mcast_accept_all = mask;
-               tstorm_mac_filter.bcast_accept_all = mask;
-               break;
+               if (IS_MF_SI(bp))
+                       __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
+               else
+                       __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
 
-       case BNX2X_RX_MODE_PROMISC:
-               tstorm_mac_filter.ucast_accept_all = mask;
-               tstorm_mac_filter.mcast_accept_all = mask;
-               tstorm_mac_filter.bcast_accept_all = mask;
-               /* pass management unicast packets as well */
-               llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
                break;
-
        default:
-               BNX2X_ERR("BAD rx mode (%d)\n", mode);
-               break;
+               BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
+               return;
        }
 
-       REG_WR(bp,
-              (port ? NIG_REG_LLH1_BRB1_DRV_MASK : NIG_REG_LLH0_BRB1_DRV_MASK),
-              llh_mask);
-
-       for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) {
-               REG_WR(bp, BAR_TSTRORM_INTMEM +
-                      TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + i * 4,
-                      ((u32 *)&tstorm_mac_filter)[i]);
-
-/*             DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i,
-                  ((u32 *)&tstorm_mac_filter)[i]); */
+       if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
+               __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
+               __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
        }
 
-       if (mode != BNX2X_RX_MODE_NONE)
-               bnx2x_set_client_config(bp);
+       __set_bit(RAMROD_RX, &ramrod_flags);
+       __set_bit(RAMROD_TX, &ramrod_flags);
+
+       bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
+                           tx_accept_flags, ramrod_flags);
 }
 
 static void bnx2x_init_internal_common(struct bnx2x *bp)
 {
        int i;
 
+       if (IS_MF_SI(bp))
+               /*
+                * In switch independent mode, the TSTORM needs to accept
+                * packets that failed classification, since approximate match
+                * mac addresses aren't written to NIG LLH
+                */
+               REG_WR8(bp, BAR_TSTRORM_INTMEM +
+                           TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
+       else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
+               REG_WR8(bp, BAR_TSTRORM_INTMEM +
+                           TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
+
        /* Zero this manually as its initialization is
           currently missing in the initTool */
        for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
                REG_WR(bp, BAR_USTRORM_INTMEM +
                       USTORM_AGG_DATA_OFFSET + i * 4, 0);
-}
-
-static void bnx2x_init_internal_port(struct bnx2x *bp)
-{
-       int port = BP_PORT(bp);
-
-       REG_WR(bp,
-              BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_U_OFFSET(port), BNX2X_BTR);
-       REG_WR(bp,
-              BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_C_OFFSET(port), BNX2X_BTR);
-       REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
-       REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
-}
-
-static void bnx2x_init_internal_func(struct bnx2x *bp)
-{
-       struct tstorm_eth_function_common_config tstorm_config = {0};
-       struct stats_indication_flags stats_flags = {0};
-       int port = BP_PORT(bp);
-       int func = BP_FUNC(bp);
-       int i, j;
-       u32 offset;
-       u16 max_agg_size;
-
-       tstorm_config.config_flags = RSS_FLAGS(bp);
-
-       if (is_multi(bp))
-               tstorm_config.rss_result_mask = MULTI_MASK;
-
-       /* Enable TPA if needed */
-       if (bp->flags & TPA_ENABLE_FLAG)
-               tstorm_config.config_flags |=
-                       TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
-
-       if (IS_E1HMF(bp))
-               tstorm_config.config_flags |=
-                               TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM;
-
-       tstorm_config.leading_client_id = BP_L_ID(bp);
-
-       REG_WR(bp, BAR_TSTRORM_INTMEM +
-              TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func),
-              (*(u32 *)&tstorm_config));
-
-       bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */
-       bp->rx_mode_cl_mask = (1 << BP_L_ID(bp));
-       bnx2x_set_storm_rx_mode(bp);
-
-       for_each_queue(bp, i) {
-               u8 cl_id = bp->fp[i].cl_id;
-
-               /* reset xstorm per client statistics */
-               offset = BAR_XSTRORM_INTMEM +
-                        XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
-               for (j = 0;
-                    j < sizeof(struct xstorm_per_client_stats) / 4; j++)
-                       REG_WR(bp, offset + j*4, 0);
-
-               /* reset tstorm per client statistics */
-               offset = BAR_TSTRORM_INTMEM +
-                        TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
-               for (j = 0;
-                    j < sizeof(struct tstorm_per_client_stats) / 4; j++)
-                       REG_WR(bp, offset + j*4, 0);
-
-               /* reset ustorm per client statistics */
-               offset = BAR_USTRORM_INTMEM +
-                        USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
-               for (j = 0;
-                    j < sizeof(struct ustorm_per_client_stats) / 4; j++)
-                       REG_WR(bp, offset + j*4, 0);
-       }
-
-       /* Init statistics related context */
-       stats_flags.collect_eth = 1;
-
-       REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func),
-              ((u32 *)&stats_flags)[0]);
-       REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func) + 4,
-              ((u32 *)&stats_flags)[1]);
-
-       REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func),
-              ((u32 *)&stats_flags)[0]);
-       REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func) + 4,
-              ((u32 *)&stats_flags)[1]);
-
-       REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func),
-              ((u32 *)&stats_flags)[0]);
-       REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func) + 4,
-              ((u32 *)&stats_flags)[1]);
-
-       REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func),
-              ((u32 *)&stats_flags)[0]);
-       REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func) + 4,
-              ((u32 *)&stats_flags)[1]);
-
-       REG_WR(bp, BAR_XSTRORM_INTMEM +
-              XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
-              U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
-       REG_WR(bp, BAR_XSTRORM_INTMEM +
-              XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
-              U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
-
-       REG_WR(bp, BAR_TSTRORM_INTMEM +
-              TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
-              U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
-       REG_WR(bp, BAR_TSTRORM_INTMEM +
-              TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
-              U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
-
-       REG_WR(bp, BAR_USTRORM_INTMEM +
-              USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
-              U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
-       REG_WR(bp, BAR_USTRORM_INTMEM +
-              USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
-              U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
-
-       if (CHIP_IS_E1H(bp)) {
-               REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
-                       IS_E1HMF(bp));
-               REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
-                       IS_E1HMF(bp));
-               REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
-                       IS_E1HMF(bp));
-               REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
-                       IS_E1HMF(bp));
-
-               REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(func),
-                        bp->e1hov);
-       }
-
-       /* Init CQ ring mapping and aggregation size, the FW limit is 8 frags */
-       max_agg_size = min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) *
-                                  SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
-       for_each_queue(bp, i) {
-               struct bnx2x_fastpath *fp = &bp->fp[i];
-
-               REG_WR(bp, BAR_USTRORM_INTMEM +
-                      USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id),
-                      U64_LO(fp->rx_comp_mapping));
-               REG_WR(bp, BAR_USTRORM_INTMEM +
-                      USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id) + 4,
-                      U64_HI(fp->rx_comp_mapping));
-
-               /* Next page */
-               REG_WR(bp, BAR_USTRORM_INTMEM +
-                      USTORM_CQE_PAGE_NEXT_OFFSET(port, fp->cl_id),
-                      U64_LO(fp->rx_comp_mapping + BCM_PAGE_SIZE));
-               REG_WR(bp, BAR_USTRORM_INTMEM +
-                      USTORM_CQE_PAGE_NEXT_OFFSET(port, fp->cl_id) + 4,
-                      U64_HI(fp->rx_comp_mapping + BCM_PAGE_SIZE));
-
-               REG_WR16(bp, BAR_USTRORM_INTMEM +
-                        USTORM_MAX_AGG_SIZE_OFFSET(port, fp->cl_id),
-                        max_agg_size);
-       }
-
-       /* dropless flow control */
-       if (CHIP_IS_E1H(bp)) {
-               struct ustorm_eth_rx_pause_data_e1h rx_pause = {0};
-
-               rx_pause.bd_thr_low = 250;
-               rx_pause.cqe_thr_low = 250;
-               rx_pause.cos = 1;
-               rx_pause.sge_thr_low = 0;
-               rx_pause.bd_thr_high = 350;
-               rx_pause.cqe_thr_high = 350;
-               rx_pause.sge_thr_high = 0;
-
-               for_each_queue(bp, i) {
-                       struct bnx2x_fastpath *fp = &bp->fp[i];
-
-                       if (!fp->disable_tpa) {
-                               rx_pause.sge_thr_low = 150;
-                               rx_pause.sge_thr_high = 250;
-                       }
-
-
-                       offset = BAR_USTRORM_INTMEM +
-                                USTORM_ETH_RING_PAUSE_DATA_OFFSET(port,
-                                                                  fp->cl_id);
-                       for (j = 0;
-                            j < sizeof(struct ustorm_eth_rx_pause_data_e1h)/4;
-                            j++)
-                               REG_WR(bp, offset + j*4,
-                                      ((u32 *)&rx_pause)[j]);
-               }
-       }
-
-       memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
-
-       /* Init rate shaping and fairness contexts */
-       if (IS_E1HMF(bp)) {
-               int vn;
-
-               /* During init there is no active link
-                  Until link is up, set link rate to 10Gbps */
-               bp->link_vars.line_speed = SPEED_10000;
-               bnx2x_init_port_minmax(bp);
-
-               if (!BP_NOMCP(bp))
-                       bp->mf_config =
-                             SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
-               bnx2x_calc_vn_weight_sum(bp);
-
-               for (vn = VN_0; vn < E1HVN_MAX; vn++)
-                       bnx2x_init_vn_minmax(bp, 2*vn + port);
-
-               /* Enable rate shaping and fairness */
-               bp->cmng.flags.cmng_enables |=
-                                       CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
-
-       } else {
-               /* rate shaping and fairness are disabled */
-               DP(NETIF_MSG_IFUP,
-                  "single function mode  minmax will be disabled\n");
+       if (!CHIP_IS_E1x(bp)) {
+               REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
+                       CHIP_INT_MODE_IS_BC(bp) ?
+                       HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
        }
-
-
-       /* Store cmng structures to internal memory */
-       if (bp->port.pmf)
-               for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
-                       REG_WR(bp, BAR_XSTRORM_INTMEM +
-                              XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4,
-                              ((u32 *)(&bp->cmng))[i]);
 }
 
 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
 {
        switch (load_code) {
        case FW_MSG_CODE_DRV_LOAD_COMMON:
+       case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
                bnx2x_init_internal_common(bp);
                /* no break */
 
        case FW_MSG_CODE_DRV_LOAD_PORT:
-               bnx2x_init_internal_port(bp);
+               /* nothing to do */
                /* no break */
 
        case FW_MSG_CODE_DRV_LOAD_FUNCTION:
-               bnx2x_init_internal_func(bp);
+               /* internal memory per function is
+                  initialized inside bnx2x_pf_init */
                break;
 
        default:
@@ -3425,49 +5033,97 @@ static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
        }
 }
 
+static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
+{
+       return fp->bp->igu_base_sb + fp->index + CNIC_CONTEXT_USE;
+}
+
+static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
+{
+       return fp->bp->base_fw_ndsb + fp->index + CNIC_CONTEXT_USE;
+}
+
+static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
+{
+       if (CHIP_IS_E1x(fp->bp))
+               return BP_L_ID(fp->bp) + fp->index;
+       else    /* We want Client ID to be the same as IGU SB ID for 57712 */
+               return bnx2x_fp_igu_sb_id(fp);
+}
+
+static void bnx2x_init_fp(struct bnx2x *bp, int fp_idx)
+{
+       struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
+       unsigned long q_type = 0;
+
+       fp->cid = fp_idx;
+       fp->cl_id = bnx2x_fp_cl_id(fp);
+       fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
+       fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
+       /* qZone id equals to FW (per path) client id */
+       fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
+
+       /* init shortcut */
+       fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
+       /* Setup SB indicies */
+       fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
+       fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
+
+       /* Configure Queue State object */
+       __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
+       __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
+       bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, fp->cid, BP_FUNC(bp),
+               bnx2x_sp(bp, q_rdata), bnx2x_sp_mapping(bp, q_rdata),
+                             q_type);
+
+       /**
+        * Configure classification DBs: Always enable Tx switching
+        */
+       bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
+
+       DP(NETIF_MSG_IFUP, "queue[%d]:  bnx2x_init_sb(%p,%p)  "
+                                  "cl_id %d  fw_sb %d  igu_sb %d\n",
+                  fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
+                  fp->igu_sb_id);
+       bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
+                     fp->fw_sb_id, fp->igu_sb_id);
+
+       bnx2x_update_fpsb_idx(fp);
+}
+
 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
 {
        int i;
 
-       for_each_queue(bp, i) {
-               struct bnx2x_fastpath *fp = &bp->fp[i];
-
-               fp->bp = bp;
-               fp->state = BNX2X_FP_STATE_CLOSED;
-               fp->index = i;
-               fp->cl_id = BP_L_ID(bp) + i;
+       for_each_eth_queue(bp, i)
+               bnx2x_init_fp(bp, i);
 #ifdef BCM_CNIC
-               fp->sb_id = fp->cl_id + 1;
-#else
-               fp->sb_id = fp->cl_id;
+       if (!NO_FCOE(bp))
+               bnx2x_init_fcoe_fp(bp);
+
+       bnx2x_init_sb(bp, bp->cnic_sb_mapping,
+                     BNX2X_VF_ID_INVALID, false,
+                     bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
+
 #endif
-               DP(NETIF_MSG_IFUP,
-                  "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  sb %d\n",
-                  i, bp, fp->status_blk, fp->cl_id, fp->sb_id);
-               bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping,
-                             fp->sb_id);
-               bnx2x_update_fpsb_idx(fp);
-       }
 
+       /* Initialize MOD_ABS interrupts */
+       bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
+                              bp->common.shmem_base, bp->common.shmem2_base,
+                              BP_PORT(bp));
        /* ensure status block indices were read */
        rmb();
 
-
-       bnx2x_init_def_sb(bp, bp->def_status_blk, bp->def_status_blk_mapping,
-                         DEF_SB_ID);
+       bnx2x_init_def_sb(bp);
        bnx2x_update_dsb_idx(bp);
-       bnx2x_update_coalesce(bp);
        bnx2x_init_rx_rings(bp);
-       bnx2x_init_tx_ring(bp);
+       bnx2x_init_tx_rings(bp);
        bnx2x_init_sp_ring(bp);
-       bnx2x_init_context(bp);
+       bnx2x_init_eq_ring(bp);
        bnx2x_init_internal(bp, load_code);
-       bnx2x_init_ind_table(bp);
+       bnx2x_pf_init(bp);
        bnx2x_stats_init(bp);
 
-       /* At this point, we are ready for interrupts */
-       atomic_set(&bp->intr_sem, 0);
-
        /* flush all before enabling interrupts */
        mb();
        mmiowb();
@@ -3497,8 +5153,7 @@ static int bnx2x_gunzip_init(struct bnx2x *bp)
        if (bp->strm  == NULL)
                goto gunzip_nomem2;
 
-       bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
-                                     GFP_KERNEL);
+       bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
        if (bp->strm->workspace == NULL)
                goto gunzip_nomem3;
 
@@ -3521,10 +5176,11 @@ gunzip_nomem1:
 
 static void bnx2x_gunzip_end(struct bnx2x *bp)
 {
-       kfree(bp->strm->workspace);
-
-       kfree(bp->strm);
-       bp->strm = NULL;
+       if (bp->strm) {
+               vfree(bp->strm->workspace);
+               kfree(bp->strm);
+               bp->strm = NULL;
+       }
 
        if (bp->gunzip_buf) {
                dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
@@ -3620,8 +5276,6 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
        else
                factor = 1;
 
-       DP(NETIF_MSG_HW, "start part1\n");
-
        /* Disable inputs of parser neighbor blocks */
        REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
        REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
@@ -3672,8 +5326,8 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
        msleep(50);
        REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
        msleep(50);
-       bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
-       bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
+       bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
 
        DP(NETIF_MSG_HW, "part2\n");
 
@@ -3737,8 +5391,8 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
        msleep(50);
        REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
        msleep(50);
-       bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
-       bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
+       bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
 #ifndef BCM_CNIC
        /* set NIC mode */
        REG_WR(bp, PRS_REG_NIC_MODE, 1);
@@ -3755,12 +5409,22 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
        return 0; /* OK */
 }
 
-static void enable_blocks_attention(struct bnx2x *bp)
+static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
 {
        REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
-       REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
+       if (!CHIP_IS_E1x(bp))
+               REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
+       else
+               REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
        REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
        REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
+       /*
+        * mask read length error interrupts in brb for parser
+        * (parsing unit and 'checksum and crc' unit)
+        * these errors are legal (PU reads fixed length and CAC can cause
+        * read length error on truncated packets)
+        */
+       REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
        REG_WR(bp, QM_REG_QM_INT_MASK, 0);
        REG_WR(bp, TM_REG_TM_INT_MASK, 0);
        REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
@@ -3779,71 +5443,53 @@ static void enable_blocks_attention(struct bnx2x *bp)
        REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
 /*     REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
 /*     REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
+
        if (CHIP_REV_IS_FPGA(bp))
                REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
+       else if (!CHIP_IS_E1x(bp))
+               REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
+                          (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
+                               | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
+                               | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
+                               | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
+                               | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
        else
                REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
        REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
        REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
        REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
 /*     REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
-/*     REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
+
+       if (!CHIP_IS_E1x(bp))
+               /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
+               REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
+
        REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
        REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
 /*     REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
-       REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18);         /* bit 3,4 masked */
-}
-
-static const struct {
-       u32 addr;
-       u32 mask;
-} bnx2x_parity_mask[] = {
-       {PXP_REG_PXP_PRTY_MASK, 0xffffffff},
-       {PXP2_REG_PXP2_PRTY_MASK_0, 0xffffffff},
-       {PXP2_REG_PXP2_PRTY_MASK_1, 0xffffffff},
-       {HC_REG_HC_PRTY_MASK, 0xffffffff},
-       {MISC_REG_MISC_PRTY_MASK, 0xffffffff},
-       {QM_REG_QM_PRTY_MASK, 0x0},
-       {DORQ_REG_DORQ_PRTY_MASK, 0x0},
-       {GRCBASE_UPB + PB_REG_PB_PRTY_MASK, 0x0},
-       {GRCBASE_XPB + PB_REG_PB_PRTY_MASK, 0x0},
-       {SRC_REG_SRC_PRTY_MASK, 0x4}, /* bit 2 */
-       {CDU_REG_CDU_PRTY_MASK, 0x0},
-       {CFC_REG_CFC_PRTY_MASK, 0x0},
-       {DBG_REG_DBG_PRTY_MASK, 0x0},
-       {DMAE_REG_DMAE_PRTY_MASK, 0x0},
-       {BRB1_REG_BRB1_PRTY_MASK, 0x0},
-       {PRS_REG_PRS_PRTY_MASK, (1<<6)},/* bit 6 */
-       {TSDM_REG_TSDM_PRTY_MASK, 0x18},/* bit 3,4 */
-       {CSDM_REG_CSDM_PRTY_MASK, 0x8}, /* bit 3 */
-       {USDM_REG_USDM_PRTY_MASK, 0x38},/* bit 3,4,5 */
-       {XSDM_REG_XSDM_PRTY_MASK, 0x8}, /* bit 3 */
-       {TSEM_REG_TSEM_PRTY_MASK_0, 0x0},
-       {TSEM_REG_TSEM_PRTY_MASK_1, 0x0},
-       {USEM_REG_USEM_PRTY_MASK_0, 0x0},
-       {USEM_REG_USEM_PRTY_MASK_1, 0x0},
-       {CSEM_REG_CSEM_PRTY_MASK_0, 0x0},
-       {CSEM_REG_CSEM_PRTY_MASK_1, 0x0},
-       {XSEM_REG_XSEM_PRTY_MASK_0, 0x0},
-       {XSEM_REG_XSEM_PRTY_MASK_1, 0x0}
-};
-
-static void enable_blocks_parity(struct bnx2x *bp)
-{
-       int i;
-
-       for (i = 0; i < ARRAY_SIZE(bnx2x_parity_mask); i++)
-               REG_WR(bp, bnx2x_parity_mask[i].addr,
-                       bnx2x_parity_mask[i].mask);
+       REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
 }
 
-
 static void bnx2x_reset_common(struct bnx2x *bp)
 {
+       u32 val = 0x1400;
+
        /* reset_common */
        REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
               0xd3ffff7f);
-       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
+
+       if (CHIP_IS_E3(bp)) {
+               val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
+               val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
+       }
+
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
+}
+
+static void bnx2x_setup_dmae(struct bnx2x *bp)
+{
+       bp->dmae_ready = 0;
+       spin_lock_init(&bp->dmae_lock);
 }
 
 static void bnx2x_init_pxp(struct bnx2x *bp)
@@ -3852,7 +5498,7 @@ static void bnx2x_init_pxp(struct bnx2x *bp)
        int r_order, w_order;
 
        pci_read_config_word(bp->pdev,
-                            bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
+                            bp->pdev->pcie_cap + PCI_EXP_DEVCTL, &devctl);
        DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
        w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
        if (bp->mrrs == -1)
@@ -3917,35 +5563,133 @@ static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
        REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
 }
 
-static int bnx2x_init_common(struct bnx2x *bp)
+static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
 {
-       u32 val, i;
-#ifdef BCM_CNIC
-       u32 wb_write[2];
-#endif
+       u32 offset = 0;
+
+       if (CHIP_IS_E1(bp))
+               return;
+       if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
+               return;
+
+       switch (BP_ABS_FUNC(bp)) {
+       case 0:
+               offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
+               break;
+       case 1:
+               offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
+               break;
+       case 2:
+               offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
+               break;
+       case 3:
+               offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
+               break;
+       case 4:
+               offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
+               break;
+       case 5:
+               offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
+               break;
+       case 6:
+               offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
+               break;
+       case 7:
+               offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
+               break;
+       default:
+               return;
+       }
+
+       REG_WR(bp, offset, pretend_func_num);
+       REG_RD(bp, offset);
+       DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
+}
+
+void bnx2x_pf_disable(struct bnx2x *bp)
+{
+       u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
+       val &= ~IGU_PF_CONF_FUNC_EN;
+
+       REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
+       REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
+       REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
+}
+
+static inline void bnx2x__common_init_phy(struct bnx2x *bp)
+{
+       u32 shmem_base[2], shmem2_base[2];
+       shmem_base[0] =  bp->common.shmem_base;
+       shmem2_base[0] = bp->common.shmem2_base;
+       if (!CHIP_IS_E1x(bp)) {
+               shmem_base[1] =
+                       SHMEM2_RD(bp, other_shmem_base_addr);
+               shmem2_base[1] =
+                       SHMEM2_RD(bp, other_shmem2_base_addr);
+       }
+       bnx2x_acquire_phy_lock(bp);
+       bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
+                             bp->common.chip_id);
+       bnx2x_release_phy_lock(bp);
+}
+
+/**
+ * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
+ *
+ * @bp:                driver handle
+ */
+static int bnx2x_init_hw_common(struct bnx2x *bp)
+{
+       u32 val;
 
-       DP(BNX2X_MSG_MCP, "starting common init  func %d\n", BP_FUNC(bp));
+       DP(BNX2X_MSG_MCP, "starting common init  func %d\n", BP_ABS_FUNC(bp));
 
        bnx2x_reset_common(bp);
        REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
-       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
 
-       bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
-       if (CHIP_IS_E1H(bp))
-               REG_WR(bp, MISC_REG_E1HMF_MODE, IS_E1HMF(bp));
+       val = 0xfffc;
+       if (CHIP_IS_E3(bp)) {
+               val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
+               val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
+       }
+       REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
+
+       bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
 
-       REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100);
-       msleep(30);
-       REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x0);
+       if (!CHIP_IS_E1x(bp)) {
+               u8 abs_func_id;
 
-       bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE);
+               /**
+                * 4-port mode or 2-port mode we need to turn of master-enable
+                * for everyone, after that, turn it back on for self.
+                * so, we disregard multi-function or not, and always disable
+                * for all functions on the given path, this means 0,2,4,6 for
+                * path 0 and 1,3,5,7 for path 1
+                */
+               for (abs_func_id = BP_PATH(bp);
+                    abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
+                       if (abs_func_id == BP_ABS_FUNC(bp)) {
+                               REG_WR(bp,
+                                   PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
+                                   1);
+                               continue;
+                       }
+
+                       bnx2x_pretend_func(bp, abs_func_id);
+                       /* clear pf enable */
+                       bnx2x_pf_disable(bp);
+                       bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
+               }
+       }
+
+       bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
        if (CHIP_IS_E1(bp)) {
                /* enable HW interrupt from PXP on USDM overflow
                   bit 16 on INT_MASK_0 */
                REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
        }
 
-       bnx2x_init_block(bp, PXP2_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
        bnx2x_init_pxp(bp);
 
 #ifdef __BIG_ENDIAN
@@ -3964,12 +5708,7 @@ static int bnx2x_init_common(struct bnx2x *bp)
        REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
 #endif
 
-       REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2);
-#ifdef BCM_CNIC
-       REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5);
-       REG_WR(bp, PXP2_REG_RQ_QM_P_SIZE, 5);
-       REG_WR(bp, PXP2_REG_RQ_SRC_P_SIZE, 5);
-#endif
+       bnx2x_ilt_init_page_size(bp, INITOP_SET);
 
        if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
                REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
@@ -3988,80 +5727,202 @@ static int bnx2x_init_common(struct bnx2x *bp)
                return -EBUSY;
        }
 
+       /* Timers bug workaround E2 only. We need to set the entire ILT to
+        * have entries with value "0" and valid bit on.
+        * This needs to be done by the first PF that is loaded in a path
+        * (i.e. common phase)
+        */
+       if (!CHIP_IS_E1x(bp)) {
+/* In E2 there is a bug in the timers block that can cause function 6 / 7
+ * (i.e. vnic3) to start even if it is marked as "scan-off".
+ * This occurs when a different function (func2,3) is being marked
+ * as "scan-off". Real-life scenario for example: if a driver is being
+ * load-unloaded while func6,7 are down. This will cause the timer to access
+ * the ilt, translate to a logical address and send a request to read/write.
+ * Since the ilt for the function that is down is not valid, this will cause
+ * a translation error which is unrecoverable.
+ * The Workaround is intended to make sure that when this happens nothing fatal
+ * will occur. The workaround:
+ *     1.  First PF driver which loads on a path will:
+ *             a.  After taking the chip out of reset, by using pretend,
+ *                 it will write "0" to the following registers of
+ *                 the other vnics.
+ *                 REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
+ *                 REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
+ *                 REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
+ *                 And for itself it will write '1' to
+ *                 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
+ *                 dmae-operations (writing to pram for example.)
+ *                 note: can be done for only function 6,7 but cleaner this
+ *                       way.
+ *             b.  Write zero+valid to the entire ILT.
+ *             c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
+ *                 VNIC3 (of that port). The range allocated will be the
+ *                 entire ILT. This is needed to prevent  ILT range error.
+ *     2.  Any PF driver load flow:
+ *             a.  ILT update with the physical addresses of the allocated
+ *                 logical pages.
+ *             b.  Wait 20msec. - note that this timeout is needed to make
+ *                 sure there are no requests in one of the PXP internal
+ *                 queues with "old" ILT addresses.
+ *             c.  PF enable in the PGLC.
+ *             d.  Clear the was_error of the PF in the PGLC. (could have
+ *                 occured while driver was down)
+ *             e.  PF enable in the CFC (WEAK + STRONG)
+ *             f.  Timers scan enable
+ *     3.  PF driver unload flow:
+ *             a.  Clear the Timers scan_en.
+ *             b.  Polling for scan_on=0 for that PF.
+ *             c.  Clear the PF enable bit in the PXP.
+ *             d.  Clear the PF enable in the CFC (WEAK + STRONG)
+ *             e.  Write zero+valid to all ILT entries (The valid bit must
+ *                 stay set)
+ *             f.  If this is VNIC 3 of a port then also init
+ *                 first_timers_ilt_entry to zero and last_timers_ilt_entry
+ *                 to the last enrty in the ILT.
+ *
+ *     Notes:
+ *     Currently the PF error in the PGLC is non recoverable.
+ *     In the future the there will be a recovery routine for this error.
+ *     Currently attention is masked.
+ *     Having an MCP lock on the load/unload process does not guarantee that
+ *     there is no Timer disable during Func6/7 enable. This is because the
+ *     Timers scan is currently being cleared by the MCP on FLR.
+ *     Step 2.d can be done only for PF6/7 and the driver can also check if
+ *     there is error before clearing it. But the flow above is simpler and
+ *     more general.
+ *     All ILT entries are written by zero+valid and not just PF6/7
+ *     ILT entries since in the future the ILT entries allocation for
+ *     PF-s might be dynamic.
+ */
+               struct ilt_client_info ilt_cli;
+               struct bnx2x_ilt ilt;
+               memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
+               memset(&ilt, 0, sizeof(struct bnx2x_ilt));
+
+               /* initialize dummy TM client */
+               ilt_cli.start = 0;
+               ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
+               ilt_cli.client_num = ILT_CLIENT_TM;
+
+               /* Step 1: set zeroes to all ilt page entries with valid bit on
+                * Step 2: set the timers first/last ilt entry to point
+                * to the entire range to prevent ILT range error for 3rd/4th
+                * vnic (this code assumes existance of the vnic)
+                *
+                * both steps performed by call to bnx2x_ilt_client_init_op()
+                * with dummy TM client
+                *
+                * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
+                * and his brother are split registers
+                */
+               bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
+               bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
+               bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
+
+               REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
+               REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
+               REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
+       }
+
+
        REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
        REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
 
-       bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE);
+       if (!CHIP_IS_E1x(bp)) {
+               int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
+                               (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
+               bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
+
+               bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
+
+               /* let the HW do it's magic ... */
+               do {
+                       msleep(200);
+                       val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
+               } while (factor-- && (val != 1));
+
+               if (val != 1) {
+                       BNX2X_ERR("ATC_INIT failed\n");
+                       return -EBUSY;
+               }
+       }
+
+       bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
 
        /* clean the DMAE memory */
        bp->dmae_ready = 1;
-       bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
+       bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
+
+       bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
+
+       bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
+
+       bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
 
-       bnx2x_init_block(bp, TCM_BLOCK, COMMON_STAGE);
-       bnx2x_init_block(bp, UCM_BLOCK, COMMON_STAGE);
-       bnx2x_init_block(bp, CCM_BLOCK, COMMON_STAGE);
-       bnx2x_init_block(bp, XCM_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
 
        bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
        bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
        bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
        bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
 
-       bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
 
-#ifdef BCM_CNIC
-       wb_write[0] = 0;
-       wb_write[1] = 0;
-       for (i = 0; i < 64; i++) {
-               REG_WR(bp, QM_REG_BASEADDR + i*4, 1024 * 4 * (i%16));
-               bnx2x_init_ind_wr(bp, QM_REG_PTRTBL + i*8, wb_write, 2);
 
-               if (CHIP_IS_E1H(bp)) {
-                       REG_WR(bp, QM_REG_BASEADDR_EXT_A + i*4, 1024*4*(i%16));
-                       bnx2x_init_ind_wr(bp, QM_REG_PTRTBL_EXT_A + i*8,
-                                         wb_write, 2);
-               }
-       }
-#endif
+       /* QM queues pointers table */
+       bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
+
        /* soft reset pulse */
        REG_WR(bp, QM_REG_SOFT_RESET, 1);
        REG_WR(bp, QM_REG_SOFT_RESET, 0);
 
 #ifdef BCM_CNIC
-       bnx2x_init_block(bp, TIMERS_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
 #endif
 
-       bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE);
-       REG_WR(bp, DORQ_REG_DPM_CID_OFST, BCM_PAGE_SHIFT);
-       if (!CHIP_REV_IS_SLOW(bp)) {
+       bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
+       REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
+       if (!CHIP_REV_IS_SLOW(bp))
                /* enable hw interrupt from doorbell Q */
                REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
-       }
 
-       bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
-       bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
+
+       bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
        REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
-#ifndef BCM_CNIC
-       /* set NIC mode */
-       REG_WR(bp, PRS_REG_NIC_MODE, 1);
-#endif
-       if (CHIP_IS_E1H(bp))
-               REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp));
 
-       bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
-       bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
-       bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE);
-       bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE);
+       if (!CHIP_IS_E1(bp))
+               REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
+
+       if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
+               /* Bit-map indicating which L2 hdrs may appear
+                * after the basic Ethernet header
+                */
+               REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
+                      bp->path_has_ovlan ? 7 : 6);
 
-       bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
-       bnx2x_init_fill(bp, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
-       bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
-       bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
+       bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
+       bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
+       bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
+       bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
 
-       bnx2x_init_block(bp, TSEM_BLOCK, COMMON_STAGE);
-       bnx2x_init_block(bp, USEM_BLOCK, COMMON_STAGE);
-       bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE);
-       bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE);
+       if (!CHIP_IS_E1x(bp)) {
+               /* reset VFC memories */
+               REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
+                          VFC_MEMORIES_RST_REG_CAM_RST |
+                          VFC_MEMORIES_RST_REG_RAM_RST);
+               REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
+                          VFC_MEMORIES_RST_REG_CAM_RST |
+                          VFC_MEMORIES_RST_REG_RAM_RST);
+
+               msleep(20);
+       }
+
+       bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
+       bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
+       bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
+       bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
 
        /* sync semi rtc */
        REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
@@ -4069,14 +5930,18 @@ static int bnx2x_init_common(struct bnx2x *bp)
        REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
               0x80000000);
 
-       bnx2x_init_block(bp, UPB_BLOCK, COMMON_STAGE);
-       bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE);
-       bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
+       bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
+       bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
+
+       if (!CHIP_IS_E1x(bp))
+               REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
+                      bp->path_has_ovlan ? 7 : 6);
 
        REG_WR(bp, SRC_REG_SOFT_RST, 1);
-       for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4)
-               REG_WR(bp, i, random32());
-       bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE);
+
+       bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
+
 #ifdef BCM_CNIC
        REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
        REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
@@ -4097,11 +5962,11 @@ static int bnx2x_init_common(struct bnx2x *bp)
                                          "of cdu_context(%ld)\n",
                         (long)sizeof(union cdu_context));
 
-       bnx2x_init_block(bp, CDU_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
        val = (4 << 24) + (0 << 12) + 1024;
        REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
 
-       bnx2x_init_block(bp, CFC_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
        REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
        /* enable context validation interrupt from CFC */
        REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
@@ -4109,24 +5974,41 @@ static int bnx2x_init_common(struct bnx2x *bp)
        /* set the thresholds to prevent CFC/CDU race */
        REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
 
-       bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE);
-       bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE);
+       bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
+
+       if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
+               REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
+
+       bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
+       bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
 
-       bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE);
        /* Reset PCIE errors for debug */
        REG_WR(bp, 0x2814, 0xffffffff);
        REG_WR(bp, 0x3820, 0xffffffff);
 
-       bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE);
-       bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE);
-       bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE);
-       bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE);
-
-       bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
-       if (CHIP_IS_E1H(bp)) {
-               REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_E1HMF(bp));
-               REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_E1HMF(bp));
+       if (!CHIP_IS_E1x(bp)) {
+               REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
+                          (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
+                               PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
+               REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
+                          (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
+                               PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
+                               PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
+               REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
+                          (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
+                               PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
+                               PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
+       }
+
+       bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
+       if (!CHIP_IS_E1(bp)) {
+               /* in E3 this done in per-port section */
+               if (!CHIP_IS_E3(bp))
+                       REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
        }
+       if (CHIP_IS_E1H(bp))
+               /* not applicable for E2 (and above ...) */
+               REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
 
        if (CHIP_REV_IS_SLOW(bp))
                msleep(200);
@@ -4149,77 +6031,105 @@ static int bnx2x_init_common(struct bnx2x *bp)
        }
        REG_WR(bp, CFC_REG_DEBUG0, 0);
 
-       /* read NIG statistic
-          to see if this is our first up since powerup */
-       bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
-       val = *bnx2x_sp(bp, wb_data[0]);
+       if (CHIP_IS_E1(bp)) {
+               /* read NIG statistic
+                  to see if this is our first up since powerup */
+               bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
+               val = *bnx2x_sp(bp, wb_data[0]);
 
-       /* do internal memory self test */
-       if ((CHIP_IS_E1(bp)) && (val == 0) && bnx2x_int_mem_test(bp)) {
-               BNX2X_ERR("internal mem self test failed\n");
-               return -EBUSY;
+               /* do internal memory self test */
+               if ((val == 0) && bnx2x_int_mem_test(bp)) {
+                       BNX2X_ERR("internal mem self test failed\n");
+                       return -EBUSY;
+               }
        }
 
-       bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
-                                                      bp->common.shmem_base,
-                                                      bp->common.shmem2_base);
-
        bnx2x_setup_fan_failure_detection(bp);
 
        /* clear PXP2 attentions */
        REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
 
-       enable_blocks_attention(bp);
-       if (CHIP_PARITY_SUPPORTED(bp))
-               enable_blocks_parity(bp);
+       bnx2x_enable_blocks_attention(bp);
+       bnx2x_enable_blocks_parity(bp);
 
        if (!BP_NOMCP(bp)) {
-               bnx2x_acquire_phy_lock(bp);
-               bnx2x_common_init_phy(bp, bp->common.shmem_base,
-                                     bp->common.shmem2_base);
-               bnx2x_release_phy_lock(bp);
+               if (CHIP_IS_E1x(bp))
+                       bnx2x__common_init_phy(bp);
        } else
                BNX2X_ERR("Bootcode is missing - can not initialize link\n");
 
        return 0;
 }
 
-static int bnx2x_init_port(struct bnx2x *bp)
+/**
+ * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
+ *
+ * @bp:                driver handle
+ */
+static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
+{
+       int rc = bnx2x_init_hw_common(bp);
+
+       if (rc)
+               return rc;
+
+       /* In E2 2-PORT mode, same ext phy is used for the two paths */
+       if (!BP_NOMCP(bp))
+               bnx2x__common_init_phy(bp);
+
+       return 0;
+}
+
+static int bnx2x_init_hw_port(struct bnx2x *bp)
 {
        int port = BP_PORT(bp);
-       int init_stage = port ? PORT1_STAGE : PORT0_STAGE;
+       int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
        u32 low, high;
        u32 val;
 
+       bnx2x__link_reset(bp);
+
        DP(BNX2X_MSG_MCP, "starting port init  port %d\n", port);
 
        REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
 
-       bnx2x_init_block(bp, PXP_BLOCK, init_stage);
-       bnx2x_init_block(bp, PXP2_BLOCK, init_stage);
+       bnx2x_init_block(bp, BLOCK_MISC, init_phase);
+       bnx2x_init_block(bp, BLOCK_PXP, init_phase);
+       bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
 
-       bnx2x_init_block(bp, TCM_BLOCK, init_stage);
-       bnx2x_init_block(bp, UCM_BLOCK, init_stage);
-       bnx2x_init_block(bp, CCM_BLOCK, init_stage);
-       bnx2x_init_block(bp, XCM_BLOCK, init_stage);
+       /* Timers bug workaround: disables the pf_master bit in pglue at
+        * common phase, we need to enable it here before any dmae access are
+        * attempted. Therefore we manually added the enable-master to the
+        * port phase (it also happens in the function phase)
+        */
+       if (!CHIP_IS_E1x(bp))
+               REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
 
-#ifdef BCM_CNIC
-       REG_WR(bp, QM_REG_CONNNUM_0 + port*4, 1024/16 - 1);
+       bnx2x_init_block(bp, BLOCK_ATC, init_phase);
+       bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
+       bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
+       bnx2x_init_block(bp, BLOCK_QM, init_phase);
+
+       bnx2x_init_block(bp, BLOCK_TCM, init_phase);
+       bnx2x_init_block(bp, BLOCK_UCM, init_phase);
+       bnx2x_init_block(bp, BLOCK_CCM, init_phase);
+       bnx2x_init_block(bp, BLOCK_XCM, init_phase);
+
+       /* QM cid (connection) count */
+       bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
 
-       bnx2x_init_block(bp, TIMERS_BLOCK, init_stage);
+#ifdef BCM_CNIC
+       bnx2x_init_block(bp, BLOCK_TM, init_phase);
        REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
        REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
 #endif
 
-       bnx2x_init_block(bp, DQ_BLOCK, init_stage);
+       bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
 
-       bnx2x_init_block(bp, BRB1_BLOCK, init_stage);
-       if (CHIP_REV_IS_SLOW(bp) && !CHIP_IS_E1H(bp)) {
-               /* no pause for emulation and FPGA */
-               low = 0;
-               high = 513;
-       } else {
-               if (IS_E1HMF(bp))
+       if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
+               bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
+
+               if (IS_MF(bp))
                        low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
                else if (bp->dev->mtu > 4096) {
                        if (bp->flags & ONE_PORT_FLAG)
@@ -4227,81 +6137,125 @@ static int bnx2x_init_port(struct bnx2x *bp)
                        else {
                                val = bp->dev->mtu;
                                /* (24*1024 + val*4)/256 */
-                               low = 96 + (val/64) + ((val % 64) ? 1 : 0);
+                               low = 96 + (val/64) +
+                                               ((val % 64) ? 1 : 0);
                        }
                } else
                        low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
                high = low + 56;        /* 14*1024/256 */
+               REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
+               REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
        }
-       REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
-       REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
+
+       if (CHIP_MODE_IS_4_PORT(bp))
+               REG_WR(bp, (BP_PORT(bp) ?
+                           BRB1_REG_MAC_GUARANTIED_1 :
+                           BRB1_REG_MAC_GUARANTIED_0), 40);
 
 
-       bnx2x_init_block(bp, PRS_BLOCK, init_stage);
+       bnx2x_init_block(bp, BLOCK_PRS, init_phase);
+       if (CHIP_IS_E3B0(bp))
+               /* Ovlan exists only if we are in multi-function +
+                * switch-dependent mode, in switch-independent there
+                * is no ovlan headers
+                */
+               REG_WR(bp, BP_PORT(bp) ?
+                      PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
+                      PRS_REG_HDRS_AFTER_BASIC_PORT_0,
+                      (bp->path_has_ovlan ? 7 : 6));
 
-       bnx2x_init_block(bp, TSDM_BLOCK, init_stage);
-       bnx2x_init_block(bp, CSDM_BLOCK, init_stage);
-       bnx2x_init_block(bp, USDM_BLOCK, init_stage);
-       bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
+       bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
+       bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
+       bnx2x_init_block(bp, BLOCK_USDM, init_phase);
+       bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
 
-       bnx2x_init_block(bp, TSEM_BLOCK, init_stage);
-       bnx2x_init_block(bp, USEM_BLOCK, init_stage);
-       bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
-       bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
+       bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
+       bnx2x_init_block(bp, BLOCK_USEM, init_phase);
+       bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
+       bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
 
-       bnx2x_init_block(bp, UPB_BLOCK, init_stage);
-       bnx2x_init_block(bp, XPB_BLOCK, init_stage);
+       bnx2x_init_block(bp, BLOCK_UPB, init_phase);
+       bnx2x_init_block(bp, BLOCK_XPB, init_phase);
 
-       bnx2x_init_block(bp, PBF_BLOCK, init_stage);
+       bnx2x_init_block(bp, BLOCK_PBF, init_phase);
 
-       /* configure PBF to work without PAUSE mtu 9000 */
-       REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
+       if (CHIP_IS_E1x(bp)) {
+               /* configure PBF to work without PAUSE mtu 9000 */
+               REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
 
-       /* update threshold */
-       REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
-       /* update init credit */
-       REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
+               /* update threshold */
+               REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
+               /* update init credit */
+               REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
 
-       /* probe changes */
-       REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
-       msleep(5);
-       REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
+               /* probe changes */
+               REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
+               udelay(50);
+               REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
+       }
 
 #ifdef BCM_CNIC
-       bnx2x_init_block(bp, SRCH_BLOCK, init_stage);
+       bnx2x_init_block(bp, BLOCK_SRC, init_phase);
 #endif
-       bnx2x_init_block(bp, CDU_BLOCK, init_stage);
-       bnx2x_init_block(bp, CFC_BLOCK, init_stage);
+       bnx2x_init_block(bp, BLOCK_CDU, init_phase);
+       bnx2x_init_block(bp, BLOCK_CFC, init_phase);
 
        if (CHIP_IS_E1(bp)) {
                REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
                REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
        }
-       bnx2x_init_block(bp, HC_BLOCK, init_stage);
+       bnx2x_init_block(bp, BLOCK_HC, init_phase);
 
-       bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage);
+       bnx2x_init_block(bp, BLOCK_IGU, init_phase);
+
+       bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
        /* init aeu_mask_attn_func_0/1:
         *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
         *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
         *             bits 4-7 are used for "per vn group attention" */
-       REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4,
-              (IS_E1HMF(bp) ? 0xF7 : 0x7));
+       val = IS_MF(bp) ? 0xF7 : 0x7;
+       /* Enable DCBX attention for all but E1 */
+       val |= CHIP_IS_E1(bp) ? 0 : 0x10;
+       REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
 
-       bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
-       bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
-       bnx2x_init_block(bp, EMAC1_BLOCK, init_stage);
-       bnx2x_init_block(bp, DBU_BLOCK, init_stage);
-       bnx2x_init_block(bp, DBG_BLOCK, init_stage);
+       bnx2x_init_block(bp, BLOCK_NIG, init_phase);
 
-       bnx2x_init_block(bp, NIG_BLOCK, init_stage);
+       if (!CHIP_IS_E1x(bp)) {
+               /* Bit-map indicating which L2 hdrs may appear after the
+                * basic Ethernet header
+                */
+               REG_WR(bp, BP_PORT(bp) ?
+                          NIG_REG_P1_HDRS_AFTER_BASIC :
+                          NIG_REG_P0_HDRS_AFTER_BASIC,
+                          IS_MF_SD(bp) ? 7 : 6);
 
-       REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
+               if (CHIP_IS_E3(bp))
+                       REG_WR(bp, BP_PORT(bp) ?
+                                  NIG_REG_LLH1_MF_MODE :
+                                  NIG_REG_LLH_MF_MODE, IS_MF(bp));
+       }
+       if (!CHIP_IS_E3(bp))
+               REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
 
-       if (CHIP_IS_E1H(bp)) {
-               /* 0x2 disable e1hov, 0x1 enable */
+       if (!CHIP_IS_E1(bp)) {
+               /* 0x2 disable mf_ov, 0x1 enable */
                REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
-                      (IS_E1HMF(bp) ? 0x1 : 0x2));
+                      (IS_MF_SD(bp) ? 0x1 : 0x2));
+
+               if (!CHIP_IS_E1x(bp)) {
+                       val = 0;
+                       switch (bp->mf_mode) {
+                       case MULTI_FUNCTION_SD:
+                               val = 1;
+                               break;
+                       case MULTI_FUNCTION_SI:
+                               val = 2;
+                               break;
+                       }
 
+                       REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
+                                                 NIG_REG_LLH0_CLS_TYPE), val);
+               }
                {
                        REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
                        REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
@@ -4309,778 +6263,900 @@ static int bnx2x_init_port(struct bnx2x *bp)
                }
        }
 
-       bnx2x_init_block(bp, MCP_BLOCK, init_stage);
-       bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
-       bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
-                                                      bp->common.shmem_base,
-                                                      bp->common.shmem2_base);
-       if (bnx2x_fan_failure_det_req(bp, bp->common.shmem_base,
-                                     bp->common.shmem2_base, port)) {
+
+       /* If SPIO5 is set to generate interrupts, enable it for this port */
+       val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
+       if (val & (1 << MISC_REGISTERS_SPIO_5)) {
                u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
                                       MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
                val = REG_RD(bp, reg_addr);
                val |= AEU_INPUTS_ATTN_BITS_SPIO5;
                REG_WR(bp, reg_addr, val);
        }
-       bnx2x__link_reset(bp);
 
        return 0;
 }
 
-#define ILT_PER_FUNC           (768/2)
-#define FUNC_ILT_BASE(func)    (func * ILT_PER_FUNC)
-/* the phys address is shifted right 12 bits and has an added
-   1=valid bit added to the 53rd bit
-   then since this is a wide register(TM)
-   we split it into two 32 bit writes
- */
-#define ONCHIP_ADDR1(x)                ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
-#define ONCHIP_ADDR2(x)                ((u32)((1 << 20) | ((u64)x >> 44)))
-#define PXP_ONE_ILT(x)         (((x) << 10) | x)
-#define PXP_ILT_RANGE(f, l)    (((l) << 10) | f)
-
-#ifdef BCM_CNIC
-#define CNIC_ILT_LINES         127
-#define CNIC_CTX_PER_ILT       16
-#else
-#define CNIC_ILT_LINES         0
-#endif
-
 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
 {
        int reg;
 
-       if (CHIP_IS_E1H(bp))
-               reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
-       else /* E1 */
+       if (CHIP_IS_E1(bp))
                reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
+       else
+               reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
 
        bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
 }
 
-static int bnx2x_init_func(struct bnx2x *bp)
+static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
+{
+       bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
+}
+
+static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
+{
+       u32 i, base = FUNC_ILT_BASE(func);
+       for (i = base; i < base + ILT_PER_FUNC; i++)
+               bnx2x_ilt_wr(bp, i, 0);
+}
+
+static int bnx2x_init_hw_func(struct bnx2x *bp)
 {
        int port = BP_PORT(bp);
        int func = BP_FUNC(bp);
+       int init_phase = PHASE_PF0 + func;
+       struct bnx2x_ilt *ilt = BP_ILT(bp);
+       u16 cdu_ilt_start;
        u32 addr, val;
-       int i;
+       u32 main_mem_base, main_mem_size, main_mem_prty_clr;
+       int i, main_mem_width;
 
        DP(BNX2X_MSG_MCP, "starting func init  func %d\n", func);
 
-       /* set MSI reconfigure capability */
-       addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
-       val = REG_RD(bp, addr);
-       val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
-       REG_WR(bp, addr, val);
+       /* FLR cleanup - hmmm */
+       if (!CHIP_IS_E1x(bp))
+               bnx2x_pf_flr_clnup(bp);
 
-       i = FUNC_ILT_BASE(func);
+       /* set MSI reconfigure capability */
+       if (bp->common.int_block == INT_BLOCK_HC) {
+               addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
+               val = REG_RD(bp, addr);
+               val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
+               REG_WR(bp, addr, val);
+       }
 
-       bnx2x_ilt_wr(bp, i, bnx2x_sp_mapping(bp, context));
-       if (CHIP_IS_E1H(bp)) {
-               REG_WR(bp, PXP2_REG_RQ_CDU_FIRST_ILT, i);
-               REG_WR(bp, PXP2_REG_RQ_CDU_LAST_ILT, i + CNIC_ILT_LINES);
-       } else /* E1 */
-               REG_WR(bp, PXP2_REG_PSWRQ_CDU0_L2P + func*4,
-                      PXP_ILT_RANGE(i, i + CNIC_ILT_LINES));
+       bnx2x_init_block(bp, BLOCK_PXP, init_phase);
+       bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
 
-#ifdef BCM_CNIC
-       i += 1 + CNIC_ILT_LINES;
-       bnx2x_ilt_wr(bp, i, bp->timers_mapping);
-       if (CHIP_IS_E1(bp))
-               REG_WR(bp, PXP2_REG_PSWRQ_TM0_L2P + func*4, PXP_ONE_ILT(i));
-       else {
-               REG_WR(bp, PXP2_REG_RQ_TM_FIRST_ILT, i);
-               REG_WR(bp, PXP2_REG_RQ_TM_LAST_ILT, i);
-       }
+       ilt = BP_ILT(bp);
+       cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
 
-       i++;
-       bnx2x_ilt_wr(bp, i, bp->qm_mapping);
-       if (CHIP_IS_E1(bp))
-               REG_WR(bp, PXP2_REG_PSWRQ_QM0_L2P + func*4, PXP_ONE_ILT(i));
-       else {
-               REG_WR(bp, PXP2_REG_RQ_QM_FIRST_ILT, i);
-               REG_WR(bp, PXP2_REG_RQ_QM_LAST_ILT, i);
+       for (i = 0; i < L2_ILT_LINES(bp); i++) {
+               ilt->lines[cdu_ilt_start + i].page =
+                       bp->context.vcxt + (ILT_PAGE_CIDS * i);
+               ilt->lines[cdu_ilt_start + i].page_mapping =
+                       bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
+               /* cdu ilt pages are allocated manually so there's no need to
+               set the size */
        }
+       bnx2x_ilt_init_op(bp, INITOP_SET);
 
-       i++;
-       bnx2x_ilt_wr(bp, i, bp->t1_mapping);
-       if (CHIP_IS_E1(bp))
-               REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i));
-       else {
-               REG_WR(bp, PXP2_REG_RQ_SRC_FIRST_ILT, i);
-               REG_WR(bp, PXP2_REG_RQ_SRC_LAST_ILT, i);
-       }
+#ifdef BCM_CNIC
+       bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
 
-       /* tell the searcher where the T2 table is */
-       REG_WR(bp, SRC_REG_COUNTFREE0 + port*4, 16*1024/64);
+       /* T1 hash bits value determines the T1 number of entries */
+       REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
+#endif
 
-       bnx2x_wb_wr(bp, SRC_REG_FIRSTFREE0 + port*16,
-                   U64_LO(bp->t2_mapping), U64_HI(bp->t2_mapping));
+#ifndef BCM_CNIC
+       /* set NIC mode */
+       REG_WR(bp, PRS_REG_NIC_MODE, 1);
+#endif  /* BCM_CNIC */
 
-       bnx2x_wb_wr(bp, SRC_REG_LASTFREE0 + port*16,
-                   U64_LO((u64)bp->t2_mapping + 16*1024 - 64),
-                   U64_HI((u64)bp->t2_mapping + 16*1024 - 64));
+       if (!CHIP_IS_E1x(bp)) {
+               u32 pf_conf = IGU_PF_CONF_FUNC_EN;
 
-       REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, 10);
-#endif
+               /* Turn on a single ISR mode in IGU if driver is going to use
+                * INT#x or MSI
+                */
+               if (!(bp->flags & USING_MSIX_FLAG))
+                       pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
+               /*
+                * Timers workaround bug: function init part.
+                * Need to wait 20msec after initializing ILT,
+                * needed to make sure there are no requests in
+                * one of the PXP internal queues with "old" ILT addresses
+                */
+               msleep(20);
+               /*
+                * Master enable - Due to WB DMAE writes performed before this
+                * register is re-initialized as part of the regular function
+                * init
+                */
+               REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
+               /* Enable the function in IGU */
+               REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
+       }
 
-       if (CHIP_IS_E1H(bp)) {
-               bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func);
-               bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func);
-               bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func);
-               bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func);
-               bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func);
-               bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func);
-               bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func);
-               bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func);
-               bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func);
+       bp->dmae_ready = 1;
 
+       bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
+
+       if (!CHIP_IS_E1x(bp))
+               REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
+
+       bnx2x_init_block(bp, BLOCK_ATC, init_phase);
+       bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
+       bnx2x_init_block(bp, BLOCK_NIG, init_phase);
+       bnx2x_init_block(bp, BLOCK_SRC, init_phase);
+       bnx2x_init_block(bp, BLOCK_MISC, init_phase);
+       bnx2x_init_block(bp, BLOCK_TCM, init_phase);
+       bnx2x_init_block(bp, BLOCK_UCM, init_phase);
+       bnx2x_init_block(bp, BLOCK_CCM, init_phase);
+       bnx2x_init_block(bp, BLOCK_XCM, init_phase);
+       bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
+       bnx2x_init_block(bp, BLOCK_USEM, init_phase);
+       bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
+       bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
+
+       if (!CHIP_IS_E1x(bp))
+               REG_WR(bp, QM_REG_PF_EN, 1);
+
+       if (!CHIP_IS_E1x(bp)) {
+               REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
+               REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
+               REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
+               REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
+       }
+       bnx2x_init_block(bp, BLOCK_QM, init_phase);
+
+       bnx2x_init_block(bp, BLOCK_TM, init_phase);
+       bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
+       bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
+       bnx2x_init_block(bp, BLOCK_PRS, init_phase);
+       bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
+       bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
+       bnx2x_init_block(bp, BLOCK_USDM, init_phase);
+       bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
+       bnx2x_init_block(bp, BLOCK_UPB, init_phase);
+       bnx2x_init_block(bp, BLOCK_XPB, init_phase);
+       bnx2x_init_block(bp, BLOCK_PBF, init_phase);
+       if (!CHIP_IS_E1x(bp))
+               REG_WR(bp, PBF_REG_DISABLE_PF, 0);
+
+       bnx2x_init_block(bp, BLOCK_CDU, init_phase);
+
+       bnx2x_init_block(bp, BLOCK_CFC, init_phase);
+
+       if (!CHIP_IS_E1x(bp))
+               REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
+
+       if (IS_MF(bp)) {
                REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
-               REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->e1hov);
+               REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
        }
 
+       bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
+
        /* HC init per function */
-       if (CHIP_IS_E1H(bp)) {
+       if (bp->common.int_block == INT_BLOCK_HC) {
+               if (CHIP_IS_E1H(bp)) {
+                       REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
+
+                       REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
+                       REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
+               }
+               bnx2x_init_block(bp, BLOCK_HC, init_phase);
+
+       } else {
+               int num_segs, sb_idx, prod_offset;
+
                REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
 
-               REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
-               REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
+               if (!CHIP_IS_E1x(bp)) {
+                       REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
+                       REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
+               }
+
+               bnx2x_init_block(bp, BLOCK_IGU, init_phase);
+
+               if (!CHIP_IS_E1x(bp)) {
+                       int dsb_idx = 0;
+                       /**
+                        * Producer memory:
+                        * E2 mode: address 0-135 match to the mapping memory;
+                        * 136 - PF0 default prod; 137 - PF1 default prod;
+                        * 138 - PF2 default prod; 139 - PF3 default prod;
+                        * 140 - PF0 attn prod;    141 - PF1 attn prod;
+                        * 142 - PF2 attn prod;    143 - PF3 attn prod;
+                        * 144-147 reserved.
+                        *
+                        * E1.5 mode - In backward compatible mode;
+                        * for non default SB; each even line in the memory
+                        * holds the U producer and each odd line hold
+                        * the C producer. The first 128 producers are for
+                        * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
+                        * producers are for the DSB for each PF.
+                        * Each PF has five segments: (the order inside each
+                        * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
+                        * 132-135 C prods; 136-139 X prods; 140-143 T prods;
+                        * 144-147 attn prods;
+                        */
+                       /* non-default-status-blocks */
+                       num_segs = CHIP_INT_MODE_IS_BC(bp) ?
+                               IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
+                       for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
+                               prod_offset = (bp->igu_base_sb + sb_idx) *
+                                       num_segs;
+
+                               for (i = 0; i < num_segs; i++) {
+                                       addr = IGU_REG_PROD_CONS_MEMORY +
+                                                       (prod_offset + i) * 4;
+                                       REG_WR(bp, addr, 0);
+                               }
+                               /* send consumer update with value 0 */
+                               bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
+                                            USTORM_ID, 0, IGU_INT_NOP, 1);
+                               bnx2x_igu_clear_sb(bp,
+                                                  bp->igu_base_sb + sb_idx);
+                       }
+
+                       /* default-status-blocks */
+                       num_segs = CHIP_INT_MODE_IS_BC(bp) ?
+                               IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
+
+                       if (CHIP_MODE_IS_4_PORT(bp))
+                               dsb_idx = BP_FUNC(bp);
+                       else
+                               dsb_idx = BP_E1HVN(bp);
+
+                       prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
+                                      IGU_BC_BASE_DSB_PROD + dsb_idx :
+                                      IGU_NORM_BASE_DSB_PROD + dsb_idx);
+
+                       for (i = 0; i < (num_segs * E1HVN_MAX);
+                            i += E1HVN_MAX) {
+                               addr = IGU_REG_PROD_CONS_MEMORY +
+                                                       (prod_offset + i)*4;
+                               REG_WR(bp, addr, 0);
+                       }
+                       /* send consumer update with 0 */
+                       if (CHIP_INT_MODE_IS_BC(bp)) {
+                               bnx2x_ack_sb(bp, bp->igu_dsb_id,
+                                            USTORM_ID, 0, IGU_INT_NOP, 1);
+                               bnx2x_ack_sb(bp, bp->igu_dsb_id,
+                                            CSTORM_ID, 0, IGU_INT_NOP, 1);
+                               bnx2x_ack_sb(bp, bp->igu_dsb_id,
+                                            XSTORM_ID, 0, IGU_INT_NOP, 1);
+                               bnx2x_ack_sb(bp, bp->igu_dsb_id,
+                                            TSTORM_ID, 0, IGU_INT_NOP, 1);
+                               bnx2x_ack_sb(bp, bp->igu_dsb_id,
+                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
+                       } else {
+                               bnx2x_ack_sb(bp, bp->igu_dsb_id,
+                                            USTORM_ID, 0, IGU_INT_NOP, 1);
+                               bnx2x_ack_sb(bp, bp->igu_dsb_id,
+                                            ATTENTION_ID, 0, IGU_INT_NOP, 1);
+                       }
+                       bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
+
+                       /* !!! these should become driver const once
+                          rf-tool supports split-68 const */
+                       REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
+                       REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
+                       REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
+                       REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
+                       REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
+                       REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
+               }
        }
-       bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
 
        /* Reset PCIE errors for debug */
        REG_WR(bp, 0x2114, 0xffffffff);
        REG_WR(bp, 0x2120, 0xffffffff);
+
+       if (CHIP_IS_E1x(bp)) {
+               main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
+               main_mem_base = HC_REG_MAIN_MEMORY +
+                               BP_PORT(bp) * (main_mem_size * 4);
+               main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
+               main_mem_width = 8;
+
+               val = REG_RD(bp, main_mem_prty_clr);
+               if (val)
+                       DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
+                                         "block during "
+                                         "function init (0x%x)!\n", val);
+
+               /* Clear "false" parity errors in MSI-X table */
+               for (i = main_mem_base;
+                    i < main_mem_base + main_mem_size * 4;
+                    i += main_mem_width) {
+                       bnx2x_read_dmae(bp, i, main_mem_width / 4);
+                       bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
+                                        i, main_mem_width / 4);
+               }
+               /* Clear HC parity attention */
+               REG_RD(bp, main_mem_prty_clr);
+       }
+
+#ifdef BNX2X_STOP_ON_ERROR
+       /* Enable STORMs SP logging */
+       REG_WR8(bp, BAR_USTRORM_INTMEM +
+              USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
+       REG_WR8(bp, BAR_TSTRORM_INTMEM +
+              TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
+       REG_WR8(bp, BAR_CSTRORM_INTMEM +
+              CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
+       REG_WR8(bp, BAR_XSTRORM_INTMEM +
+              XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
+#endif
+
        bnx2x_phy_probe(&bp->link_params);
+
        return 0;
 }
 
-int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
-{
-       int i, rc = 0;
 
-       DP(BNX2X_MSG_MCP, "function %d  load_code %x\n",
-          BP_FUNC(bp), load_code);
-
-       bp->dmae_ready = 0;
-       mutex_init(&bp->dmae_mutex);
-       rc = bnx2x_gunzip_init(bp);
-       if (rc)
-               return rc;
+void bnx2x_free_mem(struct bnx2x *bp)
+{
+       /* fastpath */
+       bnx2x_free_fp_mem(bp);
+       /* end of fastpath */
 
-       switch (load_code) {
-       case FW_MSG_CODE_DRV_LOAD_COMMON:
-               rc = bnx2x_init_common(bp);
-               if (rc)
-                       goto init_hw_err;
-               /* no break */
+       BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
+                      sizeof(struct host_sp_status_block));
 
-       case FW_MSG_CODE_DRV_LOAD_PORT:
-               bp->dmae_ready = 1;
-               rc = bnx2x_init_port(bp);
-               if (rc)
-                       goto init_hw_err;
-               /* no break */
+       BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
+                      bp->fw_stats_data_sz + bp->fw_stats_req_sz);
 
-       case FW_MSG_CODE_DRV_LOAD_FUNCTION:
-               bp->dmae_ready = 1;
-               rc = bnx2x_init_func(bp);
-               if (rc)
-                       goto init_hw_err;
-               break;
+       BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
+                      sizeof(struct bnx2x_slowpath));
 
-       default:
-               BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
-               break;
-       }
+       BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
+                      bp->context.size);
 
-       if (!BP_NOMCP(bp)) {
-               int func = BP_FUNC(bp);
+       bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
 
-               bp->fw_drv_pulse_wr_seq =
-                               (SHMEM_RD(bp, func_mb[func].drv_pulse_mb) &
-                                DRV_PULSE_SEQ_MASK);
-               DP(BNX2X_MSG_MCP, "drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
-       }
+       BNX2X_FREE(bp->ilt->lines);
 
-       /* this needs to be done before gunzip end */
-       bnx2x_zero_def_sb(bp);
-       for_each_queue(bp, i)
-               bnx2x_zero_sb(bp, BP_L_ID(bp) + i);
 #ifdef BCM_CNIC
-       bnx2x_zero_sb(bp, BP_L_ID(bp) + i);
+       if (!CHIP_IS_E1x(bp))
+               BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
+                              sizeof(struct host_hc_status_block_e2));
+       else
+               BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
+                              sizeof(struct host_hc_status_block_e1x));
+
+       BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
 #endif
 
-init_hw_err:
-       bnx2x_gunzip_end(bp);
+       BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
 
-       return rc;
+       BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
+                      BCM_PAGE_SIZE * NUM_EQ_PAGES);
 }
 
-void bnx2x_free_mem(struct bnx2x *bp)
+static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
 {
+       int num_groups;
 
-#define BNX2X_PCI_FREE(x, y, size) \
-       do { \
-               if (x) { \
-                       dma_free_coherent(&bp->pdev->dev, size, x, y); \
-                       x = NULL; \
-                       y = 0; \
-               } \
-       } while (0)
-
-#define BNX2X_FREE(x) \
-       do { \
-               if (x) { \
-                       vfree(x); \
-                       x = NULL; \
-               } \
-       } while (0)
-
-       int i;
+       /* number of eth_queues */
+       u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp);
 
-       /* fastpath */
-       /* Common */
-       for_each_queue(bp, i) {
+       /* Total number of FW statistics requests =
+        * 1 for port stats + 1 for PF stats + num_eth_queues */
+       bp->fw_stats_num = 2 + num_queue_stats;
 
-               /* status blocks */
-               BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk),
-                              bnx2x_fp(bp, i, status_blk_mapping),
-                              sizeof(struct host_status_block));
-       }
-       /* Rx */
-       for_each_queue(bp, i) {
 
-               /* fastpath rx rings: rx_buf rx_desc rx_comp */
-               BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));
-               BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),
-                              bnx2x_fp(bp, i, rx_desc_mapping),
-                              sizeof(struct eth_rx_bd) * NUM_RX_BD);
+       /* Request is built from stats_query_header and an array of
+        * stats_query_cmd_group each of which contains
+        * STATS_QUERY_CMD_COUNT rules. The real number or requests is
+        * configured in the stats_query_header.
+        */
+       num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT +
+               (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
 
-               BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),
-                              bnx2x_fp(bp, i, rx_comp_mapping),
-                              sizeof(struct eth_fast_path_rx_cqe) *
-                              NUM_RCQ_BD);
+       bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
+                       num_groups * sizeof(struct stats_query_cmd_group);
 
-               /* SGE ring */
-               BNX2X_FREE(bnx2x_fp(bp, i, rx_page_ring));
-               BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring),
-                              bnx2x_fp(bp, i, rx_sge_mapping),
-                              BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
-       }
-       /* Tx */
-       for_each_queue(bp, i) {
+       /* Data for statistics requests + stats_conter
+        *
+        * stats_counter holds per-STORM counters that are incremented
+        * when STORM has finished with the current request.
+        */
+       bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
+               sizeof(struct per_pf_stats) +
+               sizeof(struct per_queue_stats) * num_queue_stats +
+               sizeof(struct stats_counter);
 
-               /* fastpath tx rings: tx_buf tx_desc */
-               BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
-               BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
-                              bnx2x_fp(bp, i, tx_desc_mapping),
-                              sizeof(union eth_tx_bd_types) * NUM_TX_BD);
-       }
-       /* end of fastpath */
+       BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
+                       bp->fw_stats_data_sz + bp->fw_stats_req_sz);
 
-       BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
-                      sizeof(struct host_def_status_block));
+       /* Set shortcuts */
+       bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
+       bp->fw_stats_req_mapping = bp->fw_stats_mapping;
 
-       BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
-                      sizeof(struct bnx2x_slowpath));
+       bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
+               ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
 
-#ifdef BCM_CNIC
-       BNX2X_PCI_FREE(bp->t1, bp->t1_mapping, 64*1024);
-       BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, 16*1024);
-       BNX2X_PCI_FREE(bp->timers, bp->timers_mapping, 8*1024);
-       BNX2X_PCI_FREE(bp->qm, bp->qm_mapping, 128*1024);
-       BNX2X_PCI_FREE(bp->cnic_sb, bp->cnic_sb_mapping,
-                      sizeof(struct host_status_block));
-#endif
-       BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
+       bp->fw_stats_data_mapping = bp->fw_stats_mapping +
+                                  bp->fw_stats_req_sz;
+       return 0;
 
-#undef BNX2X_PCI_FREE
-#undef BNX2X_KFREE
+alloc_mem_err:
+       BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
+                      bp->fw_stats_data_sz + bp->fw_stats_req_sz);
+       return -ENOMEM;
 }
 
+
 int bnx2x_alloc_mem(struct bnx2x *bp)
 {
+#ifdef BCM_CNIC
+       if (!CHIP_IS_E1x(bp))
+               /* size = the status block + ramrod buffers */
+               BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
+                               sizeof(struct host_hc_status_block_e2));
+       else
+               BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
+                               sizeof(struct host_hc_status_block_e1x));
 
-#define BNX2X_PCI_ALLOC(x, y, size) \
-       do { \
-               x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
-               if (x == NULL) \
-                       goto alloc_mem_err; \
-               memset(x, 0, size); \
-       } while (0)
-
-#define BNX2X_ALLOC(x, size) \
-       do { \
-               x = vmalloc(size); \
-               if (x == NULL) \
-                       goto alloc_mem_err; \
-               memset(x, 0, size); \
-       } while (0)
-
-       int i;
-
-       /* fastpath */
-       /* Common */
-       for_each_queue(bp, i) {
-               bnx2x_fp(bp, i, bp) = bp;
-
-               /* status blocks */
-               BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, status_blk),
-                               &bnx2x_fp(bp, i, status_blk_mapping),
-                               sizeof(struct host_status_block));
-       }
-       /* Rx */
-       for_each_queue(bp, i) {
-
-               /* fastpath rx rings: rx_buf rx_desc rx_comp */
-               BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),
-                               sizeof(struct sw_rx_bd) * NUM_RX_BD);
-               BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),
-                               &bnx2x_fp(bp, i, rx_desc_mapping),
-                               sizeof(struct eth_rx_bd) * NUM_RX_BD);
-
-               BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),
-                               &bnx2x_fp(bp, i, rx_comp_mapping),
-                               sizeof(struct eth_fast_path_rx_cqe) *
-                               NUM_RCQ_BD);
-
-               /* SGE ring */
-               BNX2X_ALLOC(bnx2x_fp(bp, i, rx_page_ring),
-                               sizeof(struct sw_rx_page) * NUM_RX_SGE);
-               BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_sge_ring),
-                               &bnx2x_fp(bp, i, rx_sge_mapping),
-                               BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
-       }
-       /* Tx */
-       for_each_queue(bp, i) {
+       /* allocate searcher T2 table */
+       BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
+#endif
 
-               /* fastpath tx rings: tx_buf tx_desc */
-               BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
-                               sizeof(struct sw_tx_bd) * NUM_TX_BD);
-               BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
-                               &bnx2x_fp(bp, i, tx_desc_mapping),
-                               sizeof(union eth_tx_bd_types) * NUM_TX_BD);
-       }
-       /* end of fastpath */
 
        BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
-                       sizeof(struct host_def_status_block));
+                       sizeof(struct host_sp_status_block));
 
        BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
                        sizeof(struct bnx2x_slowpath));
 
-#ifdef BCM_CNIC
-       BNX2X_PCI_ALLOC(bp->t1, &bp->t1_mapping, 64*1024);
+       /* Allocated memory for FW statistics  */
+       if (bnx2x_alloc_fw_stats_mem(bp))
+               goto alloc_mem_err;
 
-       /* allocate searcher T2 table
-          we allocate 1/4 of alloc num for T2
-         (which is not entered into the ILT) */
-       BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, 16*1024);
+       bp->context.size = sizeof(union cdu_context) * bp->l2_cid_count;
 
-       /* Initialize T2 (for 1024 connections) */
-       for (i = 0; i < 16*1024; i += 64)
-               *(u64 *)((char *)bp->t2 + i + 56) = bp->t2_mapping + i + 64;
+       BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
+                       bp->context.size);
 
-       /* Timer block array (8*MAX_CONN) phys uncached for now 1024 conns */
-       BNX2X_PCI_ALLOC(bp->timers, &bp->timers_mapping, 8*1024);
+       BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
 
-       /* QM queues (128*MAX_CONN) */
-       BNX2X_PCI_ALLOC(bp->qm, &bp->qm_mapping, 128*1024);
-
-       BNX2X_PCI_ALLOC(bp->cnic_sb, &bp->cnic_sb_mapping,
-                       sizeof(struct host_status_block));
-#endif
+       if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
+               goto alloc_mem_err;
 
        /* Slow path ring */
        BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
 
+       /* EQ */
+       BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
+                       BCM_PAGE_SIZE * NUM_EQ_PAGES);
+
+
+       /* fastpath */
+       /* need to be done at the end, since it's self adjusting to amount
+        * of memory available for RSS queues
+        */
+       if (bnx2x_alloc_fp_mem(bp))
+               goto alloc_mem_err;
        return 0;
 
 alloc_mem_err:
        bnx2x_free_mem(bp);
        return -ENOMEM;
-
-#undef BNX2X_PCI_ALLOC
-#undef BNX2X_ALLOC
 }
 
-
 /*
  * Init service functions
  */
 
-/**
- * Sets a MAC in a CAM for a few L2 Clients for E1 chip
- *
- * @param bp driver descriptor
- * @param set set or clear an entry (1 or 0)
- * @param mac pointer to a buffer containing a MAC
- * @param cl_bit_vec bit vector of clients to register a MAC for
- * @param cam_offset offset in a CAM to use
- * @param with_bcast set broadcast MAC as well
- */
-static void bnx2x_set_mac_addr_e1_gen(struct bnx2x *bp, int set, u8 *mac,
-                                     u32 cl_bit_vec, u8 cam_offset,
-                                     u8 with_bcast)
+int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
+                     struct bnx2x_vlan_mac_obj *obj, bool set,
+                     int mac_type, unsigned long *ramrod_flags)
 {
-       struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
-       int port = BP_PORT(bp);
+       int rc;
+       struct bnx2x_vlan_mac_ramrod_params ramrod_param;
 
-       /* CAM allocation
-        * unicasts 0-31:port0 32-63:port1
-        * multicast 64-127:port0 128-191:port1
-        */
-       config->hdr.length = 1 + (with_bcast ? 1 : 0);
-       config->hdr.offset = cam_offset;
-       config->hdr.client_id = 0xff;
-       config->hdr.reserved1 = 0;
-
-       /* primary MAC */
-       config->config_table[0].cam_entry.msb_mac_addr =
-                                       swab16(*(u16 *)&mac[0]);
-       config->config_table[0].cam_entry.middle_mac_addr =
-                                       swab16(*(u16 *)&mac[2]);
-       config->config_table[0].cam_entry.lsb_mac_addr =
-                                       swab16(*(u16 *)&mac[4]);
-       config->config_table[0].cam_entry.flags = cpu_to_le16(port);
-       if (set)
-               config->config_table[0].target_table_entry.flags = 0;
-       else
-               CAM_INVALIDATE(config->config_table[0]);
-       config->config_table[0].target_table_entry.clients_bit_vector =
-                                               cpu_to_le32(cl_bit_vec);
-       config->config_table[0].target_table_entry.vlan_id = 0;
-
-       DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x)\n",
-          (set ? "setting" : "clearing"),
-          config->config_table[0].cam_entry.msb_mac_addr,
-          config->config_table[0].cam_entry.middle_mac_addr,
-          config->config_table[0].cam_entry.lsb_mac_addr);
-
-       /* broadcast */
-       if (with_bcast) {
-               config->config_table[1].cam_entry.msb_mac_addr =
-                       cpu_to_le16(0xffff);
-               config->config_table[1].cam_entry.middle_mac_addr =
-                       cpu_to_le16(0xffff);
-               config->config_table[1].cam_entry.lsb_mac_addr =
-                       cpu_to_le16(0xffff);
-               config->config_table[1].cam_entry.flags = cpu_to_le16(port);
-               if (set)
-                       config->config_table[1].target_table_entry.flags =
-                                       TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST;
-               else
-                       CAM_INVALIDATE(config->config_table[1]);
-               config->config_table[1].target_table_entry.clients_bit_vector =
-                                                       cpu_to_le32(cl_bit_vec);
-               config->config_table[1].target_table_entry.vlan_id = 0;
-       }
+       memset(&ramrod_param, 0, sizeof(ramrod_param));
 
-       bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
-                     U64_HI(bnx2x_sp_mapping(bp, mac_config)),
-                     U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
-}
+       /* Fill general parameters */
+       ramrod_param.vlan_mac_obj = obj;
+       ramrod_param.ramrod_flags = *ramrod_flags;
 
-/**
- * Sets a MAC in a CAM for a few L2 Clients for E1H chip
- *
- * @param bp driver descriptor
- * @param set set or clear an entry (1 or 0)
- * @param mac pointer to a buffer containing a MAC
- * @param cl_bit_vec bit vector of clients to register a MAC for
- * @param cam_offset offset in a CAM to use
- */
-static void bnx2x_set_mac_addr_e1h_gen(struct bnx2x *bp, int set, u8 *mac,
-                                      u32 cl_bit_vec, u8 cam_offset)
-{
-       struct mac_configuration_cmd_e1h *config =
-               (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config);
-
-       config->hdr.length = 1;
-       config->hdr.offset = cam_offset;
-       config->hdr.client_id = 0xff;
-       config->hdr.reserved1 = 0;
-
-       /* primary MAC */
-       config->config_table[0].msb_mac_addr =
-                                       swab16(*(u16 *)&mac[0]);
-       config->config_table[0].middle_mac_addr =
-                                       swab16(*(u16 *)&mac[2]);
-       config->config_table[0].lsb_mac_addr =
-                                       swab16(*(u16 *)&mac[4]);
-       config->config_table[0].clients_bit_vector =
-                                       cpu_to_le32(cl_bit_vec);
-       config->config_table[0].vlan_id = 0;
-       config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov);
-       if (set)
-               config->config_table[0].flags = BP_PORT(bp);
-       else
-               config->config_table[0].flags =
-                               MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE;
+       /* Fill a user request section if needed */
+       if (!test_bit(RAMROD_CONT, ramrod_flags)) {
+               memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
 
-       DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x)  E1HOV %d  CLID mask %d\n",
-          (set ? "setting" : "clearing"),
-          config->config_table[0].msb_mac_addr,
-          config->config_table[0].middle_mac_addr,
-          config->config_table[0].lsb_mac_addr, bp->e1hov, cl_bit_vec);
+               __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
 
-       bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
-                     U64_HI(bnx2x_sp_mapping(bp, mac_config)),
-                     U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
+               /* Set the command: ADD or DEL */
+               if (set)
+                       ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
+               else
+                       ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
+       }
+
+       rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
+       if (rc < 0)
+               BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
+       return rc;
 }
 
-static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
-                            int *state_p, int poll)
+int bnx2x_del_all_macs(struct bnx2x *bp,
+                      struct bnx2x_vlan_mac_obj *mac_obj,
+                      int mac_type, bool wait_for_comp)
 {
-       /* can take a while if any port is running */
-       int cnt = 5000;
-
-       DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
-          poll ? "polling" : "waiting", state, idx);
-
-       might_sleep();
-       while (cnt--) {
-               if (poll) {
-                       bnx2x_rx_int(bp->fp, 10);
-                       /* if index is different from 0
-                        * the reply for some commands will
-                        * be on the non default queue
-                        */
-                       if (idx)
-                               bnx2x_rx_int(&bp->fp[idx], 10);
-               }
-
-               mb(); /* state is changed by bnx2x_sp_event() */
-               if (*state_p == state) {
-#ifdef BNX2X_STOP_ON_ERROR
-                       DP(NETIF_MSG_IFUP, "exit  (cnt %d)\n", 5000 - cnt);
-#endif
-                       return 0;
-               }
+       int rc;
+       unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
 
-               msleep(1);
+       /* Wait for completion of requested */
+       if (wait_for_comp)
+               __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
 
-               if (bp->panic)
-                       return -EIO;
-       }
+       /* Set the mac type of addresses we want to clear */
+       __set_bit(mac_type, &vlan_mac_flags);
 
-       /* timeout! */
-       BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
-                 poll ? "polling" : "waiting", state, idx);
-#ifdef BNX2X_STOP_ON_ERROR
-       bnx2x_panic();
-#endif
+       rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
+       if (rc < 0)
+               BNX2X_ERR("Failed to delete MACs: %d\n", rc);
 
-       return -EBUSY;
+       return rc;
 }
 
-void bnx2x_set_eth_mac_addr_e1h(struct bnx2x *bp, int set)
+int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
 {
-       bp->set_mac_pending++;
-       smp_wmb();
+       unsigned long ramrod_flags = 0;
 
-       bnx2x_set_mac_addr_e1h_gen(bp, set, bp->dev->dev_addr,
-                                  (1 << bp->fp->cl_id), BP_FUNC(bp));
+       DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
 
-       /* Wait for a completion */
-       bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, set ? 0 : 1);
+       __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
+       /* Eth MAC is set on RSS leading client (fp[0]) */
+       return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
+                                BNX2X_ETH_MAC, &ramrod_flags);
 }
 
-void bnx2x_set_eth_mac_addr_e1(struct bnx2x *bp, int set)
+int bnx2x_setup_leading(struct bnx2x *bp)
 {
-       bp->set_mac_pending++;
-       smp_wmb();
-
-       bnx2x_set_mac_addr_e1_gen(bp, set, bp->dev->dev_addr,
-                                 (1 << bp->fp->cl_id), (BP_PORT(bp) ? 32 : 0),
-                                 1);
-
-       /* Wait for a completion */
-       bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, set ? 0 : 1);
+       return bnx2x_setup_queue(bp, &bp->fp[0], 1);
 }
 
-#ifdef BCM_CNIC
 /**
- * Set iSCSI MAC(s) at the next enties in the CAM after the ETH
- * MAC(s). This function will wait until the ramdord completion
- * returns.
+ * bnx2x_set_int_mode - configure interrupt mode
  *
- * @param bp driver handle
- * @param set set or clear the CAM entry
+ * @bp:                driver handle
  *
- * @return 0 if cussess, -ENODEV if ramrod doesn't return.
+ * In case of MSI-X it will also try to enable MSI-X.
  */
-int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set)
-{
-       u32 cl_bit_vec = (1 << BCM_ISCSI_ETH_CL_ID);
+static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
+{
+       switch (int_mode) {
+       case INT_MODE_MSI:
+               bnx2x_enable_msi(bp);
+               /* falling through... */
+       case INT_MODE_INTx:
+               bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
+               DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
+               break;
+       default:
+               /* Set number of queues according to bp->multi_mode value */
+               bnx2x_set_num_queues(bp);
 
-       bp->set_mac_pending++;
-       smp_wmb();
+               DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
+                  bp->num_queues);
 
-       /* Send a SET_MAC ramrod */
-       if (CHIP_IS_E1(bp))
-               bnx2x_set_mac_addr_e1_gen(bp, set, bp->iscsi_mac,
-                                 cl_bit_vec, (BP_PORT(bp) ? 32 : 0) + 2,
-                                 1);
-       else
-               /* CAM allocation for E1H
-               * unicasts: by func number
-               * multicast: 20+FUNC*20, 20 each
-               */
-               bnx2x_set_mac_addr_e1h_gen(bp, set, bp->iscsi_mac,
-                                  cl_bit_vec, E1H_FUNC_MAX + BP_FUNC(bp));
-
-       /* Wait for a completion when setting */
-       bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, set ? 0 : 1);
+               /* if we can't use MSI-X we only need one fp,
+                * so try to enable MSI-X with the requested number of fp's
+                * and fallback to MSI or legacy INTx with one fp
+                */
+               if (bnx2x_enable_msix(bp)) {
+                       /* failed to enable MSI-X */
+                       if (bp->multi_mode)
+                               DP(NETIF_MSG_IFUP,
+                                         "Multi requested but failed to "
+                                         "enable MSI-X (%d), "
+                                         "set number of queues to %d\n",
+                                  bp->num_queues,
+                                  1 + NONE_ETH_CONTEXT_USE);
+                       bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
+
+                       /* Try to enable MSI */
+                       if (!(bp->flags & DISABLE_MSI_FLAG))
+                               bnx2x_enable_msi(bp);
+               }
+               break;
+       }
+}
 
-       return 0;
+/* must be called prioir to any HW initializations */
+static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
+{
+       return L2_ILT_LINES(bp);
 }
-#endif
 
-int bnx2x_setup_leading(struct bnx2x *bp)
+void bnx2x_ilt_set_info(struct bnx2x *bp)
 {
-       int rc;
+       struct ilt_client_info *ilt_client;
+       struct bnx2x_ilt *ilt = BP_ILT(bp);
+       u16 line = 0;
 
-       /* reset IGU state */
-       bnx2x_ack_sb(bp, bp->fp[0].sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
+       ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
+       DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
 
-       /* SETUP ramrod */
-       bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_SETUP, 0, 0, 0, 0);
+       /* CDU */
+       ilt_client = &ilt->clients[ILT_CLIENT_CDU];
+       ilt_client->client_num = ILT_CLIENT_CDU;
+       ilt_client->page_size = CDU_ILT_PAGE_SZ;
+       ilt_client->flags = ILT_CLIENT_SKIP_MEM;
+       ilt_client->start = line;
+       line += bnx2x_cid_ilt_lines(bp);
+#ifdef BCM_CNIC
+       line += CNIC_ILT_LINES;
+#endif
+       ilt_client->end = line - 1;
+
+       DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
+                                        "flags 0x%x, hw psz %d\n",
+          ilt_client->start,
+          ilt_client->end,
+          ilt_client->page_size,
+          ilt_client->flags,
+          ilog2(ilt_client->page_size >> 12));
+
+       /* QM */
+       if (QM_INIT(bp->qm_cid_count)) {
+               ilt_client = &ilt->clients[ILT_CLIENT_QM];
+               ilt_client->client_num = ILT_CLIENT_QM;
+               ilt_client->page_size = QM_ILT_PAGE_SZ;
+               ilt_client->flags = 0;
+               ilt_client->start = line;
+
+               /* 4 bytes for each cid */
+               line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
+                                                        QM_ILT_PAGE_SZ);
+
+               ilt_client->end = line - 1;
+
+               DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
+                                                "flags 0x%x, hw psz %d\n",
+                  ilt_client->start,
+                  ilt_client->end,
+                  ilt_client->page_size,
+                  ilt_client->flags,
+                  ilog2(ilt_client->page_size >> 12));
+
+       }
+       /* SRC */
+       ilt_client = &ilt->clients[ILT_CLIENT_SRC];
+#ifdef BCM_CNIC
+       ilt_client->client_num = ILT_CLIENT_SRC;
+       ilt_client->page_size = SRC_ILT_PAGE_SZ;
+       ilt_client->flags = 0;
+       ilt_client->start = line;
+       line += SRC_ILT_LINES;
+       ilt_client->end = line - 1;
+
+       DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
+                                        "flags 0x%x, hw psz %d\n",
+          ilt_client->start,
+          ilt_client->end,
+          ilt_client->page_size,
+          ilt_client->flags,
+          ilog2(ilt_client->page_size >> 12));
 
-       /* Wait for completion */
-       rc = bnx2x_wait_ramrod(bp, BNX2X_STATE_OPEN, 0, &(bp->state), 0);
+#else
+       ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
+#endif
 
-       return rc;
+       /* TM */
+       ilt_client = &ilt->clients[ILT_CLIENT_TM];
+#ifdef BCM_CNIC
+       ilt_client->client_num = ILT_CLIENT_TM;
+       ilt_client->page_size = TM_ILT_PAGE_SZ;
+       ilt_client->flags = 0;
+       ilt_client->start = line;
+       line += TM_ILT_LINES;
+       ilt_client->end = line - 1;
+
+       DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
+                                        "flags 0x%x, hw psz %d\n",
+          ilt_client->start,
+          ilt_client->end,
+          ilt_client->page_size,
+          ilt_client->flags,
+          ilog2(ilt_client->page_size >> 12));
+
+#else
+       ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
+#endif
+       BUG_ON(line > ILT_MAX_LINES);
 }
 
-int bnx2x_setup_multi(struct bnx2x *bp, int index)
+/**
+ * bnx2x_pf_q_prep_init - prepare INIT transition parameters
+ *
+ * @bp:                        driver handle
+ * @fp:                        pointer to fastpath
+ * @init_params:       pointer to parameters structure
+ *
+ * parameters configured:
+ *      - HC configuration
+ *      - Queue's CDU context
+ */
+static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
+       struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
 {
-       struct bnx2x_fastpath *fp = &bp->fp[index];
+       /* FCoE Queue uses Default SB, thus has no HC capabilities */
+       if (!IS_FCOE_FP(fp)) {
+               __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
+               __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
+
+               /* If HC is supporterd, enable host coalescing in the transition
+                * to INIT state.
+                */
+               __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
+               __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
+
+               /* HC rate */
+               init_params->rx.hc_rate = bp->rx_ticks ?
+                       (1000000 / bp->rx_ticks) : 0;
+               init_params->tx.hc_rate = bp->tx_ticks ?
+                       (1000000 / bp->tx_ticks) : 0;
 
-       /* reset IGU state */
-       bnx2x_ack_sb(bp, fp->sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
+               /* FW SB ID */
+               init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
+                       fp->fw_sb_id;
 
-       /* SETUP ramrod */
-       fp->state = BNX2X_FP_STATE_OPENING;
-       bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_SETUP, index, 0,
-                     fp->cl_id, 0);
+               /*
+                * CQ index among the SB indices: FCoE clients uses the default
+                * SB, therefore it's different.
+                */
+               init_params->rx.sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
+               init_params->tx.sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
+       }
 
-       /* Wait for completion */
-       return bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_OPEN, index,
-                                &(fp->state), 0);
+       init_params->cxt = &bp->context.vcxt[fp->cid].eth;
 }
 
+/**
+ * bnx2x_setup_queue - setup queue
+ *
+ * @bp:                driver handle
+ * @fp:                pointer to fastpath
+ * @leading:   is leading
+ *
+ * This function performs 2 steps in a Queue state machine
+ *      actually: 1) RESET->INIT 2) INIT->SETUP
+ */
 
-void bnx2x_set_num_queues_msix(struct bnx2x *bp)
+int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
+                      bool leading)
 {
+       struct bnx2x_queue_state_params q_params = {0};
+       struct bnx2x_queue_setup_params *setup_params =
+                                               &q_params.params.setup;
+       int rc;
 
-       switch (bp->multi_mode) {
-       case ETH_RSS_MODE_DISABLED:
-               bp->num_queues = 1;
-               break;
+       /* reset IGU state skip FCoE L2 queue */
+       if (!IS_FCOE_FP(fp))
+               bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
+                            IGU_INT_ENABLE, 0);
 
-       case ETH_RSS_MODE_REGULAR:
-               if (num_queues)
-                       bp->num_queues = min_t(u32, num_queues,
-                                                 BNX2X_MAX_QUEUES(bp));
-               else
-                       bp->num_queues = min_t(u32, num_online_cpus(),
-