bnx2: Update firmware to 6.0.x.
[linux-2.6.git] / drivers / net / bnx2.h
index ab34a5d..efdfbc2 100644 (file)
@@ -295,6 +295,9 @@ struct l2_fhdr {
                #define L2_FHDR_ERRORS_TCP_XSUM         (1<<28)
                #define L2_FHDR_ERRORS_UDP_XSUM         (1<<31)
 
+               #define L2_FHDR_STATUS_USE_RXHASH       \
+                       (L2_FHDR_STATUS_TCP_SEGMENT | L2_FHDR_STATUS_RSS_HASH)
+
        u32 l2_fhdr_hash;
 #if defined(__BIG_ENDIAN)
        u16 l2_fhdr_pkt_len;
@@ -349,12 +352,7 @@ struct l2_fhdr {
 #define BNX2_L2CTX_BD_PRE_READ                         0x00000000
 #define BNX2_L2CTX_CTX_SIZE                            0x00000000
 #define BNX2_L2CTX_CTX_TYPE                            0x00000000
-#define BNX2_L2CTX_LO_WATER_MARK_DEFAULT                4
-#define BNX2_L2CTX_LO_WATER_MARK_SCALE                  4
-#define BNX2_L2CTX_LO_WATER_MARK_DIS                    0
-#define BNX2_L2CTX_HI_WATER_MARK_SHIFT                  4
-#define BNX2_L2CTX_HI_WATER_MARK_SCALE                  16
-#define BNX2_L2CTX_WATER_MARKS_MSK                      0x000000ff
+#define BNX2_L2CTX_FLOW_CTRL_ENABLE                     0x000000ff
 #define BNX2_L2CTX_CTX_TYPE_SIZE_L2                     ((0x20/20)<<16)
 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE             (0xf<<28)
 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED   (0<<28)
@@ -4182,6 +4180,15 @@ struct l2_fhdr {
 #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_IP_ONLY_XI   (2L<<2)
 #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_RES_XI       (3L<<2)
 
+#define BNX2_RLUP_RSS_COMMAND                          0x00002048
+#define BNX2_RLUP_RSS_COMMAND_RSS_IND_TABLE_ADDR        (0xfUL<<0)
+#define BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK            (0xffUL<<4)
+#define BNX2_RLUP_RSS_COMMAND_WRITE                     (1UL<<12)
+#define BNX2_RLUP_RSS_COMMAND_READ                      (1UL<<13)
+#define BNX2_RLUP_RSS_COMMAND_HASH_MASK                         (0x7UL<<14)
+
+#define BNX2_RLUP_RSS_DATA                             0x0000204c
+
 
 /*
  *  rbuf_reg definition
@@ -6074,6 +6081,7 @@ struct l2_fhdr {
 
 #define BNX2_COM_SCRATCH                               0x00120000
 
+#define BNX2_FW_RX_LOW_LATENCY                          0x00120058
 #define BNX2_FW_RX_DROP_COUNT                           0x00120084
 
 
@@ -6347,6 +6355,8 @@ struct l2_fhdr {
 #define BNX2_MCP_SCRATCH                               0x00160000
 #define BNX2_MCP_STATE_P1                               0x0016f9c8
 #define BNX2_MCP_STATE_P0                               0x0016fdc8
+#define BNX2_MCP_STATE_P1_5708                          0x001699c8
+#define BNX2_MCP_STATE_P0_5708                          0x00169dc8
 
 #define BNX2_SHM_HDR_SIGNATURE                         BNX2_MCP_SCRATCH
 #define BNX2_SHM_HDR_SIGNATURE_SIG_MASK                         0xffff0000
@@ -6551,6 +6561,7 @@ struct l2_fhdr {
 
 struct sw_bd {
        struct sk_buff          *skb;
+       struct l2_fhdr          *desc;
        DEFINE_DMA_UNMAP_ADDR(mapping);
 };
 
@@ -6631,9 +6642,12 @@ struct flash_spec {
 
 #define BNX2_MAX_MSIX_HW_VEC   9
 #define BNX2_MAX_MSIX_VEC      9
-#define BNX2_BASE_VEC          0
-#define BNX2_TX_VEC            1
-#define BNX2_TX_INT_NUM        (BNX2_TX_VEC << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT)
+#ifdef BCM_CNIC
+#define BNX2_MIN_MSIX_VEC      2
+#else
+#define BNX2_MIN_MSIX_VEC      1
+#endif
+
 
 struct bnx2_irq {
        irq_handler_t   handler;